JP3276705B2 - Split video monitor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a divided moving picture monitor apparatus having a function of synthesizing a plurality of video signals input from a plurality of TV cameras and the like and dividing and displaying them on the same screen.

[0002]

2. Description of the Related Art In a divided moving picture monitor device, for example, a plurality of video signals input from a monitoring TV camera installed at a plurality of locations are reduced and synthesized on one monitor screen and displayed. ing. For this reason, the monitoring images at a plurality of locations can be simultaneously observed on the same screen. As a method for displaying the divided images, a method for simultaneously displaying a plurality of images in real time (for example, US.PA)
T. 4745479), and a method of sequentially displaying a plurality of images in a non-real time manner on each divided screen at predetermined time intervals. In the former real-time display method, the same number of PIPs (Pi) as the number of input video signals are used in order to reduce and synthesize each input video signal.
ctur in Pictur) unit is used. In each PIP unit, each TV
A video signal input from the camera is digitized, converted into a reduced video signal, and combined. Thereafter, the combined digital video signal is converted into an analog signal, and is output as a video signal as a video signal.

On the other hand, in the latter non-real-time display method, a video signal input from each TV camera is sequentially digitized and converted into a reduced video signal, then converted into an analog signal, and then sequentially divided into individual signals. Video output to the screen. For this reason, with respect to other divided screens for which no video output is performed, a still image is continuously displayed until the next video is displayed.

[0004]

SUMMARY OF THE INVENTION As described above,
In the case of displaying a plurality of videos in real time or non-real time on the same screen in a divided manner, in each case, in order to convert each input video signal into a reduced video,
It is necessary to digitize each video signal once with an A / D converter. In this case, the number of A / D converters to be used needs to be the same as the number of input video signals in the case of real-time display, and one or two are provided in the case of non-real-time display. Just need. Note that when two A / D converters are provided, the display switching time of each divided screen is twice as long as that when only one is provided. The display state becomes easy to see.

[0005] As described above, the non-real-time display is more advantageous in terms of device cost than the real-time display. However, in the display state of the divided video, since the video is displayed intermittently, it is inevitable that the motion is awkward. In the non-real-time display, the time information is naturally reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a divided moving picture monitor device capable of dividing and displaying a plurality of input pictures on a monitor screen in real time at a low cost. I have.

[0007]

[0008]

According to a first aspect of the present invention, there is provided a divided moving picture monitor apparatus, comprising: dividing a plurality of video signals into two sets of first and second video signals;
For two horizontal periods of the first video signal of each set, only the video part for one horizontal period is extracted, and then the second video signal is extracted until the two horizontal periods end.
First video signal combining means for combining two input video signals into one video signal; and time-division multiplexing of the video signals synthesized for each set to form one time-division multiplexed video signal. A multiplexer; digitizing means for digitizing the time-division multiplexed video signal into a time-division multiplexed digital video signal; latching means for latching the time-division multiplexed digital video signal for each set; Separating means for separating the time-division multiplexed digital video signal for each set into first and second digital video signals for each set;
A memory for storing the separated first and second digital video signals in each set, respectively, while counting a horizontal period and a vertical period of the first and second video signals in each set, respectively. Means, for the separated first digital video signal, the count value counted by the counting means, and for the separated second digital video signal, the count value counted by the counting means. to group <br/>, as the video portion of the normal is reproduced, the write control means for controlling writing to the memory, the reading of each digital video signal stored in the memory of one digital video signal A second video signal synthesizing means for synthesizing the digital video signal into an analog signal, And analog means for, is characterized by comprising a video output unit operable to synthesize an analog video signal to the added new video sync signal video output.

According to a second aspect of the present invention, there is provided a divided moving picture monitor apparatus, further comprising: a synchronization separating means for synchronizing and separating a plurality of input video signals; A video section take-out signal creating section that divides the horizontal synchronization and creates a signal to take out only a video section in one horizontal period of each set of first video signals as an operation signal of the first video signal combining section; A / D which generates an integer multiple of the separated horizontal synchronization and generates an A / D conversion clock for each video signal by dividing the main clock.
D-conversion clock generation means, and each time-division sampling period corresponding to each of the A / D conversion clock periods generated for a predetermined set of first and second two video signals, and for each of the two video signals A multiplex signal generating means for generating, as an operation signal of the multiplexer, a multiplex signal whose waveform has been shaped so as to be shorter than each time-division sampling period for the first and second two video signals of another set; , The other set of first and second 2
When each A / D conversion clock for one video signal is applied during each time-division sampling period for one video signal, the respective A / D conversion clocks:
The logical sum of each of the first and second two video signals of the predetermined set and each A / D conversion clock is calculated, and the first and second two video signals of the predetermined set are calculated. During each time-division sampling period, if each A / D conversion clock for the other set of first and second two video signals is applied, the other set of first and second 2 Each pseudo-A / D conversion clock generated during each time-division sampling period for one video signal is generated, and each of the generated pseudo-A / D conversion clocks and the first and second 2 A time-division multiplexed video signal A / D conversion clock generating means for generating a logical sum of each A / D conversion clock for one video signal as an operation clock of the digitizing means; Depending on the clock creation means, A material obtained by inverting the A / D conversion clock created for each signal, and comprising the further comprising a latch signal generation means for the operation clock of said latch means.

[0010]

[0011]

According to the above configuration, in divided video monitor apparatus according to claim 1 of the present invention, first, a plurality of the input video signal has, by the first video signal combining means, first and second 2 It is divided into two sets each composed of one video signal and is subjected to the synthesis processing. In this case, for two horizontal periods of the first video signal of each set, only the video part for one horizontal period is extracted, and then the second video signal is extracted until the two horizontal periods end. Then, the two input video signals are combined into one video signal.

Next, the video signals thus synthesized for each set are time-division multiplexed by a multiplexer. Subsequently, the time-division multiplexed video signal is digitized by digitizing means. Subsequently, the digitized video signal is latched for each set by the latch means. Subsequently, the latched video signal for each set is separated into first and second digital video signals for each set by the separating means. Subsequently, the separated first and second video signals in each set are stored in a memory.

In storing the separated video signals in the memory, first, the counting means counts the horizontal period and the vertical period of each of the first and second video signals in each set. Then, the first digital video signal separated by the writing control means is in accordance with the count value of the counting means,
With respect to the separated second digital video signal, writing to the memory is controlled based on the count value of the counting means so that a proper video portion is reproduced.

Next, each digital video signal stored in the memory is read out by the second video signal combining means and combined into one video signal. Subsequently, the synthesized video signal is converted into an analog signal by the analog conversion means.
Subsequently, a new video synchronizing signal is added by the video output means and the video output is performed. As described above, a plurality of input video signals are surely time-division multiplexed and digitized, so that it is not necessary to provide an A / D converter for each of the plurality of video signals as in the related art. Then, the plurality of input video signals are surely divided and displayed on the same screen.

According to a second aspect of the present invention, there is provided the divided moving image monitor, wherein the first video signal synthesizing means, the multiplexer, the digitizing means, and the latch are provided. An operation clock for reliably executing each operation of the means is created as follows. First, the synchronization separation unit performs synchronization separation of a plurality of input video signals. Subsequently, the separated horizontal synchronization is frequency-divided by the video section extraction signal generating means, and a signal for extracting only the video section of each set of the first video signals in one horizontal period is generated. Therefore, the first video signal synthesizing unit extracts only the video portion of each set of the first video signal in one horizontal period according to the video portion extraction signal, and then ends the two horizontal periods of the first video signal. Until the second video signal is extracted, the two input video signals are combined.

A / D conversion clock generation means generates a main clock of an integer multiple of the separated horizontal synchronization, and further divides the main clock to generate an A / D conversion clock for each video signal. Is done. The multiplex signal generating means generates a predetermined set of first and second sets.
Each of the A / D conversion clock periods created for the two video signals, and each time-division sampling period for the two video signals corresponds to another set of the first and second sets.
A multiplex signal whose waveform is shaped so as to be shorter than each time-division sampling period for the two video signals is created. Therefore, the multiplexer time-division multiplexes the video signals synthesized for each group according to the multiplex signal.

The A / D conversion clock for digitizing the time-division multiplexed video signal is generated by the time-division multiplexed video signal A / D conversion clock generation means.
The time-division multiplexed video signal A / D conversion clock is created as follows. That is, during each time-division sampling period of the first and second two video signals of the other set other than the predetermined set, each A
When the / D conversion clock is applied, the respective A / D
A logical sum of the converted clock and each of the A / D conversion clocks for the first and second two video signals of the predetermined set is used as the time-division multiplexed video signal A / D conversion clock. .

Also, during each time-division sampling period for the predetermined set of first and second two video signals,
When each A / D conversion clock for the other set of the first and second two video signals is applied, each time of the other set of the first and second two video signals is used. Each pseudo A / D conversion clock generated during the divided sampling period is generated, and each of the generated pseudo A / D conversion clocks and each A of the predetermined set of the first and second video signals are set. A logical sum with the / D conversion clock is created as a time division multiplexed video signal A / D conversion clock.

Therefore, the digitizing means digitizes the time-division multiplexed video signal in accordance with the time-division multiplexed video signal A / D conversion clock created as described above.
As a result, the time-division multiplexed video signal is reliably digitized. Further, the latch signal generating means generates a latch signal obtained by inverting the A / D conversion clock generated for each video signal. Therefore, according to the created latch signal, the latch means latches the time-division multiplexed digital video signal.

As described above, the respective operations of the first video signal synthesizing means, the multiplexer, the digitizing means, and the latch means in the divided moving picture monitor device according to the second aspect are reliably executed. Is done.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a block diagram showing an example of a circuit configuration of a divided moving image monitor device according to the present invention, showing a case where the number of divided screens is four. In this device,
Four input asynchronous camera signals A, B, C, D
(CAMERA IN AD) to the main signals A, B (M
AIN) and sub-signals C and D (SUB) are processed separately. Also, in the set of MAIN,
The signal A is set as a master and the signal B is set as a slave (sla).
ve), and similarly, in the set of SUBs, the signal C is processed as a master and the signal D is processed as a slave.

Next, according to the circuit shown in FIG.
The operation from the reduction of one input camera signal to the video output will be described. First, the input four camera signals A, B, C, and D are respectively supplied to buffers (B)
→ Pre-filter (LPF1; a low-pass filter, which is provided for removing noise in advance for the subsequent quantization) → Clamp circuit (CP, which is provided for keeping the input level constant) , MAIN signals A and B are input to the changeover switch SW1, and the SUB signals C and D are input to the changeover switch SW2.

Subsequently, by switching the changeover switch SW1, the MAIN signals A and B are synthesized, and
When the changeover switch SW2 is switched, the SUB signals C and D are combined. Each synthesized video signal is further input to a multiplexer (MPX). In the multiplexer (MPX), time-division multiplexing processing is performed on each of the input composite video signals to generate a time-division multiplexed video signal. Further, the time division multiplexed video signal is A
It is digitized by a / D conversion circuit (A / D) and latched by latch circuits A and B and latch circuits C and D. Then, the changeover switch SW3 and the changeover switch S
Each video signal A and B digitized by W4
And video signals C and D, and are written as video data in the respective memories (MEMORY) A to D respectively.

Next, the four video data written in the memories A to D are sequentially taken out of the memories by a selector (SELECTTER) and combined into one video signal. Then, the synthesized video signal is converted into an analog signal by a D / A conversion circuit (D / A), and after high-frequency noise is removed by a post-filter (LPF2), the signal is synchronized by an adder (+). Signal generation circuit (SYNC GENER
ATER), a new horizontal synchronizing signal (HD) and a new vertical synchronizing signal (VD) are added to the buffer (B).
And video output.

The clamp circuit (CP) has a constant input level, and the A / D conversion circuit (A / D) has a constant quantization level.
A reference voltage (REF.VOLTAGE) is input. On the other hand, separately from the above-described processing of reducing and synthesizing each of the four input video signals and outputting the video, each of the four input camera signals A, B, C, and D is a synchronization separation circuit in a circuit block G. (SYNC. SEPA)
The horizontal synchronization signal (HD) and the vertical synchronization signal (VD) are created. Then, based on the horizontal synchronizing signal (HD) that is created, the clock generating circuit (P
LL, ie, a phase-locked loop)
Then, a main clock (MAIN CLK A to D; see FIG. 3) of an integral multiple of the horizontal frequency (this value is determined by the resolution of the image on the screen) is created, and each circuit block A Is input to

In each of the circuit blocks A for the MAIN signals A and B, each main clock generated for each of the input video signals A and B is frequency-divided, and an A / D conversion clock for each signal and a multiplexer. And a multiplex clock (MPX CLK) serving as an operation clock for the time-division multiplexing process in step (1).
Here, a multiplex clock is created by taking the AND (logical product) of the created main clock that has been frequency-divided by 更 に and the frequency that has been further frequency-divided by ２. In addition, the inverted clock of the main clock and the AND of the created multiplex clock
By taking (logical product), an A / D conversion clock is created.

Next, the respective A / D conversion clocks for the generated MAIN signals A and B are switched by the changeover switch SW5 in the circuit block D,
Input to the circuit block E. Also, the created MAI
The multiplex clocks for the N signals A and B are switched by the switch SW6 in the circuit block E and input to the multiplexer.

Similarly, for each of the SUB signals C and D, each of the A
A / D conversion clock is created. Then, each created A / D conversion clock is switched by the changeover switch SW7 in the circuit block D and is input to the circuit block E. No multiplex clock is created for the SUB signals C and D.

In the circuit block E, the changeover switch S
Multiplex clock from W6 (MPX CL
K. That is, after the waveforms of the multiplex clocks for the signals A and B are shaped by the shape circuit (SHAPE), the signals are latched by the D flip-flop (D). Further, the phases of the signal A and the signal B input from the changeover switch SW5 are compared with the respective A / D conversion clocks, and the A / D conversion clock of the time division multiplexed signal in the A / D converter (A / D) is compared. Is created A / D
The signals are output to the converter (note that the states of the signals g to l in each part of the circuit block E will be described in detail with reference to FIG. 3).

Also, an inverted signal of the A / D conversion clock for the MAIN signal A and the signal B input from the changeover switch SW5, and the A / D conversion clock for the signal C and the signal D input from the changeover switch SW7. The inverted signal is output to each latch circuit as a latch clock (LATCH CLK AB and CD) which is an operation clock of the latch circuits A and B and the latch circuits C and D, respectively.

In the circuit block B, the generated MAIN
A / D conversion clocks for signals A and B and SUB signals C and D are supplied to a horizontal address counter (H C
OUTER) counts and signals A to D in the memories A and B, and the memories C and D, respectively.
Horizontal write address (MEMORY WRITE)
E ADDRESS) is determined. A vertical address counter (V COUNTER) counts a clock obtained by dividing the horizontal synchronization signal (HD) by 、, and a vertical write address (MEMORY WRITE A) is counted.
DDRESS) is determined. Then, each video data is written to the memories A and C according to the write addresses for the signals A and C on the main side of the MAIN and SUB determined in this way. The write addresses determined for the signals B and D on the slave side of MAIN and SUB are:
It is input to the circuit block F.

As described above, the circuit block F includes M
Write address data for the memories B and D, which are determined for the signals B and D on the slave side of AIN and SUB, are input. And the signal B
The write address data for
It is latched and compared by the control signal LINE SW1 generated in (described later), and the control signal LINE SW
By taking the logical product with W1, the write timing signal (WRITE ENABLE) is created. The write address data for the signal D is
The signal D is latched and compared by the A / D conversion clock generated in the circuit block A, and a write timing signal (WRITE ENABLE) is generated. In this way, the memories A to A are assigned to the determined write address in accordance with the respective write timings.
D is written into the video data. Writing of the signal B and the signal D to the memory will be described in detail with reference to FIG.

The circuit block C is provided only for the signals A and C of MAIN. Then, in the circuit block C, the signals A and C on the main side (master) of MAIN and SUB are those horizontal synchronization signals (H
A signal WHD (WIDE HD; see FIG. 2) obtained by shaping the waveform of D) by a shape circuit (SHAPE);
By taking the logical product (AND) of the 分 frequency-divided signals, control signals (LINE SW1 and LINE SW) for switching the changeover switches SW1 and SW2 are obtained.
SW2) is created. Then, in accordance with the generated control signal LINE SW1, the changeover switch SW1
, Changeover switch SW5, changeover switch SW
6, and each switch of the changeover switch SW3 is switched. Further, the changeover switch SW2 and the changeover switch SW4 are switched according to the created control signal LINE SW2. The multiplex clock created for the MAIN signal A described above is
It operates in response to the control signal LINE SW1.

On the other hand, when reading the video data A to D written in the memories A to D, the reading is controlled by a memory controller (MEMORY CONTROLLER). That is, the synchronizing signal generation circuit (SYN
The horizontal address counter (H COUNTER) is monitored according to a new horizontal synchronizing signal (HD) and a vertical synchronizing signal (VD) created by the C GENERATER) and a main clock created based on the horizontal synchronizing signal (HD). The read address in the horizontal direction on the screen and the vertical address counter (V COUNTER) are controlled to count the read address in the vertical direction. Then, the respective count values are compared, and the read corresponding area is detected. Then, according to the detected address of the read applicable area, the read timing (REA)
D ENABLE), and the reading of each video data is performed. At this time, the read speed of the video data written in each of the memories A to D is controlled by the memory controller in order to reduce and combine the input video signals.

FIG. 2 shows the input camera signals A and B shown in FIG.
And their composite signals, and the input camera signals C and D
FIG. 3 is a waveform diagram showing respective waveforms of the synthesized signals and a waveform of a control signal for creating the synthesized signal.
In the figure, the upper half shows input camera signals A and B on the main side (MAIN SIDE) and waveforms of other related signals, and the lower half shows input camera signals C and D on the sub side SUB SIDE. The waveforms of other related signals are shown.

(A) is the master of MAIN.
The input waveform of signal A (CAMERA IN A) is
(B) shows the waveform of the signal “WIDE HD A” for extracting only the video portion from the signal A, and (c) shows the MAIN
Slave signal B (CAMERA IN B)
(D) shows the waveform of the signal “WIDE HD B” for extracting only the video part from the signal B,
(E) shows a circuit block C for the signal A shown in FIG. 1 for performing switching control of the changeover switch SW1.
The waveform of the control signal LINE SW1 created by
(F) shows the composite camera signal A.1 output from the switch SW1 which is switched according to the control signal LINESW1.
B (MIXED AB) respectively.

As shown in the figure, “WIDE H” in FIG.
For both the "DA" and "WIDEHD B" signals of (d), the respective horizontal synchronizations are waveform-shaped so that the video portion and the synchronization signal portion of the corresponding signals A and B can be distinguished. . Also, the control signal “LINE SW1” is
The signal is generated based on the signal “WIDE HD A” in FIG. 2B, and is a signal from which only the video portion of one horizontal period in the two horizontal periods of the signal A can be extracted. That is, 1 in this case
DUTY that takes out only the video part for the horizontal period is 50%
It is as follows. Accordingly, “MIXED” in FIG.
A. The waveform “B” includes the control signal “LINE” shown in FIG.
While the signal of "SW1" is ON, the video portion of the signal A (indicated as "nfh LINE OF A SIGNAL" in the figure; that is, a video signal corresponding to the nth horizontal scanning line of the signal A). Only the waveform
When the signal is turned off, the signal B (mth line, (m
Shown as +1) th line. That is, the waveform of the video signal corresponding to the m-th horizontal scanning line for the signal B, the subsequent horizontal synchronization signal, and a continuous signal of the video signal corresponding to the (m + 1) -th horizontal scanning line) Become.

As described above, the control signal "LINE SW"
1 "is in the OFF state during the period in which the period of the slave signal B is equal to or longer than the one horizontal period. As the slave signal B at B,
A halfway camera signal over the horizontal period is obtained. Therefore, regarding the slave signal B, the above “WID
When the horizontal address counter (H COUNTER) of the circuit block B in FIG. 1 is counted and written on the memory B based on the position information obtained from “E HD A” and “WIDE HD B”, (g) in FIG. Signal REPRODUCING SIGNA for one horizontal period of signal B shown in FIG.
Writing is controlled so that L mth line, that is, the signal B becomes a normal video signal. As a result, the slave signal B, which is once combined with the signal A and becomes an odd camera signal that straddles two horizontal periods, is stored in the memory B as a regular camera signal, that is, (m + 1) th The line is written as a signal followed by the mth line.

In the waveform shown in (g), "OVE
The signal portion indicated as “RLAP PART” is a composite signal A. The portion where the signal B to be newly written overlaps the count address for B of B and is written is shown. (H) is the SUB master (mast
er) The input waveform of signal C (CAMERA IN C), (i) the waveform of signal “WIDE HD C” created to extract only the video portion from signal C, and (j)
Is a SUB slave signal D (CAMERA).
IND), (k) creates a waveform of a signal “WIDE HD D” for extracting only a video portion from the signal D, and (l) creates a waveform for controlling the changeover switch SW2. Control signal LINE SW2
(M) shows the composite camera signal C.2 output from the changeover switch SW2 which is switched according to the control signal LINE SW2. D (MIXED CD).

Similarly to the signal on the MAIN side described above, the synthesized camera signal C.I. The slave signal D at D is an odd camera signal over the two horizontal periods. Therefore, similarly, when writing data on the memory D, the signal REPROD of one horizontal period of the signal D shown in FIG.
Writing is controlled so that the UCE SIGNAL mth line, that is, the signal D becomes a new video signal. As a result, the slave signal D which is combined with the signal C to become a halfway camera signal once over two horizontal periods
Is written on the memory D as an official camera signal.

(O) shows the combined camera signals (MIXED AB and MIXED) shown in (f) and (m) above.
C. D) is time-division multiplexed by the multiplexer (MPX) shown in FIG. 1 to obtain a time-division multiplexed signal (MULTI).
PLEXED A, B, C, D). In the figure, “x” indicates a switching point by the multiplexer. And, as is clear from the figure,
Between “× to ×”, two signals composed of a combination of any one of the signals A and B on the MAIN side and any one of the signals C and D on the SUB side are time-division multiplexed signals. And transmitted.

FIG. 3 is a timing chart showing the operation timing of each control clock used in the divided moving picture monitor shown in FIG. In the figure, the vertical line dividing the left and right charts indicates the switching point of the changeover switch SW1 by the control signal “LINE SW1”. (A) shows the waveform of the main clock (MAINCLK A / B) created by each circuit block G shown in FIG. 1 for the input camera signals A and B of MAIN,
(B) is a multiplex signal for switching between two signals A and D and two signals B and C created by dividing the main clock shown in (a) by the respective circuit blocks A shown in FIG. MPX A / D, B / C). That is, during the period when the pulse is rising, the signal A
The signal D (or the signal C) is transmitted during a period when the signal (or the signal B) is transmitted and the pulse is not raised. (C) is an A / D conversion clock (A / D CLK) for signals A and B created by dividing the main clock shown in (a) by the respective circuit blocks A shown in FIG. for A / B). That is, during the period when the pulse is rising, the signal A
A / D conversion of (or signal B) is performed for the time being. (D) shows an analog signal (MPXED ANALOG SI) created by time-division multiplexing according to the multiplex signal shown in (b).
GNAL A / D, B / C).

Next, (e) shows the main clock (MAIN CLK) generated by the respective circuit blocks G shown in FIG. 1 for the input camera signals C and D of SUB.
D / C), and (f) is an A / D conversion signal for the signals D and C created by dividing the frequency of the main clock shown in (e) by the circuit block A shown in FIG. The waveform of the clock (A / D CLK for D / C) is shown. Next, (g) to (l) show the state of signals in each part of the circuit block E shown in FIG.
(G) shows the multiplex signal (MPX) shown in (b).
A / D, B / C) during the period when the pulse is raised (Re
The multiplex signal (S) whose waveform has been shaped so that the produced area is longer than that shown in FIG.
HAPED MPX).

(H) is a signal obtained by latching the multiplex signal shown in (g) by a D-flip-flop in the circuit block E shown in FIG. 1 in accordance with the A / D conversion clock shown in (f). State (f)
The clock for A / D conversion with respect to the signals D and C shown in FIG. That is, when the pulse is "H", it is in the data sampling period, and when it is "L", it is detected that it is out of the data sampling period.
(I) is a pseudo A / D conversion clock (Reproduced A / D CLK) for signals D and C created by inverting the multiplex signal shown in (g).
for D / C). And
(J) shows the state of the signal obtained by taking the logical product (AND) of (h) and (i), and the signal C is raised only when the data sampling period of the signal A and the signal B starts.
And a pseudo A / D clock for the signal D.

On the other hand, A / A of signals C and D with respect to the outside of the data sampling period of signals A and B
The D-converted clock has the signal state shown in (l), which is the signal state (k) created by inverting the signal in the latch state shown in (h) and the signal state shown in (f). It is obtained by taking a logical product (AND). here,
Since the signal state shown in (k) is set to “H” only outside the data sampling period of the signals A and B, in this case, the A / A for the signals D and C shown in (f) is A clock for D conversion is output. And two signals indicated by (j) and (l):
By taking the logical sum (OR) of the signal A and the signal B shown in (c) with the A / D conversion clock,
As shown in (m), a total A / D conversion clock of the time division multiplexed signal transmitted from the multiplexer is created.

In the signal state shown by (m), the range of movement of the pulse indicated by the broken line is the A / D of the signal C and the signal D with respect to the outside of the data period of the signal A and the signal B.
The range in which the pulse of the conversion clock can be moved is shown. The synthesized camera signal A. B and the synthesized camera signal C. D can surely perform A / D conversion even after it becomes a time division multiplexed signal. As a result,
As shown in (n), digitized time-division multiplexed signal data (Digitized DATA) is obtained.

The latch circuit A.1 shown in FIG. B and the latch circuit C. The latch clock required to latch the digitized time-division multiplexed signal data used in D is created as follows. Latch clock (LATCH CLK A / B) for signal A and signal B
As shown in (o), the signal A shown in (c)
And the latch clock (LATCH CLK C / D) for the signals C and D is created by inverting the A / D conversion clock for the signal B.
As shown in (p), it is created by inverting the A / D conversion clock for the signals C and D shown in (f).

In the signal state shown in (p), the pulse moving range indicated by the broken line indicates the pulse moving range of the A / D conversion clock for the signals C and D. The synthesized camera signal A. B and the synthesized camera signal C. D becomes a time-division multiplexed signal, and can be reliably latched in a state where it has been A / D converted and digitized.
To D can be surely performed.

[0049]

[0050]

Effect of the Invention According to the present claim 1 and the invention according to claim 2, a plurality of video signals input are combined for every two video signals are converted into a single time division multiplexed video signal digitization After that, they are separated and developed as individual video data on a memory. Then, the developed individual video data is read out from the memory and re-synthesized, converted to analog, added with a new synchronization signal, and output as video.

Therefore, it is not necessary to provide an A / D converter for each input video signal, so that the cost of the apparatus is greatly reduced and a plurality of input video signals can be surely displayed on the same screen in real time. Is displayed. For this reason, it is possible to provide an inexpensive divided moving image monitoring device without considerably lowering the performance.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a circuit configuration of a divided moving image monitoring device according to the present invention.

FIG. 2 is a diagram showing input camera signals A and B shown in FIG. 1, their composite signals, input camera signals C and D, their respective waveforms, and control signals for generating such composite signals. FIG. 4 is a waveform diagram showing a waveform.

FIG. 3 is a timing chart showing operation timing of each control clock used in the divided moving image monitoring device shown in FIG.

[Explanation of symbols]

SW changeover switch MPX multiplexer A / D A / D conversion circuit LATCH latch circuit MEMORY memory SELECTOR selector MEMORY CONTROLLER memory controller SYNC. SEPA Synchronous separation circuit H COUNTER horizontal counter V COUNTER vertical counter

Claims (2)

(57) [Claims] 1. A divided moving picture monitor device for reducing and synthesizing a plurality of input video signals and dividing and displaying the plurality of video signals on the same screen, wherein the plurality of video signals are converted from first and second two video signals. After the two horizontal periods of the first video signal of each set are taken out, only the video part for one horizontal period is taken out, and the second horizontal period is completed until the two horizontal periods end. A first video signal synthesizing means for extracting two input video signals into one video signal, and a time-division multiplexing of the video signals synthesized for each set to obtain one video signal.
A multiplexer for digitizing the time-division multiplexed video signal, digitizing means for digitizing the time-division multiplexed video signal to generate a time-division multiplexed digital video signal, and a latch for latching the time-division multiplexed digital video signal for each set Means for separating the latched time-division multiplexed digital video signals for each set into first and second digital video signals for each set; and separated first and second digital video signals for each set. Counting means for counting the horizontal period and the vertical period of each of the first and second video signals in each set, and a memory for storing the first and second video signals in each set. For the digital video signal, according to the count value counted by the counting means, and to the separated second digital video signal Information, on the basis of the counted count value by said counting means, as video portion of the normal is reproduced, the write control means for controlling writing to the memory, the digital video signal stored in said memory A second video signal synthesizing means for reading out the digital video signal and synthesizing the digital video signal into one digital video signal; an analog converting means for converting the synthesized digital video signal into an analog signal to obtain a synthesized analog video signal; Video output means for adding a video synchronization signal to output video. 2. The divided moving picture monitor device according to claim 1 , further comprising: a synchronization separation means for synchronizing and separating each of a plurality of input video signals; A signal for extracting only the video portion of one horizontal period of the first video signal is referred to as the first video signal.
A video section extraction signal generating means for generating an operation signal of the video signal synthesizing means, and a main clock which is an integral multiple of each separated horizontal synchronization is generated, the main clock is frequency-divided, and an A / D
A / D conversion clock generation means for generating a conversion clock; and two A / D conversion clock periods corresponding to the respective A / D conversion clock periods generated for a predetermined set of first and second two video signals. Is generated as an operation signal of the multiplexer, the waveform of which is shaped so that each time-division sampling period is shorter than each time-division sampling period of the other two video signals. A multiplex signal generating means for performing the above operation, wherein each of the A / D conversion clocks for the video signals is applied during the respective time-division sampling periods for the first and second two video signals of the other set. Calculated the logical sum of each A / D conversion clock and each A / D conversion clock for the first and second two video signals of the predetermined set. During each time-division sampling period for a predetermined set of the first and second two video signals, each A / D conversion for the other set of the first and second two video signals is performed. In the case where a clock is applied, each pseudo A / D conversion clock applied during each time-division sampling period for another set of the first and second two video signals is created, and each created A / D conversion clock is created. A pseudo A / D conversion clock;
And a time-division multiplexed video signal A / D for generating a logical sum of each of the A / D conversion clocks of the two video signals as an operation clock of the digitizing means.
Conversion clock generating means; and latch signal generating means for setting the inverted A / D conversion clock generated for each video signal by the A / D conversion clock generating means as an operation clock of the latch means. A divided moving picture monitor device characterized by the above-mentioned.