JPH0370376A - Driving method for active matrix liquid crystal display device - Google Patents

Abstract

PURPOSE:To display an ID-TV image without varying the driving frequency of a drain driving circuit by separating an ID-TV signal into odd-numbered horizontal lines and even-numbered horizontal lines, making them coincident in output timing and putting the frequency back to the original frequency, and performing doublespeed line sequential driving according to the signals of the odd-numbered and even-numbered horizontal lines. CONSTITUTION:The output signals of tri-state buffers 15a-15c are led out of a common output line DL and sent as a drain line driving signal Di to a liquid crystal display device. Here, an ID (Improved Definition)-TV signal which has a horizontal frequency twice as high as that of a video signal is separated into the odd-numbered and even-numbered horizontal lines and after they are made coincident in output timing, the conversion to the frequency of the original signal is performed, thereby performing the double-speed line sequential driving of the liquid crystal display device with the frequency-converted video signals of the odd-numbered and even-numbered horizontal lines. Consequently, the ID-TV signal can be driven without making the driving frequency of a drain driving circuit different from that in NTSC driving.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for driving an active matrix liquid crystal display device, which uses an ID-TV signal to drive an active matrix liquid crystal display device.

[Prior Art] In recent years, CRT-type TVs have been used to display high-resolution images.
n) A system called TV has been developed. This method is characterized in that data is compressed by making extensive use of field memories and line memories, and 480 lines are sequentially driven in each field.

Since the video signal in the ID-TV system has 240 scanning lines in each field in the NTSC system,
The signal has a horizontal frequency twice that of the TSC signal.

Therefore, in a liquid crystal display device, it is conceivable to adopt the ID-TV method described above as a means for displaying a high-resolution image.

[Problems to be Solved by the Invention] However, when attempting to display the 1D-RV number on an active matrix liquid crystal display device as described above,
The sampling frequency of the drain drive circuit and the frequency conditions of the timing system must all be set to twice the frequency when driving the NTSC signal.

Therefore, if the ID-TV signal exceeds the driving frequency range of the drain drive circuit, the liquid crystal display device
There was a problem that images of D-TV signals could not be displayed.

The present invention has been made in view of the above-mentioned circumstances.
- It is an object of the present invention to provide a method for driving an active matrix liquid crystal display device capable of driving a TV signal.

[Means and effects for solving the problem] The present invention separates an ID-TV signal having a horizontal frequency twice that of a video signal into odd horizontal lines and even horizontal lines, and divides one of the signals into 172 horizontal lines. After delaying the period to match the output timing, converting to the same frequency as the horizontal frequency of the original signal, and sampling the frequency-converted video signals of odd horizontal lines and even horizontal lines to generate a signal with a 1/2 horizontal period. This is a method for driving an active matrix liquid crystal display device, which is characterized in that the active matrix liquid crystal display device is driven in double-speed line sequential driving mode by alternating at intervals. By separating the ID-TV signal into odd-numbered horizontal lines and even-numbered horizontal lines as described above, and returning the output timing to the original frequency by matching the output timing, the active matrix can be generated without changing the driving frequency of the drain driving circuit. It becomes possible to drive a liquid crystal display device.

[Example Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a horizontal driver, ie, a drain drive circuit, for 1-bit signal processing. In the figure, Ll is a 60-bit dynamic shift register that reads the start timing signal ST using the sampling clock φ1 and sequentially shifts it. Each bit output of this shift register 11 is input as a sampling pulse φS to the control terminal of the switch circuit SWl directly and via the switch circuit SW2.

The above switch circuit SWI includes three switch elements S Wl
a, S Wlb, and S Wlc, the switch circuit SW2 also includes two switch elements 5W2a,
It is composed of 5W2b. This switch circuit SW
A timing pulse TPI whose level is inverted every Ia is input to the control terminal of the second switch element 5W2a, and the timing pulse TPI is inputted via the inverter 12 to the control terminal of the switch element 5W2b. On the other hand, the switch element 5W1a in the switch circuit SWI receives a sampling pulse φ directly input from the shift register 11.
The switching is controlled by S, and the switch cables 5Wlb, 5W
1c is switched and controlled by a sampling pulse φS applied via switch elements 5W2a and 5W2b.

A signal line 13a is connected to one end of the switch element 5Wla.
The first video signal VDI is inputted via the signal line 13b, and the second video signal VD2 is inputted to one end of the switch elements 5Wlb and 5W1c via the signal line 13b.

The details of the circuit for generating the first video signal VDI and the second video signal VD2 will be described later. And the above-mentioned switch elements S W Ia, S W lb, S W 1G
)flb The signal taken out from the end is input to the sample and hold circuit 4.

This sample hold circuit (4 is tri-state buffers y15a, 15b, 15c and capacitor Lea).

IGb, 16c, and the above switch cable 5Wla
.

Signals from 5WLb and 5W1c are input to tristate buffers 15a, 15b, and 15c.

And Tony cheat buffer 15a, 15b
, a capacitor lea between the input end f of 15c and the common line 17.

(6b, 16c are connected. The tristate balanoor 15a is gate-controlled by the output enable signal OEL, and the tristate buffer 15b.

15c is gate-controlled by output enable signals 0E2a and 0E2b applied via switch circuit SW3. The switch circuit SW3 includes a switch element 5W3a
, 5W3b, and the control a of the switch cable 5W3a
The above timing pulse TPI is connected to the l terminal of the inverter 18.
The timing pulse TPI is input to the control terminal of the switch element 5W3b through the inverter 18. 19. Then, an enable signal 0E2a is inputted to the gate terminal of the tri-state buffer 1.5b by the output taken out via the switch cable 5W3a,
Output enable signal 0E2b taken out via switch element 5W3b is input to gate terminal -1 of tristate buffer 15c.

The output signals of the tristate buffers 15a to 15c are taken out from a common output line DL and sent to the active matrix liquid crystal display device as a drain line drive signal Di.

Next, a circuit for creating the first video signal VDI and second video signal VD2 input to the lines L3a and L3b will be explained with reference to FIG. 2. The circuits that create the first @ image signal VDI and the second video signal VD2 are an odd line output circuit 21a and an even line output circuit 2, as shown in the figure.
1b, and is manually operated from the input terminal 20.
Divide the signal into odd lines and even lines and output.

The odd line output circuit 21a is an analog switch 22a.
, 23a, 1/2H delay line 24. A/D conversion circuit 25a1 line memory 28a, D/A conversion circuit 27
It is mainly composed of a. Daylay line 2 above
4 is supplied with an ID-TV signal from the input terminal 20 via an analog switch 22a, and is also supplied with a ground potential via an analog switch 23a. The 1/2H timing pulse TP is applied to the control terminal of the analog switch 22a from the input terminal 30 via the inverter 28a, and the timing pulse TP is applied to the control terminal of the analog switch 23a via the inverters 28a, 28b.
given through. That is, the timing pulse TP
The analog switches 22a and 23a are alternately selected, and the ID-TV signal or the ground potential is input to the delay line 24. The above timing pulse TP is
Each horizontal line of ID-TV signal (NTSC 1/2H)
The signal level is inverted every time, and becomes a low level when the line is an odd number, and a high level when it is an even line.The odd line of the ID-TV signal is selected by the analog switch 22a and input to the delay line 24. The output signal of this delay line 24 is sent to the A/D conversion circuit 25.
It is taken out as an odd line output, that is, a first video signal VDI, via the a1 line memory 26a and the D/A conversion circuit 27a.

On the other hand, the even line output circuit 21b mainly includes an analog switch 22b, an SA/D conversion circuit 25b, a line memory 26b, and a D/A conversion circuit 27b. The A/D conversion circuit 25b is supplied with an ID-TV signal from the input terminal 20 via an analog switch 22b, and is also supplied with a ground potential via an analog switch 23b. The 1/2H timing pulse TP is directly input to the control terminal of the analog switch 22b, and the timing pulse TP is applied via the inverter 29 to the control terminal of the analog switch 23b. That is, the analog switches 22b and 23b are alternately selected by the timing pulse TP, and the ID-TV
A signal or ground potential is input to the A/D conversion circuit 25b. Even lines of the I D-TV signal are selected by the analog switch 22a, and outputted as an even line output, that is, a second video signal VD2, via the A/D conversion circuit 25b, 1-line memory 2Gb, and the D/A conversion circuit 27b. .

In the video signal generation circuit shown in FIG. 2 above, the input terminal 20
The ID-TV signal shown in FIG. 3(a) is input manually.

This ID-TV signal is a double-speed converted NTSC video signal, and has a horizontal frequency twice that of the NTSC system. The above ID-TV signal is shown in FIG.
), the odd lines A, B are given in the order of lines A, A'B, B', .

. . . and even number lines A', B', . . . are extracted separately. In other words, if the input terminal 20 is
At the timing when the D-TV signal is manually input, the timing pulse TP becomes low level. As a result, the output of the inverter 12a in the odd line output circuit 21a becomes high level, the analog switch 22a is turned on, and the output of the odd line A is turned on.
and input into the delay line 24. At this time, the output of the inverter 28b is at a low level, and the analog switch 23a is turned off. The video signal input to the delay line 24 is delayed by 1/2H and output to the A/D conversion circuit 25a.

At this time, the ID of the next even line A' is input to the input terminal 20.
When the TV signal is input, the timing pulse TP applied to the input terminal 30 becomes high level. Therefore,
The output of the inverter 28a becomes low level and the analog switch 22a is turned off, and the analog switch 22b of the even line output circuit 21b is turned on, so that the video signal of the even line A' is manually input to the A/D conversion circuit 25b. Ru. Since the even line output circuit 21b is not provided with a delay line, the video signal of the even line A' is immediately input to the A/D conversion circuit 25b. tt
The timing of the video signal of the odd line A manually input to the A/D conversion circuit 25a and the video signal of the even line A' input to the A/D conversion circuit 25b coincides.

The video signals inputted to the A/D conversion circuits 25a and 25b are respectively converted into digital data and inputted to the line memories 28a and 28b.

This line memory 2 (ia, 26b) drives the frequency at the original 1 horizontal frequency (NTSC) by driving the write cycle at 1/2 the period of the read cycle.
can be converted to . The above line memory 2 [ia,
The signal output from 28b is sent to the D/A conversion circuit 27a.
, 27b, it is returned to an analog signal. That is,
As shown in FIGS. 3(b) and 3(c), the ID-TV signals input to the input terminal 20 are signals of odd lines A, B, . . . and even lines A', B', . The D/A conversion circuits 27a and 27b send the signal to the drain drive circuit shown in FIG. 1 as a first video signal VDL and a second video signal VD2.

The drain drive circuit of FIG.
The double-speed line sequential drive is performed based on I and the second video signal VD2, and the details thereof will be explained below with reference to the timing chart of FIG. 4.

In the drain drive circuit of FIG. 1, the signal line 13a
The first video signal VDI of the odd line shown in FIG. 4(a) sent from the video signal generation circuit shown in FIG.
(A, B, C,...) is input, and the signal line 13b
The second video signal (A') of the even line shown in FIG.
, B', C',...) are input. Further, the shift register 11 is inputted with a start timing signal ST and a sampling clock φ1 shown in FIG. The shift register 11 reads the start timing signal ST using the sampling clock φt, sequentially shifts it, and generates the sampling pulse φS shown in FIG. By this sampling pulse φS, first,
The switch element 5Wla in the switch circuit SWi is turned on, and the odd line video signal A input to the signal line 13a is sent to the sample hold circuit 14 and stored in the capacitor 1 (ia). The output enable signal OEI shown in FIG. 1
Video signals A and B of odd lines shown in 5a to (e) of the same figure.
, C1, . . . are sequentially output.

On the other hand, the timing pulse TPI shown in FIG. 4(g) is applied directly and via the inverter 12 to the switch circuit SW2. This timing pulse TPI is a pulse whose signal level is inverted every time a horizontal synchronization signal is applied. When this timing pulse TPI is at a high level, the switch wire 5W2a of the switch circuit SW2 is turned on, and the sampling pulse φS output from the shift register 11 is taken out as φSa as shown in FIG. 4(k). Further, when the timing pulse TPI is at a low level, the output of the inverter 12 is at a level of 1, the switch element 5W2b is turned on, and the shift register 11 is turned on.
The sampling pulse φS output from is shown in Fig. 4 (N).
It is taken out as φsb as shown in . That is, the sampling pulse φS is taken out alternately as φSa and φSb by the switch circuit SW2.

First, the switching element 5W1b of the switching circuit SWI is turned on by the sampling pulse φSa outputted via the switching element 5W2a, and the even line video signal A' input to the signal line 13b is sent to the sample hold circuit 14. It is accumulated in capacitor 113b. Next, the sampling pulse φsb outputted via the switching element 5W2b turns on the switching element 5Wlc of the switching circuit SWl, and the next even line video signal B' input to the signal line 1.3b is sent to the sample hold circuit 14. is stored in the capacitor 16c.

The video signals stored in the capacitors 1 (ib, IGc) are alternately selected by the output enable signal OE2 applied to the sample and hold circuit (4) via the switch circuit SW3. ,
This is a signal obtained by delaying the output enable signal OEI by 1/2H. The switch circuit SW3 operates according to the timing pulse TPI shown in FIG. 4(g).
When timing pulse TP2 is at a low level, the switch element 5W3a is turned on and the output enable signal OE2 is output as 0E2a, and when the timing pulse TP2 is at a high level, the switch element swab is turned on and the output enable signal OE2 is output as 0E2a.
Output as 2b. That is, the switch circuit SW3 switches the switch element 5W in synchronization with the timing pulse TPI.
3a and 5W3b operate alternately, Figure 4 (t), N)
As shown in the figure, every other output enable signal OE2 is selected and outputted to the sample and hold circuit 14 as 0E2a and 0E2b.

The sample and hold circuit t4 first includes a switch element 5W.
The buffer 15b is operated by the output enable signal OE 2a selected by the output enable signal OE 2a, and outputs the video signal A' stored in the capacitor tab as shown in FIG. The buffer 15c is activated by the output enable signal 0E2b, and outputs the video signal B' stored in the capacitor lGc. Thereafter, buffers 15b and 15c are created in the same manner.
operate alternately, and even-numbered line video signals At, B/, C
/, . . . are output to the output line DL. in this case,
Since the output terminals of the tristate buffers 15a to 15c become high impedance when not selected, the output line D
It does not affect the signal on L.

As described above, the video signals A, B, C, . . . of odd lines are output from the buffer 15a, and the buffer 15b
, 15c, the even line video signal A'B'C
'... are output and synthesized on the output line DL. In this case, the odd line video signals A, B, C,
Even-numbered line video signals A', B', C' for ...
, ... are output with a delay of 1/2H, so the video signals are A, A', B, B' as shown in Fig. 4(n).
, C, C', .

In response to the drain drive signal Di from the drain drive circuit, a gate drive circuit (not shown) sequentially outputs gate pulses with a time width of IH with a time difference of 172H,
480 gate lines are sequentially driven at double speed. As a result, an active matrix liquid crystal display device having 480 gate lines can be driven using the ID and -TV signals.

In the above embodiment, the case where an active matrix liquid crystal display device is driven using an ID-TV signal is shown, but it can be used for an ED-TV signal as well as an ID-TV signal.

[Effects of the Invention] As described in detail above, according to the present invention, an IDTV signal is separated into odd horizontal lines and even horizontal lines, and their output timings are matched to restore the original frequency. Since the liquid crystal display device is driven line-sequentially at double speed based on the signals of the even-numbered horizontal lines, the active matrix liquid crystal display device can be driven without changing the drive frequency of the drain drive circuit.

14...Sample hold circuit, 15a-15c...
・Tri-state buffer, 17... common line,
21a...odd line output circuit, 21b...even line output circuit, 22a, 22b, 23a,
23b-...Analog switch, 24...Delay line, 5WI-3W3...Switch circuit, DL...
output line.

[Brief explanation of drawings]

1 to 4 show a complete embodiment of the present invention. FIG. 1 is a circuit configuration diagram showing a 1-bit signal processing system of the drain drive circuit, and FIG. 2 is a circuit diagram showing the drain drive circuit of FIG. A block diagram showing a circuit for creating the first and second video signals that are manually input to the drive circuit, FIG. 3 is a timing chart for explaining the operation in FIG. 2, and FIG. 4 is for explaining the operation in FIG. 1. This is a timing chart for

Claims (1)

[Claims] Separation means for separating a video signal having a horizontal frequency twice that of the video signal into odd horizontal lines and even horizontal lines; an output timing adjustment means for delaying the output timing by 1/2 horizontal period to match the output timing; a frequency conversion means for converting the video signal whose timing has been adjusted by the adjustment means to the same frequency as the horizontal frequency of the original signal; an output means for sampling video signals of odd horizontal lines and even horizontal lines whose frequency has been converted by the converter and outputting the samples alternately at intervals of 1/2 horizontal period; 1. A method for driving an active matrix liquid crystal display device, comprising: drive means for sequentially driving the display device at double speed.