JPH05224630A - Full color liquid crystal driving circuit - Google Patents

Abstract

PURPOSE:To provide an inexpensive full color liquid crystal driving circuit by which a liquid crystal display element having extremely large number of horizontal picture elements is easily driven. CONSTITUTION:A line memory 1 divides an inputted video signal in a horizontal scanning period into (n) phases, and extends it (n) fold (n) amplifiers 2 amplify a signal 6 outputted from the line memory 1 to voltage required for driving the liquid crystal display element 11. Then, signal output circuits 3 are respectively connected to (n) amplifiers 2. When it is assumed that the number of horizontal picture elements is (x) and the horizontal scanning period is (t), operating frequency required for the amplifier 2 and the circuit 3 is 1/{n(t/x)} and it is (1/n) fold operating frequency in the conventional manner. In the case of performing full color display in a state where the number of horizontal picture elements is large, an extremely high speed amplifier and an extremely high speed signal output circuit for impressing the voltage on the liquid crystal display element are required, but the liquid crystal display element having the large number of horizontal picture elements is easily driven even in the case of using an ordinary-speed amplifier and an ordinary-speed signal output circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full color liquid crystal drive circuit, and more particularly to a full color liquid crystal drive circuit for driving an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art FIG. 8 shows an active matrix type full color liquid crystal display (Liquid Crystal Display;
It is an equivalent circuit diagram showing a CD (NEC, Techni
calreport Vol.41 No.5 / 1988). Liquid crystal pixels 21 are arranged in a matrix, and an amorphous silicon TFT (Thin Film Transistor) 22 that functions as a switch is connected between each liquid crystal pixel 21 and a signal line. A signal supply circuit 23 and a scanning circuit 24 are connected to the liquid crystal pixels 21 and the TFTs 22. In this active matrix type liquid crystal display, when the signal of each pixel 21 is selected, the TFT 22 corresponding to the pixel 21 is turned on by the scanning circuit 24 to write the signal voltage to the pixel 21, and at the other time T
The FT 22 is turned off to prevent the crosstalk effect between the adjacent pixels and hold the signal voltage. In this operation method, only the selected signal voltage is applied to the liquid crystal pixels at all times, which enables high-quality display.

FIG. 9 is a block diagram showing a conventional full-color liquid crystal drive circuit for driving this active matrix type liquid crystal display element.

From the video signal input terminal 5, the horizontal scanning period t
When the analog video signal of 1 is input, the amplifier 2 amplifies this video signal to a voltage necessary to drive the liquid crystal display element 4 having horizontal x pixels. Therefore, the amplifier 2 has an operating frequency of 1 / (t / x). Signal output circuit 3
Has a sample hold circuit for sampling the signal output from the amplifier 2 corresponding to each horizontal pixel of the liquid crystal display element 4, and an output buffer, and outputs the signal at an operating frequency of 1 / (t / x) To do. The signal output circuit 3 divides the video signal input to the circuit 3 into x signals of the same number as the number of horizontal pixels of the liquid crystal display element 4 and outputs the signals, and the output signal is input to the liquid crystal display element 4. ..

However, in this conventional full-color liquid crystal drive circuit, when full-color display (analog display) is attempted when the number of horizontal pixels of the liquid crystal display element is increased, it is necessary to improve the frequency characteristic of the analog amplifier 2. is there. That is, the drive circuit needs to operate at an extremely high speed, and requires the amplifier 2 and the signal output circuit 3 which are extremely high speed. However, since the operating frequencies of the amplifier 2 and the signal output circuit 3 that are normally used are limited, it is difficult for a conventional drive circuit to drive a liquid crystal display element having an enormous number of pixels. On the other hand, if the operating frequencies of the amplifier 2 and the signal output circuit 3 are increased so that a liquid crystal display element having a large number of horizontal pixels can also be driven, the manufacturing cost thereof is significantly increased, and the manufacturing cost of the drive circuit is significantly increased. There is.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a low-cost full-color liquid crystal drive circuit which can easily drive a liquid crystal display device having an extremely large number of horizontal pixels. To aim.

[0007]

A full-color liquid crystal drive circuit according to the present invention inputs a video signal, divides the video signal in the horizontal scanning period into a plurality of phases, and expands the video signal of each phase in the horizontal scanning period. It has a line memory circuit for outputting. Each of the divided video signals is amplified by the amplifying means to a voltage required to drive the liquid crystal display element, and then the amplified signal is output to the liquid crystal display element via the signal output circuit.

[0008]

In the present invention, the line memory circuit divides the video signal in the horizontal scanning period into a plurality of phases, the amplifying means amplifies each divided video signal, and the signal output circuit outputs the signal to the liquid crystal display element. Therefore, the amplification means and the signal output circuit may have an operating frequency corresponding to the divided video signal. Therefore, the amplifying means and the signal output circuit may be slow in operation speed, and the liquid crystal display device having a huge number of pixels can be easily driven by using the amplifying means and the signal output circuit of the normal operation speed. can do.

[0009]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a drive circuit of a liquid crystal display element according to a first embodiment of the present invention. The video signal input terminal 5 is connected to the line memory 1 which constitutes the liquid crystal display drive circuit (enclosed by a chain line) of the present embodiment, and the video signal VI input to the video signal input terminal 5 is connected.
Is input to the line memory 1. From the line memory 1, n signals VO1, VO2, ..., VOn are output to the line memory output signal line 6, and these signals are supplied to the n amplifiers 2 (OP1, OP2, OP3, ... OP (n- 1), OP
input in n). The output signal of each amplifier 2 is a signal output circuit 3 (IC1, IC2, IC3, ... IC (n-1), I
It is input to Cn). The output terminal of each signal output circuit 3 is
In each group obtained by dividing the x horizontal pixels of the liquid crystal display element 4 into n, it is possible to connect to (x / n) horizontal pixels.

In the liquid crystal display element drive circuit having such a configuration, the video signals VI inputted to the line memory 1 through the video signal input terminal 5 are n by the line memory 1 every n horizontal scanning periods. It is divided into (phase). Each video signal obtained by division is expanded n times on the time axis. The line memory 1 uses the expanded n signals as divided video signals VO1 to VOn and outputs the n line memory output signal lines 6
Output to.

Next, the signals of each phase output from the line memory 1 are amplified by the n amplifiers 2 to a voltage required to drive the liquid crystal display element. After that, the signal amplified by the amplifier 2 is divided into the same number as each pixel on one scanning line by the signal output circuit 3 having a sampling hold circuit and an output buffer corresponding to each pixel on one scanning line of the liquid crystal display element 4. , To the liquid crystal display element 4.

At this time, assuming that the number of horizontal pixels of the liquid crystal display element 4 is x and the horizontal scanning period is t, the operating frequency required for the amplifier 2 and the signal output circuit 3 is 1 / {n (t / x)}, Compared with the case where the conventional circuit shown in FIG. 1 is used and a liquid crystal display element having the same number of horizontal pixels x is driven,
The operating frequency required for the amplifier 2 and the signal output circuit 3 is 1 /
It is reduced to n times. Therefore, even in a liquid crystal display device having a large number of horizontal pixels x, a drive circuit can be configured by using a conventional amplifier and signal output circuit that have been conventionally used. Therefore, the manufacturing cost is reduced.

Next, a specific configuration of the line memory 1 of this embodiment will be described with reference to FIGS. 2 and 3A to 3N.

FIGS. 2 and 3 are a block diagram and a timing diagram showing a portion for expanding the video signal into the n-phase in the line memory 1 shown in FIG. 1, respectively. As shown in FIG. 2, the video signal input to the video signal input terminal 5 is input to the line buffer 8 via the A / D converter 7. This line buffer 8 includes two sets of n line buffer circuits {1- (1), 1- (2), 2- (1), 2- (2).
... n- (1), n- (2)}. The line buffer 8 is a device capable of holding data of one horizontal period while converting a video signal into a digital signal.

The timing generation circuit (1) 10 has an oscillation circuit, a counter circuit, a decoder circuit and a phase comparator. Then, the timing generation circuit 10 outputs the write sampling clock signal WCK having a frequency sufficient not to deteriorate the image quality when the video signal is subjected to the digital signal processing, to the A / D converter 7 and each line buffer 8. , And outputs the read clock RCK to each line buffer 8. Further, the timing generation circuit 10 generates signals WE1n, WE2n ... RE1, RE2, etc. necessary for digital signal processing synchronized with the video signal. The output of each line buffer 8 is input to the n D / A converters 9, and the output signal of each D / A converter 9 is output to the line memory output signal line 6.

Next, the operation of the line memory 1 thus configured will be described. The signal input from the video signal input terminal 5 is input to the A / D converter 7 and converted into a digital signal at the timing of the signal WCK.
Then, after the write address of the line buffer 8 is reset by the write reset signal RSTW1, when the write control signals WE11, WE12, ... WE1n are at the LOW level, the output signal of the A / D converter 7 is changed to the line buffer 8 {1 -(1), 2- (1), ··· n- (1)} is input.

Next, after the read address is reset by the read reset signal RSTR1, the holding signal of each line buffer 8 is read by the read clock RCK having a frequency of 1 / n of WCK when the read control signal RE1 is at the LOW level. Be done. Further, when data is being read from the line buffer 8 {1- (1), 2- (1), ... N- (1)}, the line buffer 8 {1- (2), 2- ( 2), ... n-
(2)} is reset by the write reset signal RSTW2, and write control signals WE21, WE22, ... WE
When 2n is LOW level, the digitally converted video signal is input.

Next, the read address is reset by the read reset signal RSTR2, the read control signal RE2 becomes LOW, and the data is read at the timing of the signal RCK. The data read from each line buffer is converted into an analog signal by the D / A converter 9 (1, 2, ... N) and output to the line memory output signal line 6.

The above operation will be specifically described with reference to the case where the video signals D1 to Dn are supplied in a certain horizontal scanning period as shown in FIG.

At the start of the horizontal scanning period, as shown in FIG. 3 (E), the line buffers 1- (1) to n-
The write address reset signal RSTW1 is supplied to (1), the read address reset signal RSTR2 is supplied to the line buffers 1- (2) to n- (2), and the write address and the read address are reset.

Next, the supplied video signal is converted into a digital signal in response to the clock signal WCK shown in FIG. As shown in FIG. 3C, the write control signals WE11 to WE1n sequentially become active levels (low level in FIG. 3C), and the line buffers 1- (1) to n- (1) sequentially write. Then, as shown in FIG. 3G, the line buffer 1- (1)
To n- (1), the digitized video signals D1 to Dn are sequentially written.

On the other hand, the line buffers 1- (2) to n-
3 (J), an active level (low level in FIG. 3 (J)) read signal is supplied to the line buffers 1- (2) to n- (2) as shown in FIG. 3 (J). Three
In response to the clock RCK shown in FIG.
As shown in (M), the sequentially stored video signals are output. The video signals output from the line buffers 1- (2) to n- (2) are converted into analog signals by the D / A converter as shown in FIG.

At the start of the next horizontal scanning period, as shown in FIG.
As shown in (F), line buffer 1- (1)-
Address reset signal RSTR1 read to n- (1)
And the write address reset signal RSTW2 is supplied to the line buffers 1- (2) to n- (2),
The read address and write address are reset.

Next, the video signal shown in FIG. 3 (A) is converted into a digital signal in response to the clock signal WCK shown in FIG. 3 (B), and as shown in FIG. 3 (D),
The write control signals WE21 to WE2n sequentially become active levels, and the line buffers 1- (2) to n- (2).
Are sequentially written, and the digitized video signals D1 'to Dn' are written in the line buffers 1- (2) to n- (2) as shown in FIG.

The line buffers 1- (1) to n- (1) are supplied with the active level read signal RE1 as shown in FIG.
(1) to n- (1) respond to the clock RCK, and
As shown in (L), the video signals D1 to Dn stored in the previous horizontal scanning period are output. Line buffer 1-
The video signals output from (1) to n- (1) are converted by the D / A converter into the analog signals shown in FIG. After that, the same operation is repeated.

FIGS. 4 and 5A to 5L are a block diagram and a timing diagram, respectively, showing a specific configuration of IC1 to ICn of the signal output circuit. The timing generation circuit (2) 14 shown in FIG. 4 is composed of an oscillation circuit, a counter circuit, a decoder circuit, and a phase comparator (none of which is shown). Then, the timing generation circuit 14 outputs the shift clock of the shift register 12 having a frequency of 1 / {2 (t / n)}, and in synchronization with the video signal,
It generates control signals for the multiplexer 11, shift register 12, and sample hold 13. The multiplexer 11 switches the input video signals R, G, B according to the pixel arrangement of the liquid crystal display element selected by the MP signal and the shift direction of the shift register designated by the R / L signal, and switches to the sample hold 13. The video signal C of any one of R, G and B is output. The multiplexer 11 resets the internal counter every vertical cycle by the RESET signal and every horizontal cycle by the INH signal, and starts the switch operation when the SP signal is input.

When the SP signal is input to the shift register 12 after the internal counter is reset by the INH signal, the shift register 12 shifts to the C direction in accordance with the shift direction designated by the R / L signal.
Sampling pulses SMP1 to SM synchronized with the LK signal
Pm is sequentially output, and after the m-th sampling pulse is output, the SO signal for the SP signal of the next signal output circuit is output. The sample hold 13 has outputs HO1 to HOm, and each output has two sample hold capacitors. Then, when the sampling pulses SPM1 to SPMm from the shift register 12 are at the HIGH level, the voltage value of the video signal C output from the multiplexer 11 is held in each capacitor of the sample hold 13, and the next INH signal is at the LOW level. The voltage held in between is output, and then the INH signal goes high.
The voltage held during the GH level is reset. Then, by switching the capacitors to be held and output for each horizontal cycle, signals are continuously output.

Next, the operation of the signal output circuit configured as described above will be described with reference to FIGS. 5 (A) to 5 (L). At the start of the vertical scanning period, the RESET signal is supplied to the multiplexer 11 and the sample hold circuit 13 as shown in FIG. 5B, and the internal timers of both are reset. After that, at each start of the horizontal scanning period, FIG.
INH signal is supplied as shown in FIG.
1, reset the internal timers of the shift register 12 and the sample and hold circuit 13. As shown in FIG.
The SP signal is supplied immediately after the supply of the RGB video signal in each horizontal scanning period. In response to this SP signal, the multiplexer 11 sequentially selects the supplied RGB video signals and supplies them to the sample hold circuit 13, as shown in FIG. The sample hold circuit 13 sequentially samples the supplied video signal C and outputs it in parallel in response to the start of the next horizontal scanning period, that is, the next INH, as shown in FIG. 5 (F). ..

The operation of each part within one horizontal scanning period is shown in FIG.
(G) to FIG. 5 (L) will be described with reference to FIG.
As shown in FIG. 5, the INH signal is output at the beginning of the horizontal scanning period, and thereafter, the SP signal is output almost at the same time as the supply of the RGB video signal as shown in FIG. 5 (J). In response to the internal clock CLK shown, the multiplexer 11 sequentially selects and outputs the RGB video signals. As shown in FIG. 5K, the shift register 12 has sequential sampling pulses SMP1 to SMPm (R
SMPm to SMP1) are output depending on the level of the / L signal. In response to the sampling pulses SMP1 to SMPm, the sampling and holding circuit 13 sequentially samples and holds the supplied data from the HO1 side.
Finally, the shift register 12 outputs the signal S0 as shown in FIG.

As described above, in the present embodiment, the line memory 1 divides the video signal in the horizontal scanning period into a plurality of phases, and the signals of each phase are expanded in the horizontal scanning period, and then the plurality of amplifiers 2 are provided. Since a drive signal is output to the liquid crystal display element 4 by the plurality of signal output circuits 3, it becomes possible to use an amplifier and a signal output circuit having a low operating frequency.
Therefore, the drive circuit of this embodiment can easily drive a liquid crystal display element having an enormous number of horizontal pixels.

That is, in the conventional drive circuit, full-color display (analog display) is performed when the number of horizontal pixels increases.
Therefore, it is necessary to improve the frequency characteristic of the analog amplifier. However, in this embodiment, a clear image can be displayed without improving the frequency characteristic of the amplifier.

Next, an embodiment when the video signal is divided into four phases will be described with reference to FIG. 6 and FIG. 7 which is a signal waveform diagram thereof. The video signal input to the line memory 1 is divided into four phases by the line memory 1, expanded four times, and output to the line memory output signal line 6. Next, the line memory output signal is input to the four amplifiers 2, each signal is amplified by the amplifier 2 to a voltage required to drive the liquid crystal display element, and is input to the signal output circuit 3. Next, the signal input to the signal output circuit 3 is divided into 500 signals, which is a quarter of 2000, and then output to a liquid crystal display element having 2000 horizontal pixel numbers. In this case, if the horizontal scanning period is 50 μsec, the operating frequency required for the amplifier 2 and the signal output circuit 3 is 10 MHz.
On the other hand, when the conventional drive circuit is used, the operating frequency required for the amplifier and the signal output circuit is 40 MHz.
z.

[0034]

As described above, according to the present invention, a liquid crystal display device having an extremely large number of horizontal pixels can be easily driven by using an amplifier and a signal output circuit having a low operating frequency. , Its manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a full-color liquid crystal drive circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing details of a line memory 1.

FIG. 3 is a timing chart of the same.

FIG. 4 is a block diagram showing details of a signal output circuit 3.

FIG. 5 is a timing chart of the same.

FIG. 6 is a block diagram of a full-color liquid crystal drive circuit according to a second embodiment of the present invention.

FIG. 7 shows an input signal according to a second embodiment of the present invention,
It is a waveform diagram with the signal output from the line memory.

FIG. 8 is an equivalent circuit diagram showing an active matrix full-color liquid crystal display.

FIG. 9 is a block diagram of a conventional drive circuit.

[Explanation of symbols]

 1; line memory 2; amplifier 3; signal output circuit 4; liquid crystal display element 5; video signal input terminal 6; line memory output signal line 7; A / D converter 8; line buffer 9; D / A converter 10, 14; Timing generation circuit 11; Multiplexer 12; Shift register 13; Sample and hold 23; Signal supply circuit 24; Scan circuit

Claims (3)

[Claims] 1. A line memory circuit for inputting a video signal, dividing the video signal per one horizontal scanning period into a plurality of phases, and expanding the video signal of each phase to the horizontal scanning period on the time axis and outputting the same. An amplifying means for amplifying each divided video signal to a voltage required to drive the liquid crystal display element, and a signal outputting means for outputting the signal amplified by the amplifying means to the liquid crystal display element. A full-color liquid crystal drive circuit characterized by the above. 2. The sample output circuit, wherein the signal output circuit divides each divided video signal into a number corresponding to the number of pixels of the liquid crystal display element which the signal output circuit is responsible for,
An output buffer, and the full-color liquid crystal drive circuit according to claim 1. 3. The line memory inputs and holds one A / D converter for converting an analog signal of a video signal into a digital signal and an output signal of the A / D converter.
A pair of line buffers, n D / A converters for converting the outputs of the line buffers into analog signals and then outputting the analog signals to the n output terminals of the line memory, and input / output of signals in the line buffers. The output signal of the A / D converter is controlled to be divided into n phases in one horizontal scanning period, the signals of each phase are sequentially input to the n sets of line buffers, and the holding signals are sequentially output from each line buffer. 2. The full-color liquid crystal drive circuit according to claim 1, further comprising a timing generation circuit that outputs a timing signal for causing the liquid crystal display device to operate.