JPS61131975A - Picture processor - Google Patents

Abstract

PURPOSE:To improve the operability by inserting a reduced still pattern automatically in an animation pattern when a prescribed time is elapsed after the still picture mode is selected so as to reduce the switching. CONSTITUTION:In operating a switch 32 to set the still picture mode for observing a still picture, a video switch 4 is thrown to the position of a buffer amplifier 30, a still picture video signal is relayed to a monitor 34, a timer 33 starts the operation and when a vertical synchronizing signal -V is generated after the setting time, a timeout signal CE is outputted. Then the read start time and read period of a video information signal onto a monitor pattern from a memory 5 are controlled. Further, the signal CE is fed to an address selector 28 to obtain the 1/2 reduction still picture mode. Then the switch 4 relays the video signal of the 1/2 reduction still picture to the monitor 34 and applies the animation video signal from a buffer amplifier 20 to the monitor 34. A master/slave pattern where the reduced still picture is inserted to a part of the animation picture is obtained on the monitor.

Description

TECHNICAL FIELD The present invention relates to an image processing device, and more particularly to an image device that inserts and displays a reduced still image as a so-called child screen in a part of a two-dimensional screen obtained by a composite video signal.

BACKGROUND ART An example of such an image processing apparatus is one having a configuration as shown in FIG. 1 (α) proposed by the applicant of the present invention. In the figure, a so-called composite video signal supplied from the outside is sent to an analog/digital converter 1 (hereinafter referred to as A/D) for converting an analog signal into digital data.
(referred to as a D converter) is supplied to one input terminal of a synchronization signal separation circuit 2 for separating a synchronization signal from a composite video signal and a video switch 4 for relaying the composite video signal to a monitor 3, respectively. The video signal digitized by the A/D converter 1 is supplied to a memory 5. In response to the supply of the WE double signal, which is a write command, the memory 5 sequentially stores data corresponding to the video information component in the video signal at the memory address corresponding to the address signal supplied to the column address selector 6 and row address selector 7. (hereinafter referred to as video information data) is stored. In addition, the memory 5 converts the video information data at the storage address corresponding to the address signals supplied from the column address selector 6 and the row address selector 7 to the digital/analog converter 8 ( (hereinafter referred to as a D/A converter). The D/A converter 8 converts the supplied video information data into an analog signal and supplies it to the synchronization signal synthesis circuit 9 as a video signal. The synchronization signal synthesis circuit 9 inserts horizontal and vertical synchronization signals into the video signal based on the synchronization signal supplied from the synchronization separation circuit 2, returns the signal to a composite video signal, and supplies the signal to the other input terminal of the video switch 4. Video Switch 4 is also available in Thailand! The video signal is selectively relayed in response to a trigger signal supplied from the signal generator 10.

The horizontal and vertical synchronization signals extracted from the composite video signal by the synchronization separation circuit 2 are further transmitted to the timing signal generator 1.
0. The timing signal generator 10 generates the WE and RD double signal memory 5 based on the synchronization signal.
Then, the CLc signal, which is a clear command, is sent to the clear signal input terminal of the oscillator 11 and column address counter 12, the CLR signal, which is a clear command, is sent to the clear signal input terminal of the row address counter 13, and the CKR signal, which is a clock signal, is sent to the row address counter 13. The clock signals are supplied to the clock signal input terminals of the counter 13, respectively. The oscillator 1 generates a frequency f in accordance with the sampling synchronization of the video signal while being synchronized with the CLc signal.
A CKo signal, which is a CK clock signal, is supplied to the lock signal input terminal of the column address counter 12. The column address counter 12 is an 8-digit binary counter,
It is counted up by the CK signal and cleared by the CLc signal. 8 of column address counter
The output of the digit is supplied to each input terminal of the column address selector 6 which performs the address shift shown in FIG. 1(6). The column address selector 6 is, for example, a changeover switch having N+2 input terminals and N+1 common terminals as output terminals, and the input terminal corresponding to the minimum digit is grounded. When the changeover switch is changed, a 1-bit shift is performed in which the digits are shifted down one digit at a time.

The N+1 digit outputs of the column address selector are respectively supplied to the N+1 digit column address input terminals of the memory 5. The column address selector performs the address shift in response to the reduction command signal α. The CKR and CLR signals from the timing signal generator are supplied to the clock signal input terminal and clear signal input terminal of the row address counter 13, respectively. The row address counter 13 and the row address selector are each column address counter 12.
and column address selector 6, and similarly performs address shifts in response to reduction command signal α. Row address selector 7 ON + 1 digit output is memory 5
These are supplied to the ON+1 digit row address input terminals, respectively.

Next, the operation will be explained with reference to the timing chart of FIG. The write mode will now be explained. In write mode, each switch is connected as shown. The supplied composite video signal is digitized by the A/D converter 1 and supplied to the memory 5 as video information data. Each period corresponding to the WE double signal, synchronization signal, and retrace period on the screen supplied from the timing signal generator 10 to the memory 5 is set to a low level (hereinafter referred to as LQ level), and the other periods are set to a high level (hereinafter referred to as Hi). level). The memory 5 sequentially stores the video information data in predetermined positions corresponding to the supplied column address and row address signals in response to the WE multiplied signal Hi level. The CLc signal supplied to the column address counter 12 clears the count value of the column address counter 12 every period corresponding to one horizontal scan of the screen (hereinafter referred to as IH).

Also, CKc supplied to the column address counter 12
The signal is a clock signal that counts and amplifies the column address counter 12 in synchronization with the CLc signal, and the video information data is sampled and stored in the memory 5 at the clock cycle. Row address counter 13
The CKR and CLR signals supplied to I
These are a clock signal that counts up the counter every period corresponding to H, and a signal that clears the count value every period corresponding to one field or one screen. In this way, each signal is sequentially supplied, and video information data equivalent to one screen is stored in the memory 5.
It is memorized.

The still image mode will be explained. When the timing signal generator (not shown) is commanded to enter the still image mode, which is a normal-sized still screen, the video switch 4. Only the WE multiple signal and RE multiple signal states change. Video switch 4 relays the composite video signal supplied from the synchronization signal synthesis circuit to monitor 3. The waveform of the WE-multiplied signal and the RE-multiplied signal is obtained by replacing the waveforms shown in FIG. 2 in the write mode with each other. Therefore, in the still image mode, reading is performed with the same timing, period, and address specification as in the write mode. The read video information data is converted into a video signal by a D/A converter 8 and supplied to a synchronization signal synthesis circuit. Then, an image of the same size as the image based on the standard video signal is reproduced on the monitor 3.

Next, the false reduced still image mode will be explained.

When the false reduction still image mode is commanded to the timing signal generator 10 (not shown), the timing signal generator 10 supplies the reduction command signal α to the column address selector 6 and the row address selector 7, as shown in FIG. Each signal is generated at such timing. The column and row address selectors 6.7, for example, change the connected switches shown in FIG. 1(b) from the illustrated state to an address shift state in which the address is shifted down by one bit. At this time, the least significant bits of the column and row addresses are fixed to correspond to "1" or "0". Further, the frequency of each clock signal supplied to the column and row address counters 6.7 is the same as in the write mode.

Therefore, the column and row address signals supplied to the memory 5 designate the address of the memory 5 at every other address in the same cycle as the write mode.

Further explanation will be given with reference to FIG. 4(cL) and FIG. 4(ri). FIG. 4(α) shows each address signal supplied from the column and row address selector 6.
” before the address shift and the least significant bit as rO
This is an example of a signal after the address shift selected as J. FIG. 4(b) is a schematic diagram of a memory area for explaining memory addresses. The memory 5 becomes (0,0) when the first RD signal pulse is supplied.

Output image information data. In addition, the memory 5 is a second RD
% (210) when the signal pulse is supplied.

In response to every other column address and row address such as (2, 2), (2, 4), etc., the corresponding stored video information data is output. The video information data read out in this way passes through the D/A converter 8, the synchronizing signal synthesis circuit 9, and the video switch 4, and is displayed on the screen of the monitor 3, which is 14 times larger in both the vertical and horizontal directions than in the write mode. It is reproduced as an image of the same size.

Since the image processing device is configured as described above, if either video information or still image information is selected, the other information cannot be obtained.1 For example, when a television broadcast, etc. is supplied as video information, If still image information is selected, necessary information from television broadcasts or the like will be missed, which increases the frequency of mode switching, and such switching operations are cumbersome.

The purpose of the present invention is to reduce such switching operations,
The object of the present invention is to provide an image processing device with improved operability.

In order to achieve the above object, the image processing apparatus of the present invention is configured to automatically insert a reduced still screen into the video screen after a predetermined time has elapsed after the still image mode is selected.

Embodiment An embodiment of the present invention will be described with reference to the block diagram of FIG. In this figure, the same reference numerals are used for parts equivalent to the circuit shown in FIG. 1, and the explanation of these parts will be omitted. The input composite video signal is passed through a buffer amplifier 20 to a low pass filter (hereinafter referred to as LPF') 2.
11 synchronization separation circuit 2, and is also supplied to one input terminal of a video switch 4 as a moving video signal.

The LPF 21 sets the frequency component of the video signal below a predetermined frequency and supplies the composite video signal to the clamp amplifier 22. The clamp amplifier 22 removes the synchronizing signal portion from the video signal and supplies only the video information portion at a predetermined level to the A/D converter 1. The A/D converter 1 digitizes the video signal and supplies it to the memory 5 as video information data. The synchronization separation circuit 2 extracts horizontal and vertical synchronization signals H and V from the composite video signal, and sends them to the horizontal timing 1 circuit 50, the horizontal timing 2 circuit 511, the vertical timing 1 circuit 52, and the vertical timing 2 circuit 531 as shown in the figure. The signal is supplied to the oscillator 11, the switch timing circuit 23, and the synchronization signal synthesis circuit 9.

The horizontal timing 1 circuit 50 supplies the above-mentioned CLc signal to one input terminal of the changeover switch 25 of the address control section 24. FIG. 5 (b>) shows a schematic diagram of an example of the configuration of the address control section.The horizontal timing 2 circuit 51 synchronizes with the horizontal synchronization signal and generates a Lo times signal, and when a set time elapses, a Hi times signal becomes an H2 signal. The signal is supplied to the other input terminal of the changeover switch 25.The vertical tie 9 Fufu 1 circuit 52Fi supplies the aforementioned CLR signal to one input terminal of the changeover switch 26.The vertical timing 2 circuit 53 is synchronized with the vertical synchronization signal. Then, when a set time has elapsed, a Lo multiplication signal or a Hi multiplication signal is supplied to the input terminal of the changeover switch 260.The common terminals of the changeover switches 25 and 26 are connected to the column address counter 12 and the input terminal of the changeover switch 260, respectively. The oscillator 11 is connected to the clear signal input terminal of the row address counter 13.The changeover switches 25 and 26 are also triggered by the switching command signal Z supplied from the controller 27 during the second reduced still image mode. The above-mentioned CKc signal is supplied to the clock signal input terminal of the column address counter.The CLc signal is supplied as the above-mentioned CKR signal to the clock signal input terminal of the row address counter 13 via an inverter. An image mode signal, time error) CE multiplication signal, write mode signal (not shown), etc. are supplied. and,
The controller 27 generates a successive command R signal in response to the still image mode signal, the switching command signal Z in response to the time error (CE) multiplication signal, and a write command signal W in response to the write mode signal. The output of the valley address counter is supplied to the address shift section 28.

The address selector unit 28 is composed of a column address selector 6 and a row address selector 7 as shown in FIGS. 1(α) and (6), and performs address shifting in response to the timeout CE signal. Address selector section 2
The output of 8 is supplied to the column address and row address signal input terminals of the memory 5. Memo! The video information data supplied in response to the JljW signal is sequentially stored in memory addresses corresponding to the supplied address signals. Further, the memory 5 supplies the D/A converter 8 with the video information data stored in the storage address corresponding to the address signal supplied in response to the R signal. The D/A converter 8 converts the image information data into an analog signal and supplies it to the LPF 29. LPF29f
d Smooth the analog signal and supply it to the synchronization signal synthesis circuit as a VDI signal. The synchronization signal synthesis circuit 9 supplies a video signal VD2 obtained by adding horizontal and vertical synchronization signals to the analog signal to the other input terminal of the video switch 4 via the buffer amplifier 30.

At the switch timing, a switching command pulse signal synchronized with the supply timing of the address signal in the 14-reduced still image mode is supplied to the switch control circuit 31. One terminal of the still image selection switch 32 that commands the still image mode is grounded, and the other terminal is connected to the timer 33, the switch control circuit 31, and the address control section 24.

The timer 33 to which the still image mode SW signal is supplied starts timing operation when the still image mode SW signal is supplied from the still image selection switch, and generates a timeout CE signal when a predetermined time has elapsed. This timeout cE signal is supplied to the address control section 24, the trigger input terminal of the address selector section 28, and the switch control circuit 31.

The switch control circuit 31 supplies an SC signal to the trigger terminal of the video switch 4. And - when in write mode,
A Lo level is supplied to the video switch 4 to cause the video switch 4 to relay the moving video signal supplied from the buffer amplifier 20 to the monitor 34. Further, the switch control circuit 31 supplies a Hi level to the video switch 4 in accordance with the still image mode SW signal, and relays the still image video signal supplied from the buffer amplifier 30 to the monitor 34.

Furthermore, the timeout CE of the switch control circuit 311d
When the signal is supplied, a BT double signal, which is a switching command pulse signal from the switch timing circuit 23, is sent to the video switch 4.
relay to the trigger input terminal.

Next, the operation will be explained with reference to the timing charts from FIG. 6 onwards. Figures 6 and 7 show the rose mode,
The waveforms of the main signals in the still image mode and the reduced still image mode are shown. Write mode, still image mode and IA
Each operation in the reduced still image mode is the same as that of the circuit shown in FIG. 1, so a description thereof will be omitted.

The parent-child screen mode will be explained. It is assumed that the memory 5 has already stored video information data of the latest frame. To view still images, press the still image selection switch 32.
When the switch is temporarily closed, the SW signal is supplied to the address control unit 24, and the still image mode is started. At the same time, SWB
The signal is supplied to the switch control circuit 31 and the timer 33, switches the video switch 4 to the buffer amplifier 30 side, relays the still image video signal to the monitor 34, and starts the timer 33's timing operation. When the V signal is generated after a predetermined time set in the timer 33 has elapsed, a timeout CE signal is generated.

This timeout CE signal causes the address control unit 24
The selector switches 25 and 26 are switched.

The H2 signal and the V2 signal are supplied to the clear signal input terminals of the column address counter 12 and the row address counter 13, respectively. FIG. 9 shows the waveforms of the %H2 signal and the v2 signal. L of H2 signal (Level period X and v2
The H timing 2 circuit 51 and the V timing 2 circuit 53 are configured so that the L'o level period Y of the signal can be set within a predetermined range. These H2 and V2 signals control the start time and output period of the video information signal on the monitor screen. Figure 10 shows an example in which the moving image screen is the so-called main screen and the reduced still screen is the child screen. The position of the child screen is set corresponding to the above X and Y periods.The CE double signal is also supplied to the address selector 28, and the address is shifted to enter the 1/2 reduction still image mode.

Furthermore, the ST double signal in the reduced still image mode is supplied to the CE double signal switch control circuit 31, and is a pulse signal as shown in FIG. That's what I'm doing. That is, it is also possible to maintain the Hi level only during the period when the read command R signal and the address signal are present. S
The generation timing of the pulse signal and its Lo level period are changed according to the T-fold signal v2 signal and the H2 signal. Therefore, the video switch 4 relays the video signal to the monitor 34 only when the video signal in the 1/s reduction still image mode is supplied from the buffer amplifier 30, and otherwise relays the video signal supplied from the buffer amplifier 20. The video signal is relayed to the monitor 34. The image reproduced on the monitor 34 becomes a parent-child screen in which a reduced still image is inserted into a part of a moving image as shown in FIG.

When the still image selection switch 32 is closed again, the parent-child screen mode is canceled and a moving image is reproduced on the monitor.

In the above embodiment, the screen is replaced with still image information stored in the memory in accordance with the still image mode command, but signals of a moving image and a still image or a moving image and a reduced still image are alternately transmitted every predetermined scanning layer, for example, every IH. It is also possible to create a so-called double projection state by relaying the image to

In addition, in the embodiment, the still image was reduced to 14, but any reduction ratio, for example, 1. It is also possible to use a sub-screen such as a /44 reduced still image or a 2x enlarged still image.

As described in detail, the image processing device of the present invention includes:
This is because it is possible to perform signal processing such that a frame arbitrarily selected from the supplied video signal is displayed as a still image in place of the moving image screen based on the video signal, and then this is reduced and displayed on the moving image screen. Since a screen is formed that is continuously reduced and displayed after confirming a desired frame, various uses can be considered.

[Brief explanation of drawings]

FIG. 1 (α) is a schematic block diagram showing an example of an image processing device;
FIG. 1 (6) is a specific circuit example of the column and row address selector; FIG. 2 is a timing chart of the main signals in the write mode of the device shown in FIG. FIG. 5 (6) is a block diagram showing an example of the 14-reduced still image mode, and FIG. 6 is a block diagram showing an example of an address control circuit. @Figure 9 is the waveform diagram of the main signals, the first
Figure 0 is a beak samurai diagram to explain the parent-child screen. Explanation of symbols of main parts 4...Video switch 5...Memory 23...
- Switch timing circuit 24...Address control section 28...Address shift section 31...Switch control circuit 33...Timer 34
・・－Monitor

Claims (1)

[Claims] An A/D conversion means converts only the video information component of the supplied composite video signal into a digital signal, and while a write command exists, the digital signal is stored at an address specified by an address signal and a read command is issued. a memory matrix that reads a digital signal from an address specified by an address signal while it exists; an address signal generating means that sequentially outputs the address signal at a timing according to a synchronization signal separated from the video signal; a still image signal generating means for converting the output digital signal into an analog signal and mixing the synchronization signal to generate a still image signal; a command switch for generating a still image mode command signal; and a command switch for generating a still image mode command signal; a timer means for generating a reduced still image mode command signal after a predetermined period has elapsed; an address signal changing means for removing a part of the address signal in response to the reduced still image mode command signal; During the period when the reduced still image mode command signal is absent, the video signal is relayed, and during the period when the still image mode command signal is present, only the still image signal or the still image signal and the video signal are alternately transmitted every predetermined scanning line. While the reduced still image mode command signal is present, only the still image signal or the still image signal and the video signal are alternately relayed for each predetermined scanning line only when the address signal corresponds to a predetermined area of the playback screen. and relay means for relaying the video signal in other areas.