JPH0918843A - Multiplexer - Google Patents

Abstract

PURPOSE: To multiplex digital video signals DV in a simple constitution by subjecting signals DV1 and DV2 to time base compression based on a reference signal synchronized with the horizontal synchronizing signal of the signal DV1 and multiplexing them and converting them to serial data. CONSTITUTION: A PLL circuit 10 separates a horizontal/vertical synchronizing signal (HD/VD) from a video signal SV1 to output clocks CK1 and CK2 synchronized with the signal HD and a reference/vertical synchronizing signal (HDD /VDA). A/D conversion circuits 17 and 18 write digital video signals DV1 and DV2, which are obtained by subjecting the signals SV1 and SV2 to A/D conversion based on the clock CK1, in memories 19 and 20 based on the clock CK1. Selection circuits 21 and 23 are switched based on the signal BDD and output the clock CK2 to the memory 19/20 to selectively output the output data of the memory 19/20 in the first/latter half of one horizontal scanning period of the signal SV1. Thus, data DM where signals DV1 and DV2 subjected to time base compression are multiplexed by memories 19 and 20 is outputted in the simple constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexing device.
By compressing and multiplexing a plurality of video signals on the basis of the video signal of (1), the video signals of a plurality of channels can be multiplexed and serially transmitted with a simple configuration.

[0002]

2. Description of the Related Art Conventionally, in a surveillance system for factories, public facilities, etc., a surveillance camera is installed at each surveillance point,
The image pickup results of these surveillance cameras can be centrally monitored in a surveillance room or the like.

Therefore, in a surveillance camera applied to this type of surveillance system, each is connected to a monitor device in a surveillance room by a coaxial cable or the like, and operates in synchronization with a reference signal sent from the surveillance system. It was done.

[0004]

By the way, if the image pickup result of this type of surveillance camera can be transmitted through one transmission line, complicated cable laying work can be simplified, and monitoring can be performed if necessary. It is possible to add more cameras, which is considered convenient.

The present invention has been made in view of the above points, and an object thereof is to propose a multiplexer capable of multiplexing and transmitting video signals of a plurality of channels with a simple structure.

[0006]

In order to solve the above problems, according to the present invention, reference signal generating means for generating a reference signal synchronized with a horizontal synchronizing signal of one digital video signal among a plurality of digital video signals. With this reference signal as a reference, a plurality of digital video signals are time-axis-compressed in units of the horizontal scanning period determined by the previous horizontal synchronization signal, and the plurality of time-axis-compressed digital video signals are multiplexed. Data conversion means for converting to serial data.

At this time, the above-mentioned data conversion means inserts identification data for identifying the horizontal blanking period and the vertical blanking period of each digital video signal into each digital video signal, and then converts it into serial data.

[0008]

Of the plurality of digital video signals, the reference signal synchronized with the horizontal synchronization signal of one digital video signal causes the plurality of digital video signals to be time-axis based on the horizontal scanning period determined by the horizontal synchronization signal. Compress,
By multiplexing the plurality of time-axis-compressed digital video signals and converting them into serial data, it is possible to process and multiplex the plurality of digital video signals by one system of reference signal.

At this time, if the above-mentioned data conversion means inserts identification data for identifying the horizontal blanking period and the vertical blanking period of each digital video signal into each digital video signal, and then converts it into serial data, On the receiving side,
The required digital video signal can be processed based on this identification data.

[0010]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing a monitoring system according to an embodiment of the present invention. This monitoring system 1
Surveillance camera 2 consisting of an NTSC television camera
An image of a desired subject is picked up by 3 and 3, and the result of the picked-up image is monitored by the monitor device 4 installed in the monitoring room. For this reason, the surveillance cameras 2 and 3 send the video signals SV1 and SV2, respectively, which are image pickup results, to the coaxial cable 6 via the serial data interface circuit 5, and then output them from the serial data interface circuit 7 to the monitor device 4.

That is, as shown in FIG. 1, the serial data interface circuit 5 outputs the video signal SV1 to PL.
It is input to the L (Phase Locked Loop) circuit 10 and the operation reference clocks CK1 and CK2 are generated from the video signal SV1.

That is, in the PLL circuit 10, the sync separation circuit 11 separates the horizontal sync signal HD and the vertical sync signal from the video signal SV1. Phase detection circuit (PD:
The phase detector 12 obtains the result of phase comparison between the horizontal synchronizing signal HD and the horizontal synchronizing signal HDA output from the counter 13, and the result of this phase comparison is passed through a low-pass filter (not shown) to a voltage controlled oscillator circuit (VCO: Voltage
Output to Controlled Oscillator 14).

The voltage control type oscillation circuit 14 receives the phase comparison result as a control voltage and generates a clock CK2 having a frequency of 8 fsc with respect to the subcarrier frequency fsc of the video signal SV1 and synchronized with the video signal SV1. . The 1/2 frequency dividing circuit 15 divides this clock CK2 by 2 to generate a clock CK1 having a frequency 4fsc synchronized with the video signal SV1.

The counter 13 is formed of a ring counter that counts a specified number of clocks CK1 having the frequency 4fsc, and generates the above-mentioned horizontal synchronizing signal HDA. As a result, the PLL circuit 10 feeds back the horizontal synchronization signal HDA to the phase comparison circuit 12 to form a feedback loop, and generates clocks CK1 and CK2 synchronized with the video signal SV1. Also counter 1
Similarly, 3 is a horizontal synchronizing signal HD of the video signal SV1.
The reference synchronizing signal HDD having a duty ratio of 50% and the vertical synchronizing signal VDA synchronized with the vertical synchronizing signal of the video signal SV1 are generated and output.

As shown in FIG. 3, the analog-digital conversion circuits (A / D) 17 and 18 have a frequency of 4 fsc.
Video signals SV1 and SV2 (FIGS. 3A and 3B) based on the clock CK1 (FIG. 3C) of FIG.
To analog-to-digital conversion to convert each video signal SV1 and SV2 into an 8-bit digital video signal DV
1 and DV2 (FIGS. 3D and 3E).

As a result, the analog-digital conversion circuit 1
7 and 18 are two-channel video signals SV1 and SV
Of V2, a clock CK synchronized with the video signal SV1
1, the video signals SV1 and SV2 are converted into digital video signals DV1 and DV2, and as shown in FIG. 4, the video signal SV1 used as the reference for generating this clock CK1 (FIG. 4B) is ( FIG. 4 (A)), 1
The horizontal scanning period is sampled by 910 samples to generate the digital video signal DV1. On the other hand, for the video signal SV2 asynchronous with the video signal SV1, the digital video signal DV2 is generated by sampling 910 samples for a period corresponding to one horizontal scanning period of the video signal SV1.

The memories 19 and 20 execute the writing process with the clock CK1 as a reference, and sequentially and cyclically use the memory space to generate the digital video signal DV1.
And DV2 are stored. Furthermore, the memories 19 and 20 are
The clock CK2 supplied via the selection circuit 21 (see FIG.
With reference to (G)), the stored digital video signals DV1 and DV2 are output in the order of storage.

The selection circuit 21 switches the operation based on the reference synchronization signal HDD (FIG. 3 (F)),
The clock CK2 is output to the memory 19 in the first half of one horizontal scanning period of the video signal SV1, and the clock CK2 is output to the memory 20 in the second half.

As a result, the memories 19 and 20 time-compress the digital video signals DV1 and DV2 of 910 samples corresponding to one horizontal scanning period of the video signal SV1 in the 1/2 horizontal scanning period to form the reference synchronization signal HDD. Alternately output synchronously.

The selection circuit 23 switches the contact based on the reference synchronization signal HDD and selectively outputs the output data of the memories 19 and 20. As a result, the selection circuit 23 multiplexes the digital video signals DV1 and DV2 that have been time-axis compressed by the memories 19 and 20 and outputs them to generate multiplexed data DM (FIG. 3 (H)).

As a result, in the serial data interface circuit 5, with reference to the clocks CK1 and CK2 generated by the video signal SV1 and the reference synchronization signal HDD,
With the horizontal scanning period of the video signal SV1 as a unit, the video signals SV1 and SV2 are converted into digital signals and then time-axis compressed, and the plurality of time-axis compressed digital video signals DV1 and DV2 are horizontally scanned during the horizontal scanning period of the video signal SV1. It is designed to be multiplexed on the basis of.

The inverter circuits 24 and 25 output an inverted signal of the lower 2 bits of the multiplexed data DM, thereby adding 2 bits of surplus bits to the 8-bit multiplexed data DM and converting it to 10 bits. , Multiplexed data DM
The DC component of is removed.

The sync separation circuit 26 separates the horizontal sync signal HDB and the vertical sync signal VDB from the video signal SV2 and outputs them. The identification data adding circuit 27 uses the reference synchronization signal H.
Based on the DD, the vertical synchronizing signal VDA, the horizontal synchronizing signal HDB, and the vertical synchronizing signal VDB, prescribed identification data is inserted in the multiplexed data DM.

That is, as shown in FIG. 5, the identification data adding circuit 27 corresponds to the rising of the horizontal blanking period of the video signal SV1 with reference to the reference synchronizing signal HDD (FIGS. 5A and 5B). The 3-byte timing data is inserted at the timing. Here, the timing data is
In synchronization with the clock CK2 (FIG. 5 (C)), the first 1 byte is set to 3FFh and the subsequent 2 bytes are set to 000h (FIGS. 5 (D0) to (D0)).
9)). As a result, the identification data adding circuit 27 sets all bits of the multiplexed data DM corresponding to the rising of the horizontal blanking period, which are not allowed in other bytes, to the logical H and logical L states, and the serial data is set. After the conversion to, the break of the byte can be detected based on this timing data.

Further, the identification data adding circuit 27 similarly uses the vertical synchronizing signal VDA as a reference at a timing corresponding to the rising of the vertical blanking period of the video signal SV1.
The specified identification data is inserted into the multiplexed data DM. As a result, the identification data adding circuit 27 can detect the timing of horizontal scanning and vertical scanning of the video signal SV1 in the multiplexed data DM with reference to the timing data and this identification data.

Further, the identification data adding circuit 27 uses the horizontal synchronizing signal HDB and the vertical synchronizing signal VDB as a reference, at a timing corresponding to the rising edges of the vertical blanking period and the horizontal blanking period of the video signal SV2. The specified identification data is inserted in each. As a result, the sync separation circuit 26 can detect the timing of horizontal scanning and vertical scanning of the video signal SV2 for the multiplexed data DM based on this identification data. Thus, like the timing data, these identification data are defined such that all the bits which are not allowed in other bytes are combined with bytes of logical H or logical L, and are different from other identification data. Thereby, each identification data can be detected easily and surely.

Parallel-serial conversion circuit (P / S) 28
Performs parallel-serial conversion on the multiplexed data DM output from the identification data adding circuit 27, and as a result, a transmission rate of about 290 [Mbps] (286 [Mbps] ≈91.
0 sample x 525 lines x 30 frames x 10 bits x 2 systems = 4 x 3.579545MHz x 10 bits x
The transmission data DS, which is serial data of two systems), is output to the coaxial cable 6.

As a result, the serial data interface circuit 5 generates a reference signal based on the video signal SV1 by one reference signal generation system, generates the digital video signals DV1 and DV2 using this reference signal, and outputs the time. After axial compression, the signals are multiplexed and sent out in the form of serial data to the transmission target, so that two systems of video signals SV1 and SV2 can be transmitted with a simple structure.

FIG. 6 is a block diagram showing the serial data interface circuit 7 installed in the monitoring room. In the serial data interface circuit 7, the serial / parallel conversion circuit (S / P) 30 receives the transmission data DS from the coaxial cable 6 and detects the timing data from the transmission data DS. Further, the serial-parallel conversion circuit 30 converts the transmission data DS into parallel data based on this timing data and demodulates the multiplexed data DM.

Further, the serial / parallel conversion circuit 30 includes
With the detection cycle of the timing data as a reference, a reference signal whose signal level changes in a half cycle of the detection cycle is generated, and the reference synchronization signal HDD is demodulated thereby. Further, the serial-parallel conversion circuit 30 reproduces the clock CK2 of the transmission data DS by the built-in PLL circuit.

The selection circuit 31 outputs the 10-bit multiplexed data D output from the serial-parallel conversion circuit 30.
Of M, input the upper 8-bit multiplexed data DM,
As a result, the surplus bits added by the inverter circuits 24 and 25 during transmission are removed. Further, the selection circuit 31 switches the contact according to the reference synchronization signal HDD and alternately outputs the higher-order 8-bit multiplexed data DM to the memories 32 and 33, whereby the digital video signal multiplexed by the selection circuit 23 at the time of transmission. Separate DV1 and DV2.

The selection circuit 34 switches the contact according to the reference synchronization signal HDD and sets the clock CK2 to the memories 32 and 3.
Alternately output to 3. The 1/2 divider circuit 35 divides this clock CK2 by two to reproduce the clock CK1.

The memories 32 and 33 use the clock CK2 output from the selection circuit 34 as a reference to select the selection circuit 31.
Output digital video signals DV1 and DV2
Are sequentially stored, and the stored digital video signals DV1 and DV2 are output with reference to the clock CK1, whereby the time-axis-compressed and transmitted digital video signals DV1 and DV2 are time-axis expanded.

That is, in FIG. 7, the memories 32 and 3 are
As shown in the symbols W and R for the write and read positions for the memory space of 3, the memory 32 is
The writing / reading process is executed in units of one cycle of the reference synchronization signal HDD (FIG. 7 (A)), and in this one cycle, after the signal level of the reference synchronization signal HDD rises at time t1, time t2 is set. The digital video signal DV1 input from the selection circuit 31 is stored during the first half and the half cycle until the time point t3 (FIG. 7B).
Further, the memory 32 stores the digital video signal DV1.
The digital video signal DV1 stored at a speed half that at the time of writing is read out and output in accordance with the writing operation of (1), whereby the time-axis-compressed digital video signal DV1 is expanded in the time axis.

Similarly, the memory 33 stores the reference synchronization signal HDD
The writing / reading process is executed in a unit of one cycle, and in this one cycle, the signal level of the reference synchronization signal HDD falls at the time point t3, and then the time point t4 and then the time point t.
During the period of the second half and half cycle until reaching 5, the selection circuit 31
The input digital video signal DV2 is stored (FIG. 7C). Further, the memory 33 follows the write operation of the digital video signal DV2 and stores the digital video signal DV stored at a speed half that at the time of writing.
2 is read out and output, whereby the time-axis-compressed digital video signal DV2 is time-axis expanded.

Digital-analog conversion circuit (D / A) 3
7 and 38 digital-analog convert the digital video signals DV1 and DV2 output from the memories 32 and 33, respectively, and output them, thereby demodulating the video signals SV1 and SV2.

As a result, the serial data interface circuit 7 demodulates the transmission data DS multiplexed and transmitted based on the video signal SV1 into the original two-system video signals SV1 and SV2 based on the video signal SV1. The transmission data DS transmitted with a simple structure is demodulated accordingly.

The identification data detection circuit 39 detects various identification data added during transmission from the multiplexed data DM output from the serial / parallel conversion circuit 30. The sync signal generation circuit 40 receives the video signal SV from the detection result of the identification data detection circuit 39 and the reference sync signal HDD.
The horizontal synchronizing signal HDA and the vertical synchronizing signal VDA of 1 are generated and output. The delay circuit 41 includes the identification data detection circuit 3
Based on the detection result of 9, the horizontal synchronizing signal HDA and the vertical synchronizing signal VDA output from the synchronizing signal generating circuit 40 are delayed, whereby the horizontal synchronizing signal H of the video signal SV2 is delayed.
DB and vertical synchronization signal VDB are generated and output.

The signal processing circuit 42 switches its operation in response to a switching signal SW inputted by operating a prescribed operator, and in a normal operation, the video signal SV1 or SV.
2 is selectively output to the monitor device 4. At this time, the signal processing circuit 42 adds and outputs the corresponding horizontal synchronizing signal HDA or HDB and vertical synchronizing signal VDA or VDB. Accordingly, in the monitor device 4, one video signal S
The imaging result multiplexed by the coaxial cable 6 and serially transmitted based on V1 can be selectively monitored.

On the other hand, when the wipe mode is set, the signal processing circuit 42 selectively outputs the video signal SV1 in the first half of one horizontal scanning period with reference to the horizontal synchronizing signal HDA of the video signal SV1. In the remaining second half, the video signal SV2 is selectively output. Further, at this time, the signal processing circuit 42 adds the horizontal synchronizing signal HDA and the vertical synchronizing signal VDA of the video signal SV1 and outputs a video signal. Accordingly, when the horizontal synchronizing signals of the video signal SV1 and the video signal SV2 are synchronized, a wipe image as shown in FIG. 1 can be obtained, and two monitoring points can be observed at the same time.

On the other hand, in the wipe mode, when the user selects the video signal SV2, the signal processing circuit 4
The reference numeral 2 similarly selects and outputs the video signals SV1 and SV2 based on the horizontal synchronization signal HDB of the video signal SV2 instead of the horizontal synchronization signal HDA of the video signal SV1. Further, the signal processing circuit 42 replaces the horizontal synchronizing signal HDA and the vertical synchronizing signal VDA of the video signal SV1 with the horizontal synchronizing signal HDB and the vertical synchronizing signal VB of the video signal SV2.
DB is added and a video signal is output, whereby a display image of a wipe synchronized with the video signal SV2 is displayed.

As a result, the serial data interface circuit 7 can display the video signals SV1 and SV2 multiplexed and transmitted with the video signal SV1 as a reference, if necessary, with the video signal SV1 as a reference. Further, the identification data inserted at the time of transmission can be displayed in a desired form as a reference, and the usability can be improved with a simple structure.

In the above structure, the video signals SV1 and SV2 as the image pickup result are converted into digital video signals DV1 and DV2 with the clock CK1 generated from the video signal SV1 as a reference in the analog-digital conversion circuits 17 and 18, respectively. Memory 19
And 20 and is time-compressed in units of one horizontal scanning period of the digital video signal DV1 with reference to the clock CK2 generated from the video signal SV1 and the reference synchronization signal HDD.

The time-axis-compressed digital video signals DV1 and DV2 are multiplexed through the selection circuit 23 with the reference synchronization signal HDD as a reference, and the subsequent inverter circuits 24 and 25 provide the resulting multiplexed data. DM
The surplus bit formed by inverting the lower 2 bits is added to
The DC component is removed.

Timing data is added to the multiplexed data DM by the subsequent identification data adding circuit 27 during a fixed period corresponding to the start of horizontal scanning of the video signal SV1 with reference to the reference synchronizing signal HDD, and further the video signal SV1.
Of the vertical synchronizing signal VDA and the horizontal synchronizing signals HDB and VDB of the video signal SV2 are added with identification data, respectively, and the parallel-to-serial conversion circuit 28 makes the transmission data DS of serial data. It is converted and sent to the coaxial cable 6.

As a result, the two video signals SV1 and SV2 are clocked by clocks CK1 and CK generated by one reference signal generation system with the video signal SV1 as a reference.
2. Based on the reference synchronization signal HDD, the digital video signals DV1 and DV2 are converted and time-axis-compressed, then multiplexed and sent out to the transmission target in the form of serial data.

The transmission data DS thus transmitted to the transmission target is demodulated in the serial-parallel conversion circuit 30 into 10-bit parallel multiplexed data DM based on the timing data added at the time of transmission, and is also transmitted. The reference synchronization signal HDD used as the operation reference at that time is reproduced. After the redundant bits are removed, the multiplexed data DM is applied to the reference synchronizing signal HD in the subsequent selection circuit 31.
Digital video signals DV1 and DV2 with reference to D
And the digital video signals DV1 and DV
In the memories 32 and 33, which are followed by 2, the time is expanded.

The time-axis expanded digital video signals DV1 and DV2 are converted into video signals SV1 and SV2 by the digital-analog conversion circuits 37 and 38 and input to the signal processing circuit 42, contrary to the transmission.
In this signal processing circuit 42, the video signals SV1 and SV2 are added with the corresponding horizontal synchronizing signal and vertical synchronizing signal in response to the switching signal SW, and are output to the monitor device 4, whereby the monitoring cameras 2 or 3 are monitored. The imaging result is monitored by the monitor device 4.

On the other hand, in the wipe mode, the video signals SV1 and SV2 are alternately output with reference to the horizontal scanning period of the video signal SV1 or SV2, and the video signal SV1 or SV2 is output in response to the switching signal SW. Corresponding horizontal synchronizing signals and vertical synchronizing signals are added, whereby an image of the wipe is displayed on the monitor device 4 and two monitoring points can be observed at the same time.

According to the above configuration, the video signals SV1 and SV2 are digital video based on the clocks CK1 and CK2 and the reference synchronization signal HDD which are generated by one reference signal generation system based on the video signal SV1. By converting the signals to DV1 and DV2, compressing them on the time axis, multiplexing them, and sending them out in the form of serial data to the transmission target, two systems of video signals can be multiplexed and serially transmitted with a simple configuration. .

Further, the transmission data DS transmitted on the basis of the video signal SV1 is demodulated, and if necessary, the video signal SV1 is used as a reference and the identification data added at the time of transmission is used as a reference. By selectively outputting SV1 and SV2, the transmitted video signals SV1 and SV2 can be demodulated and displayed in a desired form, and the usability can be improved with a simple configuration.

In the above embodiment, the case where the video signals of two systems are multiplexed and transmitted is described.
The present invention is not limited to this, and can be widely applied to the case of transmitting video signals of a plurality of systems.

Further, in the above-mentioned embodiments, the case where the analog video signal is converted into the digital video signal and multiplexed is described, but the present invention is not limited to this, and the digital video signal is multiplexed. The present invention can be widely applied to the case of transmission after being converted.

In the above embodiments, the case where the present invention is applied to the monitoring system has been described, but the present invention is not limited to this and can be widely applied to various transmission systems.

[0056]

As described above, according to the present invention, among a plurality of digital video signals, one of these digital video signals is synchronized with the horizontal synchronizing signal of one digital video signal, and these plurality of digital video signals are The time axis compression is performed, and the plurality of time axis compressed digital video signals are multiplexed and converted into serial data.
Multiple channels of video signals can be multiplexed and serially transmitted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a serial data interface circuit applied to a monitoring system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an overall configuration of the monitoring system of FIG.

FIG. 3 is a signal waveform diagram for explaining the operation of the serial data interface circuit of FIG.

FIG. 4 is a signal waveform diagram for explaining processing of a video signal of the serial data interface circuit of FIG.

5 is a signal waveform diagram for explaining timing data of the serial data interface circuit of FIG.

FIG. 6 is a serial data interface circuit 7 of FIG.
FIG.

7 is a signal waveform diagram for explaining the operation of the serial data interface circuit of FIG.

[Explanation of symbols]

1 Monitoring System 2, 3 Monitoring Camera 4 Monitoring Device 5, 7 Serial Data Interface Circuit 6 Coaxial Cable 10 PLL Circuit 17, 18 Analog-to-Digital Conversion Circuit 19, 20, 32, 33 Memory 27 Identification Data Addition Circuit 28 Parallel-Serial Conversion Circuit 30 Serial-parallel conversion circuit

Claims (2)

[Claims] 1. Among a plurality of digital video signals,
Reference signal generating means for generating a reference signal in synchronization with the horizontal synchronizing signal of one digital video signal, and the plurality of digital videos in units of the horizontal scanning period determined by the horizontal synchronizing signal with the reference signal as a reference. And a data conversion unit that multiplexes the time-axis compressed digital video signals and converts the signals into serial data. 2. The data converting means inserts, into the digital video signals, identification data for identifying a horizontal blanking period and a vertical blanking period of each digital video signal, and then converts the data into the serial data. The multiplexing device according to claim 1, wherein: