JP3275489B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus used for an information processing apparatus such as a personal computer, a work station, and an office computer.

[0002]

2. Description of the Related Art Conventionally, a bus for an information processing apparatus is a system in which an address and data are multiplexed, and a read operation is divided into independently completed address transfer transactions and data transfer transactions. Examples of a bus having split transfer means and so-called source synchronous transfer means for performing transfer at a timing synchronized with a source clock supplied from an output source during data transfer include, for example, IEE, Draft Standard P896. .1R / D8.5: Futurebus Plus Logical Layer Specifications (1991) pp. 63-104 (IEEE D
raft Standard P896.1R / D8.
5: Futurebus + Logical Layer
r Specifications, IEEE Com
puter Society Press (1991)
Future Bus Plus described in PP63-104) is known.

In recent years, buses have become an important technology for improving system performance, and higher performance is required. As one of effective methods for responding to the problem of increasing the speed of the bus, a source synchronous transfer method is being adopted. The source synchronous transfer method has advantages in that the clock distribution skew is small and the transfer frequency can be easily increased.

On the other hand, a CPU bus, a system bus, an IO bus, and the like are separated via a bus adapter from conflicting demands for following the CPU performance and compatibility with existing IOs, multi-line and various IO connection requests, and the like. The so-called bus hierarchy is increasing.

[0005]

In a system in which these conventional techniques are combined, that is, a bus system in which source-synchronous buses (including one-to-one paths and channels) are hierarchically connected, modules on the same bus are used. Transfers between competitors are performed at high speed by the source synchronous transfer method.However, the problem of transfer across the bus hierarchy is that the original advantage of the source synchronous transfer method cannot be fully utilized due to the overhead of bus conversion at the bus connection. there were. An object of the present invention is to prevent a decrease in access speed due to a bus conversion overhead or the like in a bus connection unit in an information processing system using hierarchically connected source synchronous buses.
It is an object of the present invention to provide a high-speed bus control system that can fully utilize the original superiority of the source synchronous transfer system, and a bus system therefor.

[0006]

According to the present invention, in order to achieve the above object, a bus system (including one-to-one paths and channels) adopting a source synchronous transfer system is hierarchically connected to each other. Means (1) to (3) are provided.

(1) In the data transfer source module,
A means for recognizing the transfer destination module and the bus to which it is connected by decoding the access address, converting the transfer speed to the transfer speed of the bus, and transmitting data and a clock is provided.

(2) In the data transfer source module,
In addition to the bus to which the own module is connected, there is provided means for simultaneously acquiring a bus use right of another hierarchy required as a transfer path.

(3) In the bus converter, there is provided means for allowing the data and the transfer clock signal supplied from the data transfer source module to pass through the inside of the bus converter and to flow on the bus of another hierarchy as it is.

[0010]

According to the above means, even if the access destination is on a different hierarchical bus, the data and the transfer clock signal supplied by the data transfer source module can be received by the slave module as it is. Thus, the source synchronous transfer method can be applied. That is,
Conventionally, data is once latched by a bus converter, and then
A process that started data transfer to the next layer can be realized as a source synchronous transfer similar to a bus in the same layer by delaying only the internal delay of the bus converter, improving the transfer speed. Can be done.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing an internal configuration of a bus converter for connecting source synchronous buses of a bus system according to the present invention and a bus master module connected to each source synchronous bus. FIG. FIG. 3 is a block diagram showing an application example in which the present invention is applied to a hierarchically connected bus system. FIGS. 3 and 4 show an application of the present invention applied to a system in which a source synchronous bus and a source synchronous type channel (one-to-one) are hierarchically connected. System configuration diagram showing an example,
FIG. 5 is a system configuration diagram showing an application example in which the present invention is applied to a system in which source synchronous channels are hierarchically connected, FIG. 6 is an access timing chart of a bus system according to the present invention, and FIG. FIG. 8 is a flowchart of an example of the operation, and FIG. 8 is an access time chart for each transfer destination module.

In FIG. 1, reference numeral 1 denotes a bus converter for connecting the source synchronous buses of the present embodiment, 2 denotes a bus master module connected to one hierarchical source synchronous bus (A bus), and 3 denotes a bus master module. A bus master module connected to the other layered source synchronous bus (B bus), 4 to 8 are components of the bus master module 2,
4 is an input data buffer, 5 is an output data buffer, 6
Is a transmission clock control unit, 7 is a transmission control unit, 8 is a bus arbiter for arbitrating the A bus, 9 and 10 are bidirectional input / output drivers, 11 to 24 are components inside the bus converter 1, and 11 is an input. A data buffer, 12 is an input data buffer, 13 is a transmission clock control unit, 14 is a bus right control unit of A bus, 15 is a transmission / reception control unit, 16 is a bus arbiter that performs bus arbitration of B bus, 17, 18, and 19 , And 20 are bidirectional input / output drivers, 21, 22, 23 and 24 are selectors, 25 to 31 are components of the bus master module 3, 25 is an input data buffer, 26
Is an output data buffer, 27 is a transmission clock controller, 2
8 is a transmission control unit, 29 is a bus right control unit of the B bus, 30 and 31 are bidirectional input / output drivers, 32 is a clock line of the A bus which is a source synchronous bus, and 33 is a data line of the A bus (address is also used). , 34 is a clock line of a B bus which is a source synchronous bus, 35 is a data line (including an address) of a B bus, 36 is an arbitration control signal of an A bus, 37 is an arbitration control signal of a B bus, 38
, An arbitration control signal for the B bus, 39, an arbitration control signal for the B bus, 39, an inter-layer source synchronous transfer request signal for which the bus master module 3 is the master, and 40, an internal signal of the bus converter 1. A control register, 41 is a source synchronization transfer permission signal across the hierarchy in which the bus master module 2 is the master, 42 is a source synchronization transfer permission signal in the hierarchy, the bus master module 3 is the master, 43 is the access address decoder, and 44 is the access destination module. A clock speed converter 45, an address-specific module table 45 for associating an access address with an access destination module, 46 an access address decoder, 47 a clock speed converter corresponding to an access destination module, 48
Is an address-specific module table that associates access addresses with access destination modules. In FIG. 2, reference numeral 101 denotes a processor, 102 denotes a processor and a main storage device interface device, 103 denotes a main storage device,
04 is a system bus which is a source synchronous bus, 105 and 106 are IO buses which are source synchronous buses, 111
Is a bus converter for connecting the system bus 104 and the IO bus 105; 112 is a bus converter for connecting the system bus 104 and the IO bus 106;
Reference numerals 7, 108, 109 and 110 are IO adapter devices. In FIG. 3, reference numeral 113 denotes a channel for transferring data between the processor and the main storage device interface device 102 and the IO bus 105; 114, a channel for transferring data between the processor and the main storage device interface device 102 and the IO bus 106; A bus converter for connecting the channel 113 to the IO bus 105, and a bus converter 116 for connecting the channel 114 to the IO bus 106. In FIG. 4, 117 is the system bus 10
Channel for transferring data between 4 and IO adapter 107, 11
8, a channel for transferring data between the system bus 104 and the IO adapter 108; 119, a channel for transferring data between the system bus 104 and the IO adapter 109; 120, a channel for transferring data between the system bus 104 and the IO adapter 110; A converter for connecting the system bus 104 to the channels 117 and 118, and a converter 122 for connecting the system bus 104 to the channels 119 and 120. In FIG. 5, 123 and 124 are channels,
125 is a channel for transferring between the channel 123 and the IO adapter 107; 126 is a channel for transferring between the channel 123 and the IO adapter 108; 127 is a channel 1
Channel for transferring data between I / O 24 and IO adapter 109, 1
28 is a channel for transferring data between the channel 124 and the IO adapter 110, 129 is a channel 123 and a channel 12
Converter 130 connects channels 5 and 126, and converter 130 connects channel 124 to channels 127 and 128. In FIG. 6, 601 to 608 are time charts at the time of data transfer from the bus master module 2 to the bus master module 3, 601 is A bus data observed at the terminal of the master module 2, and 602 is observed at the terminal of the master module 2 A bus clock, 603
Is the data of the A bus observed at the terminal of the bus converter 1, 6
04 is the clock of the A bus observed at the terminal of the bus converter 1, 605 is the data of the B bus observed at the terminal of the bus converter 1, 606 is the clock of the B bus observed at the terminal of the bus converter 1, and 607 is Is the B bus data observed at the terminal of the master module 3, and 608 is the master module 3
Are the clocks of the B bus observed at the terminal (1). In FIG. 8, 801, 802, 803 and 804 are transfer time charts from the processor / main storage interface 102 to the IO adapter 107 which is a module on the IO bus 105, and 801 is observed at a terminal of the processor / main storage interface 102. 802, a clock waveform observed at a terminal of the processor / main memory interface 102, 803, a data waveform observed at a terminal of the IO adapter 107, 804, an IO adapter 107
805, 806, 8
Reference numerals 07 and 808 denote transfer time charts from the processor / main storage interface 102 to the IO adapter 109, which is a module on the IO bus 106. Reference numeral 805 denotes a data waveform observed at the terminal of the processor / main storage interface 102; The waveform of the clock observed at the terminal of the main memory interface 102, 80
Reference numeral 7 denotes a data waveform observed at the terminal of the IO adapter 109, and reference numeral 808 denotes a clock waveform observed at the terminal of the IO adapter 109. First, consider a system configuration in which source-synchronous buses in FIG. 2 are hierarchically connected. When the processor 101 performs processor IO access (PIO) and direct memory access (DMA), both pass through a path in which source synchronous buses are hierarchically connected. Here, the processor and main storage device interface device 102 as components of FIG. 2, a system bus 104 as a source synchronous bus, a bus converter 111 for connecting the system bus 104 and the IO bus 105, a source synchronous IO The bus 105 and the IO adapter 107 have structures such as the bus master module 2, the source synchronous bus (A bus), the bus converter 1, the source synchronous bus (B bus), and the bus master module 3 in FIG.

When performing PIO access that is activated from the bus master module 2 side, the bus master module 2
Determines from the decoder 43 and the module table 45 by address which module the transfer address is to access. Here, the contents of the address-specific module table 45 are set by PIO access. As a result, B that allows source synchronous transfer across layers
When it is determined that the request is for a module on the bus, a source synchronous transfer request is made to the bus converter 1 across the hierarchy using the control signal 38. After receiving this, the bus converter 1 obtains the bus right of the B bus, and then transmits a permission for source-synchronous transfer across the hierarchy to the bus master module 2 using the control signal 41. The master module 2 having received the source-synchronous transfer permission between the hierarchies includes the clock speed converter 44.
As a result, the transfer operation in accordance with the speed of the B bus connected to the module 3 is started. The output data sent from the output data buffer 5 is output from the bidirectional input / output buffers 9 and 10 onto the A bus together with the source clock generated by the transmission clock controller 6. The bus converter 1 takes in transfer data and a clock from the bidirectional input / output buffers 17 and 18. In the source transfer mode across layers, unlike the normal access, the bus converter 1 does not store the data in the internal input data buffer 11 but directly transmits the data to the B bus through the selector 21 and the bidirectional input / output buffer 19. . Similarly, the clock is transmitted to the B bus 3 via the selector 23 and the bidirectional input / output buffer 20.
4 is output. The master module 3 uses the clock fetched from the bidirectional input / output buffer 31 to convert the data fetched from the bidirectional input / output buffer 30 into the input data buffer 25 And a series of operations from the master module 2 to the master module 3 is completed. In this case, the transfer pitch of the source synchronous transfer across the hierarchy differs depending on the performance of the IO bus. FIG. 8 shows the difference between the transfer using the system bus 104 and the IO bus 105 and the transfer using the system bus 104 and the IO bus 106. During source-synchronous transfer between layers using the system bus 104 and the IO bus 105, transfer between IO adapters on the IO bus 105 is possible. On the other hand, the system bus 104 and the IO bus 1
During the source-synchronous transfer between layers using the IO bus 06, the IO bus 1
05 can be transferred between IO adapters. FIG. 7 shows this operation in a flowchart. (After start, 701: Access request generated in module 2, 70
2: Request for source-synchronous transfer across the hierarchy to the bus converter 1, 703: The bus converter 1 requests a bus right to the B bus arbiter, 704: Wait until the B bus bus right is acquired, 705: From the bus converter 1 706: Module 2 sends transmission data and clock to module 2, 706: Module 2 sends transmission data and clock, 707: Bus converter 1 passes data and clock transmitted by module 2 to B bus simply, 708 : The module 3 takes in the clock and data on the B bus, latches the data, and terminates. Conversely, when performing DMA access that is started from the bus master module 3 side, the bus master module 3
Decoder 46 and address-specific module table 48
Is used to determine which module the transfer address accesses. As a result, when it is determined that the request is for a module on the B bus that can perform source-synchronous transfer across layers, a request for source-synchronous transfer across layers is made to the bus converter 1 using the control signal 39. The bus converter 1 having received the request acquires the bus right of the A bus by using the arbitration control signal 36 of the A bus, and then transmits the source synchronous transfer permission across the hierarchy to the bus master module 3 by using the control signal 42. The master module 3 that has received the source-synchronous transfer permission between layers starts the transfer operation by the clock speed converter 47 in accordance with the speed of the A bus to which the module 2 is connected. Output data buffer 2
The output data transmitted from the transmission clock control unit 2
Along with the source clock generated at 8, the signals are output from the bidirectional input / output buffers 30 and 31 onto the B bus. The bus converter 1 takes in transfer data and a clock from the bidirectional input / output buffers 19 and 20. In the source transfer mode across layers, unlike the normal access, the bus converter 1 does not store the data in the internal input data buffer 12 but directly transmits the data to the A bus through the selector 22 and the bidirectional input / output buffer 17. . Similarly, the clock is output to the A bus 32 via the selector 24 and the bidirectional input / output buffer 18. The master module 2 uses the clock fetched from the bidirectional input / output buffer 10 to transfer the data fetched from the bidirectional input / output buffer 9 irrespective of whether the mode is the source transfer mode across layers.
Latched in the input data buffer 4, the master module 3
A series of operations from to the master module 2 is completed.
Note that read access to both PIO and DMA is based on split transfer in which a read start cycle and a response data cycle can be divided by bus arbitration. Therefore, the PIO read response is an access started from the bus master module 3, and the DMA read response is an access started from the bus master module 2. FIG. 6 shows a time chart of access from the bus master module 2 to the bus master module 3. Both the waveforms of the data and the clock signal observed at the terminal of the bus master module 3 of the B bus are obtained from the waveform observed at the terminal of the master module 2 of the A bus, based on the A bus propagation delay, the bus converter internal delay, and the B bus propagation delay. It is reported by the total time delayed. In the present embodiment, an application example of two layers is shown, but there is no problem even if the cross-layer source synchronization method of the present invention is applied to three or more layers. In addition, as a system configuration, when the upper side becomes a channel and the lower side becomes a bus as shown in FIG. 3, when the upper side becomes a bus and the lower side becomes a channel as shown in FIG. 4, both the upper and lower sides as shown in FIG. Although the operation may be a channel, each of the operations described above does not include the process of acquiring the bus right in advance when the opposite side of the activation bus master module is a channel across the bus converter. Becomes

As described above, when the system of this embodiment is used, when a source synchronous bus or channel is hierarchically connected, even if the access destination is on a different hierarchical bus, the data transfer source module is used. Since the data and the transfer clock signal supplied by the slave module can be received as they are, the source synchronous transfer method can be applied across the bus hierarchy. That is, the process of latching data once by the bus converter and then starting data transfer to the next hierarchical bus is the same as that of a bus in the same hierarchy, only delayed by the internal delay of the bus converter. This can be realized as source synchronous transfer, and has the effect of improving the transfer speed.

[0015]

According to the present invention, even when the access destination is on a different hierarchical bus, the data and the transfer clock signal supplied from the data transfer source module can be received by the slave side module as it is. The source synchronous transfer method can be applied across layers. That is, the process of latching data once by the bus converter and then starting data transfer to the next hierarchical bus is the same as that of a bus in the same hierarchy, only delayed by the internal delay of the bus converter. This can be realized as source synchronous transfer, and has the effect of improving the transfer speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an internal configuration of a bus converter for connecting source synchronous buses of a bus system according to the present invention and a bus master module connected to each source synchronous bus.

FIG. 2 is a system configuration diagram showing a configuration example in which the present invention is applied to a bus system in which source synchronous buses are hierarchically connected.

FIG. 3 is a system configuration diagram showing a configuration example in which the present invention is applied to a system in which a source synchronous bus and a source synchronous channel are hierarchically connected.

FIG. 4 is a system configuration diagram showing a configuration example in which the present invention is applied to a system in which a source synchronous bus and a source synchronous channel are hierarchically connected.

FIG. 5 is a system configuration diagram showing a configuration example in which the present invention is applied to a system in which source synchronous channels are hierarchically connected.

FIG. 6 is an access timing chart of the bus system according to the present invention.

FIG. 7 is a flowchart of an example of the operation of the bus system according to the present invention.

FIG. 8 is an access time chart for each transfer destination module according to the present invention.

[Description of Signs] 1. Bus conversion device for connecting source-synchronous buses to each other 2. Bus master module connected to one layered source-synchronous bus (A bus) 3. Other layered Bus master module connected to a source synchronous bus (B bus), 4 ... input data buffer, 5 ... output data buffer, 6 ... transmission clock control unit, 7 ... transmission control unit, 8 ... bus arbitration of A bus Bus arbiter, 9, 10 bidirectional input / output driver, 11 input data buffer, 12 input data buffer, 13 transmission clock control unit, 14 A bus bus right control unit, 15 transmission / reception control unit, 16 ... Bus arbiter for bus arbitration of B bus 17, 18, 19, 20 ... bidirectional input / output driver, 21, 22, 23, 24 ... selector, 25 ... input data 26, an output data buffer, 27, a transmission clock control unit, 28, a transmission control unit, 29, a bus right control unit for the B bus, 30, 31, a bidirectional input / output driver, 32, a source synchronous bus A A clock line of the bus; 33 a data line (including an address) of the A bus; 34 a clock line of a B bus which is a source synchronous bus; 35 a data line of the B bus (including an address); An arbitration control signal, 37 an arbitration control signal for the B bus, 38 an inter-layer source synchronous transfer request and permission signal for which the bus master module 2 is the master, an arbitration control signal for the B bus 39, and the bus master module 3 as the master Source synchronous transfer request and permission signal across hierarchy, 40 ... Control inside bus converter 1

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-201154 (JP, A) JP-A-63-120355 (JP, A) JP-A-58-219627 (JP, A) (58) Investigation Field (Int.Cl. ⁷ , DB name) G06F 13 / 28,13 / 36 G06F 13 / 38,13 / 42

Claims (7)

(57) [Claims] (1)A first bus to which a first module is connected
A second bus to which the second module is connected, and a data bus.
A buffer for storing the first bus and the first bus.
And a bus converter for hierarchically connecting the two buses.
A data transfer between the first bus and the second bus;
If the first module is a bus clock of the first bus,
Output the data in the data converter, and the bus converter outputs the data
Is stored in a buffer in the bus converter, and the first
The bus clock of the bus is used as the bus clock of the second bus.
After the conversion, the bus clock of the second bus
An information processing device for transferring to a bus, The first module includes the first bus and the second bus.
Sends a control signal indicating a source synchronous transfer request across the bus.
A transmission control unit for receiving The bus converter outputs the first module.
Acquiring a right to use the second bus based on the control signal
And the data and the query sent from the first module.
Lock signal is sent through a signal line that does not pass through the buffer.
Information processing means for transferring data to the second bus.
Equipment. 2. The information processing apparatus according to claim 1, wherein the first module transfers data output from the first module to the second module together with a clock of the second module. An information processing apparatus comprising: means. 3. An information processing apparatus according to claim 2, wherein said first module has means for transmitting said transfer data in synchronization with a transfer speed of said second bus. Information processing device. 4. The information processing apparatus according to claim 1, wherein the first module includes a first bus arbiter for acquiring a right to use a bus of the first bus, and a second module included in the bus conversion unit. An information processing apparatus, comprising: a transmission control unit for controlling a bus arbiter to acquire a right to use a second bus. 5. The information processing apparatus according to claim 1, wherein the bus converter receives a source synchronous transfer request signal from the first module and transmits a source synchronous transfer permission signal to the transfer source module. And a means for acquiring a bus use right of the second bus after receiving the source synchronous transfer request signal. 6. The information processing apparatus according to claim 1, wherein at least one of said first bus and said second bus is a source-synchronous channel connected one-to-one. Characteristic information processing device. 7. A first module as a transfer source, a second module as a transfer destination, a first bus connected to the first module, and a first bus connected to the second module. An information transfer method for transferring information from the first module to the second module in an information processing apparatus having a second bus and a bus converter that connects the first bus and the second bus. Generating an access request from the first module to the second module; requesting a source synchronous transfer to the bus converter; and providing a second request to the second bus arbiter. Requesting a right to use a bus of a bus; transmitting a source synchronous transfer permission signal from the bus converter to the first module; Information transfer method characterized by comprising the steps of: sending a clock, and a step of passing through the bus converter the data and the source clock.