JP3271215B2 - Pad section and method of forming the same - Google Patents

Pad section and method of forming the same

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Publication number
JP3271215B2
JP3271215B2 JP24387293A JP24387293A JP3271215B2 JP 3271215 B2 JP3271215 B2 JP 3271215B2 JP 24387293 A JP24387293 A JP 24387293A JP 24387293 A JP24387293 A JP 24387293A JP 3271215 B2 JP3271215 B2 JP 3271215B2
Authority
JP
Japan
Prior art keywords
conductive layer
layer
forming
orientation
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP24387293A
Other languages
Japanese (ja)
Other versions
JPH0774204A (en
Inventor
照峰 平山
義洋 尼崎
克也 亀岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
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Application filed by Sony Corp filed Critical Sony Corp
Priority to JP24387293A priority Critical patent/JP3271215B2/en
Publication of JPH0774204A publication Critical patent/JPH0774204A/en
Application granted granted Critical
Publication of JP3271215B2 publication Critical patent/JP3271215B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05017—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、パッド部及びその形成
方法に関し、特には、半導体装置において基板上に形成
されるパッド部及びその形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pad portion and a method for forming the same, and more particularly to a pad portion formed on a substrate in a semiconductor device and a method for forming the same.

【０００２】[0002]

【従来の技術】半導体装置では、基板上に形成される配
線と外部端子との接続を図るために、上記基板上にパッ
ド部が形成されている。このパッド部は、上記配線を形
成する導電層と同じ導電層で形成されるものである。2. Description of the Related Art In a semiconductor device, a pad portion is formed on a substrate in order to connect a wiring formed on the substrate to an external terminal. This pad portion is formed of the same conductive layer as the conductive layer forming the wiring.

【０００３】一方、半導体装置の高速化及び高集積化に
伴い、デバイス構造の多層化と微細化とが進展してい
る。上記多層化の進展によって、各導電層は薄膜化する
傾向にある。このため、上記パッド部の構造も、例え
ば、ワイヤボンディング時の衝撃によって基板に加えら
れるダメージを防止するために、複数の導電層を積層し
た多層構造で形成される。[0003] On the other hand, with the increase in speed and integration of semiconductor devices, multilayering and miniaturization of device structures are progressing. With the progress of the multilayering, each conductive layer tends to be thinner. Therefore, the structure of the pad portion is also formed in a multilayer structure in which a plurality of conductive layers are stacked, for example, in order to prevent damage to the substrate due to impact during wire bonding.

【０００４】さらに、デバイス構造の微細化の進展によ
って、各導電層間の電気的な導通を図るための接続孔で
はアスペクト比が高くなる傾向にある。このため、上層
導電層の形成には、高アスペクト比の接続孔の埋め込み
特性に優れた高温スパッタ法を適用することが提案され
ている。この高温スパッタ法は、スパッタリングによる
導電層の成膜時に、成膜雰囲気の温度を４００℃〜６０
０℃に設定して成膜を行う方法である。[0004] Further, as the device structure is miniaturized, the aspect ratio tends to increase in connection holes for achieving electrical continuity between the conductive layers. For this reason, it has been proposed to apply a high-temperature sputtering method which is excellent in filling characteristics of a connection hole having a high aspect ratio in forming the upper conductive layer. In this high-temperature sputtering method, when forming a conductive layer by sputtering, the temperature of the film formation atmosphere is set to 400 ° C. to 60 ° C.
In this method, the film is formed at a temperature of 0 ° C.

【０００５】上記高温スパッタ法を用いて上層導電層を
成膜する場合の、パッド部の形成方法の一例を以下に説
明する。先ず、図４（１）に示すように、基板４０１の
表面に第１の層間絶縁膜４０２を成膜する。そして、第
１の層間絶縁膜４０２の上面に、アルミニウム系金属か
らなる下層導電層４０３を成膜し、この下層導電層４０
３をパッド部の形状にエッチングする。その後、下層導
電層４０３を覆う状態に第１の層間絶縁膜４０２の上面
に第２の層間絶縁膜４０４を成膜する。そして、この第
２の層間絶縁膜４０４に下層導電層４０３に達する接続
孔４０５を形成する。[0005] An example of a method of forming a pad portion when the upper conductive layer is formed by using the high-temperature sputtering method will be described below. First, as shown in FIG. 4A, a first interlayer insulating film 402 is formed on a surface of a substrate 401. Then, on the upper surface of the first interlayer insulating film 402, a lower conductive layer 403 made of an aluminum-based metal is formed.
3 is etched into the shape of the pad portion. After that, a second interlayer insulating film 404 is formed on the upper surface of the first interlayer insulating film 402 so as to cover the lower conductive layer 403. Then, a connection hole 405 reaching the lower conductive layer 403 is formed in the second interlayer insulating film 404.

【０００６】次に、図４（２）に示すように、接続孔４
０５の内部を含む第２の層間絶縁膜４０４の上面に、高
温スパッタ法にてアルミニウム系金属からなる上層導電
層４０６を成膜する。そして、この上層導電層４０６を
パッド部の形状にエッチングし、基板４０１上に下層導
電層４０３と上層導電層４０６とを積層した構造のパッ
ド部４を形成する。Next, as shown in FIG.
An upper conductive layer 406 made of an aluminum-based metal is formed on the upper surface of the second interlayer insulating film 404 including the inside of the substrate 05 by a high-temperature sputtering method. Then, the upper conductive layer 406 is etched into a shape of a pad portion, and the pad portion 4 having a structure in which the lower conductive layer 403 and the upper conductive layer 406 are stacked on the substrate 401 is formed.

【０００７】その後、例えば、上層導電層４０６を覆う
状態に上層絶縁膜４０７を成膜し、この上層絶縁膜４０
７に上層導電層４０６に達する接続孔４０８を形成す
る。After that, for example, an upper insulating film 407 is formed so as to cover the upper conductive layer 406.
7, a connection hole 408 reaching the upper conductive layer 406 is formed.

【０００８】[0008]

【発明が解決しようとする課題】しかし、上記のように
して形成されたパッド部には、以下のような課題があっ
た。すなわち、図４に示したように、アルミニウム系金
属からなる下層導電層４０３及び上層導電層４０６の表
面には、成膜時の配向性の問題から凹凸が形成される。
そして、高温スパッタ法によって成膜される上層導電層
４０６は、下層導電層４０３の配向性を引き継ぎ易い。
このため、パッド部４の表面になる上層導電層４０６の
表面では、下層導電層４０３の凹凸の度合いがさらに拡
大されて表面粗れが発生する。However, the pad portion formed as described above has the following problems. That is, as shown in FIG. 4, irregularities are formed on the surfaces of the lower conductive layer 403 and the upper conductive layer 406 made of an aluminum-based metal due to the problem of orientation during film formation.
Then, the upper conductive layer 406 formed by a high-temperature sputtering method easily inherits the orientation of the lower conductive layer 403.
For this reason, on the surface of the upper conductive layer 406 which becomes the surface of the pad portion 4, the degree of unevenness of the lower conductive layer 403 is further enlarged, and surface roughness occurs.

【０００９】そして、上記のように表面粗れが発生した
パッド部４では、表面反射率が低下するために、ワイヤ
ボンディング時のアライメント精度が低下し、ボンディ
ングの位置ずれが発生する。In the pad portion 4 where the surface is roughened as described above, the surface reflectance is reduced, so that the alignment accuracy at the time of wire bonding is reduced, and a displacement of bonding occurs.

【００１０】そこで、本発明は上記の課題を解決するパ
ッド部及びその形成方法を提供することによって、半導
体装置の信頼性と歩留りの向上を図ることを目的とす
る。Accordingly, an object of the present invention is to improve the reliability and yield of a semiconductor device by providing a pad portion and a method for forming the pad portion which solve the above-mentioned problems.

【００１１】[0011]

【課題を解決するための手段】上記の目的を達成するた
めの本発明のパッド部は、基板上に成膜されたアルミニ
ウム系金属からなる下層導電層と、当該下層導電層上に
高温スパッタ法によって成膜されたアルミニウム系金属
からなる上層導電層とで構成されたパッド部である。こ
のパッド部において、上層導電層は、チタン層、窒化系
チタン層およびチタン層を下層から順次積層してなる配
向性改善膜を介して前記下層導電層上に積層されてい
る。According to the present invention, there is provided a pad portion comprising: a lower conductive layer made of an aluminum-based metal formed on a substrate; and a high-temperature sputtering method formed on the lower conductive layer. And a upper conductive layer made of an aluminum-based metal formed by the above method. In this pad portion, the upper conductive layer is a titanium layer, a nitride-based layer.
A titanium layer and a titanium layer are stacked on the lower conductive layer via a directivity improving film formed by sequentially stacking the titanium layers from the lower layer .

【００１２】さらに、上記構造のパッド部の形成方法
は、先ず、第1の工程で基板上に下層導電層を成膜す
る。次いで、第２の工程で下層導電層上に、チタン層、
窒化系チタン層およびチタン層を下層から順次積層して
配向性改善膜を形成する。そして、第３の工程でこの配
向性改善膜上に高温スパッタ法によって上層導電層を成
膜する。Further, in the method of forming the pad portion having the above structure, first, a lower conductive layer is formed on a substrate in a first step. Next, in a second step, a titanium layer is formed on the lower conductive layer,
A nitrided titanium layer and a titanium layer are sequentially laminated from the lower layer to form an orientation improving film. Then, in a third step, an upper conductive layer is formed on the orientation improving film by a high-temperature sputtering method.

【００１３】[0013]

【作用】上記パッド部では、下層導電膜と上層導電膜と
の間に窒化系チタン層を含む配向性改善膜を設けたこと
で、下層導電層の配向性がこの配向性改善膜によって分
断される。このため、下層導電層の面粗れに起因して、
高温スパッタ法によって成膜された上層導電膜の表面に
粗れが生じることが防止される。そして特に、この配向
性改善膜を、チタン層、窒化系チタン層およびチタン層
の３層構造とし、窒化系チタン層をチタン層で挟んだ構
成としたことにより、上層のチタン層によって上層導電
層成膜時のヌレ性を改善することができ、また下層のチ
タン層によって下層導電層との密着性を改善することが
できるため、上層導電層の表面粗れを防止する効果をさ
らに高めることができる。 In the above pad portion, the lower conductive film and the upper conductive film are
Orientation improvement film including nitrided titanium layer between
Thus, the orientation of the lower conductive layer is separated by the orientation improving film.
Refused. Therefore, due to the surface roughness of the lower conductive layer,
On the surface of the upper conductive film formed by high-temperature sputtering
The occurrence of roughness is prevented. And especially this orientation
A titanium layer, a nitrided titanium layer and a titanium layer
And a nitrided titanium layer sandwiched between titanium layers
The upper conductive layer is formed by the upper titanium layer.
It is possible to improve wettability when forming a layer,
It is possible to improve the adhesion with the lower conductive layer by the tan layer.
The effect of preventing surface roughness of the upper conductive layer.
Can be further increased.

【００１４】さらに、上記パッド部の形成方法では、下
層導電層上に窒化系チタン層を含む配向性改善膜を形成
し、この上部に上層導電層を成膜することで、下層導電
層の配向性がこの配向性改善膜によって分断され、上層
導電層の下地の配向性が改善される。そして、高温スパ
ッタ法によって成膜される上層導電層は、配向性改善膜
の配向性を引き継いで成膜されるため、形成されるパッ
ド部の表面は配向性が改善されて表面粗れが防止され
る。特に、チタン層、窒化系チタン層およびチタン層を
順次積層して配向性改善膜を形成することで、下層のチ
タン層によって配向性改善膜の密着性が改善され、また
上層のチタン層によって上層導電層成膜時のヌレ性を改
善されて、上層導電層の表面粗れを防止する効果をさら
に高めることができる。 Furthermore, in the method for forming the pad portion, the lower
Of an orientation-improving film containing a nitrided titanium layer on the conductive layer
By forming an upper conductive layer on this, the lower conductive layer is formed.
The orientation of the layer is separated by the orientation improving film, and the upper layer
The orientation of the base of the conductive layer is improved. And hot spa
The upper conductive layer formed by the sputtering method is an orientation improving film.
Since the film is formed while inheriting the orientation of
The surface of the metal part has improved orientation, preventing surface roughness.
You. In particular, titanium layer, nitrided titanium layer and titanium layer
By sequentially stacking to form an orientation improving film, the lower layer chip is formed.
The adhesion of the orientation improving film is improved by the tan layer,
Improved wetting property when forming upper conductive layer with upper titanium layer
To improve the effect of preventing surface roughness of the upper conductive layer.
Can be increased.

【００１５】[0015]

【実施例】以下、本発明のパッド部及びその形成方法の
実施例を図面に基づいて説明する。先ず、図１に示すよ
うに、実施例のパッド部１は、基板１１上に第１の層間
絶縁膜１２を介して成膜された下層導電層１３と、この
下層導電層１３に接続する状態で形成された配向性改善
膜１６と、この配向性改善膜１６上に成膜された上層導
電層１７とで構成されている。上記配向性改善膜１６と
上層導電層１７とは、下層導電層１３上の層間絶縁膜１
４に形成された接続孔１５の内部を埋め込む状態で形成
されている。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing an embodiment of a pad portion and a method of forming the same according to the present invention. First, as shown in FIG. 1, the pad portion 1 of the embodiment has a lower conductive layer 13 formed on a substrate 11 via a first interlayer insulating film 12 and a state in which the lower conductive layer 13 is connected to the lower conductive layer 13. And an upper conductive layer 17 formed on the orientation improving film 16. The orientation improving film 16 and the upper conductive layer 17 are the same as the interlayer insulating film 1 on the lower conductive layer 13.
4 is formed so as to bury the inside of the connection hole 15 formed therein.

【００１６】上記下層導電層１３は、例えば、１％のシ
リコンを含有するアルミニウム系金属を５００ｎｍの膜
厚で成膜してなる層であり、エッチングによってパッド
部１の形状にパターニングされている。The lower conductive layer 13 is, for example, a layer formed by depositing an aluminum-based metal containing 1% of silicon with a thickness of 500 nm, and is patterned into the shape of the pad portion 1 by etching.

【００１７】上記配向性改善膜１６は、下層導電層１３
の配向性を分断して上層導電層１７の配向性を改善する
ための膜であり、例えば、窒化チタンまたは酸化窒化チ
タンのような窒化系チタンを１００ｎｍの膜厚で成膜し
てなる層である。この配向性改善膜１６は、エッチング
によってパッド部１の形状にパターニングされている。
さらに、この配向性改善膜１６の上面と下面とには、こ
こでは図示しないチタン層が３０ｎｍの膜厚で成膜され
ている。このチタン層は下層導電層１３と配向性改善膜
１６との密着性を改善すると共に、上層導電層１７の成
膜時のヌレ性を改善する。The orientation improving film 16 is formed of the lower conductive layer 13.
Is a film for improving the orientation of the upper conductive layer 17 by dividing the orientation of the film, for example, a layer formed by forming a nitride-based titanium such as titanium nitride or titanium oxynitride to a thickness of 100 nm. is there. The orientation improving film 16 is patterned into the shape of the pad portion 1 by etching.
Further, a titanium layer (not shown) having a thickness of 30 nm is formed on the upper surface and the lower surface of the orientation improving film 16. This titanium layer improves the adhesion between the lower conductive layer 13 and the orientation improving film 16 and also improves the wetting property when the upper conductive layer 17 is formed.

【００１８】上層導電層１７は、高温スパッタ法によっ
て成膜されたアルミニウム系金属からなる層である。そ
して、例えば上記下層導電層１３と同様に、１％のシリ
コンを含有するアルミニウム系金属を７００ｎｍの膜厚
で成膜してなると共に、エッチングによってパッド部１
の形状にパターニングされている。The upper conductive layer 17 is a layer made of an aluminum-based metal formed by a high-temperature sputtering method. Then, similarly to the lower conductive layer 13, for example, an aluminum-based metal containing 1% silicon is formed to a thickness of 700 nm, and the pad portion 1 is etched.
Is patterned.

【００１９】上記構造のパッド部１では、下層導電層１
３の上面に配向性改善膜１６を介して上層導電層１７が
積層されている。このため、下層導電層１３と上層導電
層１７との配向性がこの配向性改善膜１６によって分断
された状態になっている。したがって、下層導電層１３
の配向性が上層導電層１７に引き継がれることによる上
層導電層の表面粗れが防止される。In the pad portion 1 having the above structure, the lower conductive layer 1
An upper conductive layer 17 is laminated on the upper surface of the substrate 3 via an orientation improving film 16. Therefore, the orientation of the lower conductive layer 13 and the orientation of the upper conductive layer 17 are separated by the orientation improving film 16. Therefore, the lower conductive layer 13
The upper conductive layer 17 is prevented from being roughened by the upper conductive layer 17 taking over the orientation.

【００２０】次に、上記パッド部の形成方法を説明す
る。先ず、図２（１）に示すように、基板１１の表面に
第１の層間絶縁膜１２を成膜する。Next, a method of forming the above pad portion will be described. First, as shown in FIG. 2A, a first interlayer insulating film 12 is formed on the surface of a substrate 11.

【００２１】そして、第１の層間絶縁膜１２の上面にア
ルミニウム系金属からなる下層導電層１３を成膜し、こ
の下層導電層１３をエッチングして形成しようとするパ
ッド部の形状にパターニングする。次いで、下層導電層
１３を覆う状態に、第１の層間絶縁膜１２の上面に第２
の層間絶縁膜１４を成膜する。そして、この第２の層間
絶縁膜１４に下層導電層１３に達する接続孔１５を形成
する。Then, a lower conductive layer 13 made of an aluminum-based metal is formed on the upper surface of the first interlayer insulating film 12, and the lower conductive layer 13 is patterned by etching into a pad portion to be formed. Next, a second layer is formed on the upper surface of the first interlayer insulating film 12 so as to cover the lower conductive layer 13.
Is formed. Then, a connection hole 15 reaching the lower conductive layer 13 is formed in the second interlayer insulating film 14.

【００２２】次に、図２（２）に示すように、接続孔１
５の内壁を含む第２の層間絶縁膜１４の上面に、窒化系
チタンからなる配向性改善膜１６を形成する。そして、
配向性改善膜１６の上面と下面とには、ここでは図示し
ないチタン層を成膜する。Next, as shown in FIG.
On the upper surface of the second interlayer insulating film 14 including the inner wall of No. 5, an orientation improving film 16 made of titanium nitride is formed. And
On the upper and lower surfaces of the orientation improving film 16, a titanium layer (not shown) is formed.

【００２３】上記配向性改善膜１６及びチタン層とは、
例えば、以下のようにして形成する。先ず、接続孔１５
の内部を含む第２の層間絶縁膜１４上に、スパッタ法に
よって上記のチタン層（図示せず）を成膜する。この時
の成膜条件は、例えば、スパッタリングガスにアルゴン
ガスを用いる。そして、アルゴンガスの流量を１００ｓ
ｃｃｍ、成膜雰囲気の圧力を０．４Ｐａ、スパッタリン
グ出力を４ｋＷ、及び成膜温度を１５０℃に設定する。The orientation improving film 16 and the titanium layer are as follows.
For example, it is formed as follows. First, the connection hole 15
The above titanium layer (not shown) is formed on the second interlayer insulating film 14 including the inside by a sputtering method. As for the film forming conditions at this time, for example, an argon gas is used as a sputtering gas. Then, the flow rate of the argon gas is set to 100 seconds.
ccm, the pressure of the film forming atmosphere is set to 0.4 Pa, the sputtering output is set to 4 kW, and the film forming temperature is set to 150 ° C.

【００２４】次に、上記チタン層の上面に、スパッタ法
によって窒化チタンからなる配向性改善膜１６を形成す
る。この時の形成条件は、例えば、スパッタリングガス
にアルゴンガスと窒素ガスとを用いる。そして、アルゴ
ンガスの流量を３０ｓｃｃｍ、窒素ガスの流量を７０ｓ
ｃｃｍ、成膜雰囲気の圧力を０．４Ｐａ、スパッタリン
グ出力を５ｋＷ、及び成膜温度を１５０℃に設定する。Next, an orientation improving film 16 made of titanium nitride is formed on the upper surface of the titanium layer by a sputtering method. The formation conditions at this time are, for example, argon gas and nitrogen gas used as the sputtering gas. Then, the flow rate of the argon gas is 30 sccm, and the flow rate of the nitrogen gas is 70 s.
ccm, the pressure of the film formation atmosphere is set to 0.4 Pa, the sputtering output is set to 5 kW, and the film formation temperature is set to 150 ° C.

【００２５】その後、上記配向性改善膜１６の上面に、
上記と同様のチタン層（図示せず）を上記と同様の成膜
条件にて成膜する。Then, on the upper surface of the orientation improving film 16,
A titanium layer (not shown) similar to the above is formed under the same film forming conditions as described above.

【００２６】そして、図２（３）に示すように、上面に
チタン層を成膜した配向性改善膜１６の上面に、高温ス
パッタ法によって上層導電層１７を成膜する。成膜条件
は、例えば、スパッタリングガスにアルゴンガスを用い
る。そして、アルゴンガスの流量を１００ｓｃｃｍ、成
膜雰囲気の圧力を０．４Ｐａ、スパッタリング出力を１
０ｋＷ、及び成膜温度を５００℃に設定する。Then, as shown in FIG. 2C, an upper conductive layer 17 is formed on the upper surface of the orientation improving film 16 having a titanium layer formed thereon by a high-temperature sputtering method. As a film forming condition, for example, an argon gas is used as a sputtering gas. Then, the flow rate of the argon gas was 100 sccm, the pressure of the film formation atmosphere was 0.4 Pa, and the sputtering output was 1
0 kW and the film forming temperature are set to 500 ° C.

【００２７】その後、エッチングによって配向性改善膜
１６とこの上層導電層１７とのパターニングを行い、パ
ッド部１を形成する。After that, the orientation improving film 16 and the upper conductive layer 17 are patterned by etching to form the pad portion 1.

【００２８】上記のようにしてパッド部１を形成した
後、例えば、図３に示すように、パッド部１を覆う状態
に、第２の層間絶縁膜１４の上面に上層絶縁膜１８を成
膜する。そして、この上層絶縁膜１８にパッド部１の表
面に達する接続孔１９を形成する。After the pad 1 is formed as described above, for example, as shown in FIG. 3, an upper insulating film 18 is formed on the upper surface of the second interlayer insulating film 14 so as to cover the pad 1. I do. Then, a connection hole 19 reaching the surface of the pad portion 1 is formed in the upper insulating film 18.

【００２９】上記パッド部の形成方法では、下層導電層
の上面に窒化系チタンからなる配向性改善膜を形成する
ことによって、下層導電層の配向性が分断されると共に
上層配線層の下地の配向性が改善される。そして、高温
スパッタ法によって成膜される上層導電層は、配向性改
善膜の配向性を引き継いで成膜されるため、形成される
パッド部の表面は配向性が改善されて表面粗れが防止さ
れる。In the method of forming the pad portion, the orientation of the lower conductive layer is divided and the orientation of the base of the upper wiring layer is formed by forming the orientation improving film made of titanium nitride on the upper surface of the lower conductive layer. Is improved. Since the upper conductive layer formed by the high-temperature sputtering method is formed by inheriting the orientation of the orientation improving film, the surface of the formed pad portion is improved in orientation and surface roughness is prevented. Is done.

【００３０】上記実施例においては、上層導電層と下層
導電層との２層の積層構造でパッド部を形成する場合を
例にとって説明した。しかし本発明は、上記実施例に引
き続いて３層以上の導電層を高温スパッタ法によって成
膜するような積層構造のパッド部を形成する場合にも適
用することが可能である。In the above embodiment, the case where the pad portion is formed with a two-layered structure of the upper conductive layer and the lower conductive layer has been described as an example. However, the present invention can also be applied to the case of forming a pad portion having a laminated structure in which three or more conductive layers are formed by a high-temperature sputtering method following the above embodiment.

【００３１】さらに上記実施例では、第２の層間絶縁膜
に接続孔を形成した後に、配向性改善膜を形成する方法
を説明した。しかし本発明は、上記の手順に限らず、下
層導電層の上面に配向性改善膜を形成した後に、第２の
層間絶縁膜を成膜する手順でも良い。Further, in the above embodiment, the method of forming the orientation improving film after forming the connection hole in the second interlayer insulating film has been described. However, the present invention is not limited to the above procedure, but may be a procedure of forming an orientation improving film on the upper surface of the lower conductive layer and then forming a second interlayer insulating film.

【００３２】[0032]

【発明の効果】以上説明したように、本発明のパッド部
の構造およびその製造方法によれば、窒化系チタン層を
含む配向性改善膜によって下層導電層の配向性を分断し
て、この配向性改善膜上に高温スパッタ法によって成膜
される上層導電膜の表面粗れを防止する場合に、窒化チ
タン層の上層のチタン層によって上層導電層成膜時のヌ
レ性を改善し、また窒化チタン層の下層のチタン層によ
って下層導電層との密着性を改善することで、上層導電
膜の表面粗れを防止する効果をさらに高めることが可能
になる。したがって、パッド部のアライメントの精度を
向上させることが可能になり、ワイヤボンディングの位
置ずれを防止することができ、半導体装置の歩留まりと
信頼性の向上を図ることができる。As described above, according to the structure of the pad portion and the method of manufacturing the same of the present invention, the orientation of the lower conductive layer is divided by the orientation improving film containing the nitride-based titanium layer. In order to prevent the surface roughness of the upper conductive film formed by the high-temperature sputtering method on the property improving film, the wetting property at the time of forming the upper conductive layer is improved by the titanium layer on the titanium nitride layer, and By improving the adhesion to the lower conductive layer by the titanium layer below the titanium layer, the effect of preventing the surface roughness of the upper conductive film can be further enhanced. Therefore, it is possible to improve the accuracy of the alignment of the pad portion, to prevent the displacement of the wire bonding, and to improve the yield and reliability of the semiconductor device.

【図面の簡単な説明】[Brief description of the drawings]

【図１】実施例のパッド部の断面模式図である。FIG. 1 is a schematic cross-sectional view of a pad section of an embodiment.

【図２】実施例を説明する断面模式図である。FIG. 2 is a schematic sectional view illustrating an example.

【図３】実施例を説明する断面模式図である。FIG. 3 is a schematic sectional view illustrating an example.

【図４】従来例を説明する断面模式図である。FIG. 4 is a schematic sectional view illustrating a conventional example.

【符号の説明】[Explanation of symbols]

１ パッド部 １１ 基板 １３ 下層導電層 １６ 配向性改善膜 １７ 上層導電層 DESCRIPTION OF SYMBOLS 1 Pad part 11 Substrate 13 Lower conductive layer 16 Orientation improvement film 17 Upper conductive layer

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平２−153544（ＪＰ，Ａ) 特開 平５−3254（ＪＰ，Ａ) 特開 平２−35753（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-153544 (JP, A) JP-A-5-3254 (JP, A) JP-A-2-35753 (JP, A) (58) Field (Int.Cl. 7 , DB name) H01L 21/60

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 基板上に成膜されたアルミニウム系金属
からなる下層導電層と、当該下層導電層上に高温スパッ
タ法によって成膜されたアルミニウム系金属からなる上
層導電層とで構成されたパッド部において、 前記上層導電層は、チタン層、窒化系チタン層およびチ
タン層を下層から順次積層してなる配向性改善膜を介し
て前記下層導電層上に積層されていることを特徴とする
パッド部。1. A pad comprising: a lower conductive layer made of an aluminum-based metal formed on a substrate; and an upper conductive layer made of an aluminum-based metal formed on the lower conductive layer by a high-temperature sputtering method. In the portion, the upper conductive layer includes a titanium layer, a nitrided titanium layer, and a titanium layer.
A pad portion which is laminated on the lower conductive layer via an orientation improving film formed by laminating a tan layer sequentially from a lower layer. 【請求項２】 請求項１記載のパッド部の形成方法であ
って、 基板の上面に下層導電層を成膜する第１の工程と、 前記下層導電層上に、チタン層、窒化系チタン層および
チタン層を下層から順次積層して配向性改善膜を形成す
る第２の工程と、 前記配向性改善膜上に高温スパッタ法によって上層導電
層を成膜する第３の工程とを行うことを特徴とするパッ
ド部の形成方法。2. The method for forming a pad portion according to claim 1, wherein: a first step of forming a lower conductive layer on an upper surface of the substrate; and a titanium layer and a titanium nitride layer on the lower conductive layer. and
A second step of forming an orientation improving film by sequentially laminating a titanium layer from a lower layer, and a third step of forming an upper conductive layer on the orientation improving film by a high-temperature sputtering method. A method of forming a pad portion.
JP24387293A 1993-09-03 1993-09-03 Pad section and method of forming the same Expired - Fee Related JP3271215B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24387293A JP3271215B2 (en) 1993-09-03 1993-09-03 Pad section and method of forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24387293A JP3271215B2 (en) 1993-09-03 1993-09-03 Pad section and method of forming the same

Publications (2)

Publication Number Publication Date
JPH0774204A JPH0774204A (en) 1995-03-17
JP3271215B2 true JP3271215B2 (en) 2002-04-02

Family

ID=17110239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24387293A Expired - Fee Related JP3271215B2 (en) 1993-09-03 1993-09-03 Pad section and method of forming the same

Country Status (1)

Country Link
JP (1) JP3271215B2 (en)

Also Published As

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JPH0774204A (en) 1995-03-17

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