JP3270865B2 - Current switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current switching circuit for switching a current supply destination between a plurality of circuits, and more particularly to a current switching circuit applied to a bipolar digital integrated circuit such as a flip-flop. .

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an example of a conventional current switching circuit. In FIG. 5, 1 is a first circuit, 2 is a second circuit, 3 is a third circuit, V _CC is a power supply voltage, and _{Tr 1} to
T _r4 indicates an npn transistor, I ₀ is a constant current source, respectively.

[0003] current switching circuit, together with the emitters of the transistors T _r1 and T _r2 is a first differential pair of transistors are connected is configured, the transistors T _r3 and T
The emitters of _r4 are connected to each other to form a second transistor differential pair, the midpoint of connection between the emitters of the first transistor differential pair is connected to the collector of the transistor _Tr3 , and the second transistor differential pair is connected. connection point between the emitters of the pair is configured by connecting the constant current source I _0.

[0004] The collector of the transistor T _r1 of the first differential pair of transistors is connected to the first circuit 1, the collector of the transistor T _r2 is connected to the second circuit 2,
The collector of the transistor T _r4 of the second differential pair of transistors is connected to the third circuit 3, by inputting a switching signal sw ₁ is complementary signals to the bases of the transistors T _r1 and T _r2, the switching signal sw ₂ was inputted to the base of the transistor T _r3 and T _r4, depending on the input level to the bases of these switching signals sw ₁ and sw _2, the supply destination of the current I by the steady current source I ₀ is first to 3 is switched to one of the circuits 1 to 3.

FIG. 6 shows a switching signal sw for the circuit of FIG.
_1, the input level of the sw ₂ is a diagram illustrating the like. As shown in FIG. 6, the switching signal sw ₁ takes a binary high level sw _IH and a low level sw _1L. Similarly, the switching signal sw ₂ takes a binary high level sw _2H and low level sw _2L, these four levels satisfies the following conditions. sw _1H > sw _1L > sw _2H > sw _2L

In such a configuration, for example,
Jista T_r4Switching signal sw at the base of _TwoIs high level sw
_2HAnd the transistor T_r3Switching signal s at the base of
w_TwoIs low level sw_2LWhen input with, the transistor
T_r4Is turned on. In this case, the current I is
3 so that the third circuit 3 is activated.
You.

On the other hand, the transistor T_r3Base of
Switching signal sw_TwoIs high level sw _2HAnd the tiger
Transistor T_r4Switching signal sw at the base of_TwoIs low level s
w_2L, The transistor T_r3Is turned on
You. At this time, the transistor T_r1Switching signal s at the base of
w₁Is high level sw_1HAnd the transistor T_r2
Switching signal sw at the base of₁Is low level sw_1LTyped in
The transistor T_r1Is turned on. This place
The current I is supplied to the first circuit 1 so that the first
Circuit 1 is activated.

On the other hand, when the transistor T _r3 is on, the switching signal sw ₁ is input at a high level sw _IH to the base of the transistor T _r2, switching signal sw ₁ to the base of the transistor T _r1 is at low level sw _1L When input, the transistor _Tr2 is turned on. In this case, the current I is supplied to the second circuit 2, so that the second circuit 2 is activated.

FIG. 7 is a circuit diagram showing an example in which a T-type flip-flop with a data setting function as shown in FIG. 8 is configured as a bipolar digital integrated circuit by applying the current switching circuit of FIG. This circuit is a general circuit used when configuring a programming counter. The circuit of FIG. 5 has a two-stage configuration of a stage (master) and b stage (slave). Will be described.

[0010]

According to the present invention, there is provided a current switching circuit for switching a current supply destination among a first circuit, a second circuit, and a third circuit, comprising: The first and second transistors have their emitters connected to a current source, and the emitter has an emitter connected to the emitter of the first and second transistors. And a collector of the first transistor is connected to a first circuit, a collector of the second transistor is connected to a second circuit, and a collector of the third transistor is connected to a third transistor. And the first and second circuits
Of at least one of the transistors
Emitter area and emitter area of the third transistor
Was set to 1: n (where n> 1) .

The first circuits 1a, 1a,
1b is, npn-type transistors Q _1a having their emitters connected together, Q _2a and Q _1b, consists differential pair of Q _2b,
Each connection point of these emitters of the transistors T _r1a, is connected to the collector of T _r1b. Also,
The base of the a-stage transistor Q _1a is connected to the collector of the b-stage transistor Q _2b , and the a-stage transistor Q _2a
Is connected to the collector of the transistor _{Q1b in} the b-stage.

In the second circuits 2a and 2b, the emitters are connected to each other, and the collectors are resistors R _1a , R _2a and R _1b ,
A differential pair of npn transistors Q _3a , Q _4a and Q _3b , Q _4b connected to the power supply voltage V _cc via R _2b and their collectors and bases are connected to each other. Is connected to the transistor _Tr2a ,
Each is connected to the collector of _Tr2b .

In the third circuits 3a and 3b, the emitters are
Connected npn transistor Q _5a, Q_6aand
Q_5b, Q_6bOf these emitters
The middle point of the connection is the transistor T_r4a, T_r4bCollector
Connected to each other. A-stage transistor
Q_5aAre the first and second circuits 1a, 2a of the a stage.
transistor Q of a_1a, Q_3aConnected to the collector
And the transistor Q of the first circuit 1b of the b-stage_1b
Connected to the base. In addition, Transis
TA Q_6aIs a first stage and a second circuit 1a,
2a transistor Q_2a, Q_4aConnected to the collector
And the transistor Q of the b-stage first circuit 1b
_2bConnected to the base. On the other hand, the b-stage transistor
TA Q_5bIs also a b-stage first and second circuit
1b, 2b transistor Q_1b, Q_3bConnect to collector
And the transistor Q _6bIs also the first stage of b stage
And the transistors Q of the second circuits 1b and 2b _2b, Q_4b
Connected to the collector.

In such a configuration, the signal D is supplied to the stage a.
And transistors of the third circuits 3a and 3b in the b-th stage
Q_5a, Q_5bAnd the level complementary to signal D
Signal XD which takes_6a, Q_6bEnter the base
Is forced. Further, the clock signal CK is the first switching signal s
w₁A-stage transistor T _r2aBase and b
Stage transistor T_r1bIs entered into the base of
, A signal XCK having a complementary level to the clock signal CK
Is the first switching signal sw₁A-stage transistor T
_r1aBase and b-stage transistor T_r2bBase of
Is input to Further, the set signal S is the second switching signal
sw_TwoA-stage transistor T_{r4 a}Base and
b-stage transistor T_r4bIs entered into the base of
, A set signal X having a level complementary to the clock signal S
S is the second switching signal sw_TwoA-stage transistor T
_r3aBase and b-stage transistor T_r3bBase of
Is input to Then, the first to third circuits 1b to
3b constituting each transistor Q_1b~ Q_6bThe collector
Output signals Q and XQ of the flip-flop
You.

For example, a set as a second switching signal
When the signal S is at a high level, the transistors T in the a and b stages
_r4a, T_r4bIf input to the base of
I_a, I _bIs supplied to the third circuits 3a and 3b.
3a and 3b are activated. This allows the input signal
D and XD are output from this circuit as they are.

On the other hand, when the set signal S is at a low level
With transistor T_r4a, T_r4bEntered in the base of
When the set signal XS, which takes a complementary level to
Transistor T_r3a, T_r3bEntered at the base of
In the state, the clock signals CK, X as the first switching signal
When CK is high level or low level, the transistor T
_r1a, T_r2aAnd T_r1b, T_r2bEntered in the base of
Then, the current I_a, I_bIs the first circuit 1a, 1b or
2 circuits 2a and 2b, and the circuits 1a and 1b or
2a and 2b are activated. In this case, the clock signal
Output signals Q and XQ according to the input levels of signals CK and XCK.
Functions as a T-type flip-flop in which the level of
You.

[0017]

[SUMMARY OF THE INVENTION Incidentally, in the conventional circuit described above, the transistor T _r1, T _r2 of the first differential pair of transistors and the transistor T _r3 of the second differential pair of transistors is connected in cascade _Therefore , it is affected by the forward voltage _Vf of these transistors Tr1, _Tr2 and _Tr3 . When the circuit is actually, as shown in FIG. 7, a constant current source I _0a, I _0b transistor Q _Ia,
Q _Ib is used, and first to third circuits 1 a to 3
a, 1b~3b also transistor _{Q 1a ~Q 6a, Q 1b ~Q} 6b
, The power supply voltage V _CC is affected by the forward voltage V _f of these transistors. In particular, in order to operate the first circuit 1 and the second circuit 2, the power supply voltage V _CC is set to a value larger than 4 V _f. However, there is a problem that a usable voltage range is narrow.

[0018] Here, when the V _f of the transistor to be 0.7 V, in order to satisfactorily operate the circuit of FIG. 7, the value of the supply voltage V _CC must satisfy the following conditions. V _CC > 2.8 V (= 0.7 × 4) This cannot meet the demand for a low power supply voltage of around 2.7 V, which has been particularly increasing in recent years.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a current switching circuit that can be used even at a low power supply voltage.

[0020]

According to the present invention, there is provided a current switching circuit for switching a current supply destination among a first circuit, a second circuit, and a third circuit, comprising: The first and second transistors have their emitters connected to a current source, and the emitter has an emitter connected to the emitter of the first and second transistors. And a collector of the first transistor is connected to a first circuit, a collector of the second transistor is connected to a second circuit, and a collector of the third transistor is connected to a third transistor. Connected to the circuit.

In the present invention, the bases of the first and second transistors are respectively connected to the input lines of the first switching signal which takes a high level and a low level complementarily, and the base of the third transistor is high. The second switching signal is connected to an input line of a second switching signal that takes two values, a level and a low level, and the high level value of the second switching signal is set to a value equal to or higher than the high level of the first switching signal. The low level value of the second switching signal is set to a value lower than the high level of the first switching signal.

[0022]

According to the present invention, the first, second and third circuits have two transistors each having an emitter connected to each other and a collector connected to a power supply voltage. Are connected to the collectors of the first, second and third transistors, respectively. In one of the first circuit and the second circuit, the collector of one transistor and the other transistor Are connected to each other.

[0024]

According to the present invention, a switching signal is input to the bases of the first to third transistors, and the current supply destinations of the current source are changed according to the input levels of the switching signals.
Can be arbitrarily switched between the circuits. In this case, since the first to third transistors are connected in parallel, even if the first to third circuits and the current source are constituted by transistors, the value of the power supply voltage is a value larger than 3 _Vf . If there is, each circuit operates.

According to the present invention, the first switching signal which takes the high level and the low level complementarily is input to the bases of the first and second transistors, and the base of the third transistor is input to the base of the third transistor. A second switching signal having two values of a high level and a low level is input.

According to the present invention, the ratio of the emitter area of at least one of the first and second transistors to the emitter area of the third transistor is set to 1: n (n> 1). Therefore, for example, the first switching signal is input at a high level to the base of the first transistor whose emitter area is set small,
When the second switching signal is input to the base of the third transistor at a high level, only {I / (1 + n)} of the current I from the current source I ₀ flows into the first circuit, and {(n ·
I) / (1 + n)} flows into the third circuit. Therefore, here, the value of n is a somewhat large value,
For example, if “4”, the supply destination of the current I is switched from the first or second circuit to the third circuit when the second switching signal is at a high level. As a result, the third circuit is activated.

According to the present invention, for example, the base of a transistor differential pair forming the first circuit or the second circuit;
In addition, by inputting a signal of a predetermined level from the outside to the base of the transistor differential pair constituting the third circuit, the transistor functions as a D-type flip-flop.

[0028]

FIG. 1 is a block diagram showing an embodiment of a current switching circuit according to the present invention. The same components as those in FIG. 5 showing a conventional example are denoted by the same reference numerals. That is, the first circuit 1, the second circuit 2, the third circuit 3, V _CC is the power supply voltage, T _r1 is a first transistor, T _r2 is a second transistor, T _r5 third Transistor, I ₀ is a constant current source, S
W ₁ represents a first switching signal, SW ₂ shows a second switching signal, respectively.

The emitter and the second of the first transistor T _r1
And the emitter of the transistor _Tr2 is connected to form a transistor differential pair. The first transistor T _r1
Is connected to the current input line of the first circuit 1, and the collector of the second transistor _Tr2 is connected to the second circuit 2
Connected to the current input line. The emitter of the third transistor T _r5 is connected to the connection point between the emitters of the transistors T _r1 and T _r2, the collector is connected to the third circuit 3 of the current input line. The constant current source I ₀ is connected to the connection point between the emitters of the transistors T _r1 and T _r2.

Furthermore, the ratio of the emitter area of the first transistor T _r1 and the emitter area of the second transistor T _r2 is set to 1: 1, the emitter area of the third transistor T _r5, these first n-to-1 with respect to the emitter area of the first and second transistor T _r1, T _r2 (However, n>
1) is set.

The circuit includes a complementary first switching signal SW ₁
The first and second transistors of the differential transistor pair T _r1, T base is the input of _r2, the circuit 1 or the second supply destination of the first current I from the constant current source I ₀ in accordance with the input level switch to the circuit 2, the second switch signal SW ₂ is input to the base of the third transistor T _r5, switches the third supply state and a non-supply state to the circuit 3 of the current I in accordance with the input level It is configured as follows.

Next, the input levels of the first switching signal SW ₁ and the second switching signal SW ₂ will be considered.

In order for the first to third circuits 1 to 3 to operate
Indicates that the power supply voltage V_CCAnd the first to third
Between the input sides A, B, and C of the circuits 1 to 3 of FIG.
It is necessary to configure so that a difference appears. Therefore, the first
And the second switching signal SW₁, SW_TwoHigh-level SW
_1H, SW _2HIs preferably as low as possible. However,
Current source I₀Must be within the range in which it can operate normally. No.
First and second switching signals SW₁, SW_TwoLow level S
W_1L, SW_2LIs a high level SW_1H, SW_2HAgainst
The only requirement is that the transistor be as low as possible.
There are no restrictions.

In this embodiment, for example, in consideration of the case where the first to third circuits 1 to 3 require the same level of the power supply voltage V _{CC to the} potential difference between the points A, B and C, FIG. As shown in the figure, the high level SW _1H of the _first switching signal SW ₁ and the high level SW _{2H of the second} switching signal SW ₂ are set to the same level (voltage, for example, 2 V), and the low level voltage of 2 of the switching signal SW ₂ at the low level SW _2L is a low value relative to the first switching signal SW ₁ of the low-level SW _1L voltage (e.g., 1.8V) (e.g. 1.6
V). Thereby, the supply destination of the current I is set to the first
The first to third circuits 1 to 3 can be arbitrarily switched between the first to third circuits 1 to 3, and can be satisfactorily operated.

Next, the operation of the above configuration will be described. For example, when the second switching signal SW ₂ is input at a low level SW _2L to the base of the third transistor T _r5, first
Switching signal SW ₁ is input at the base to a high level SW _IH of the first transistor T _r1, the second transistor T _r2
Is input to the base at the low level SW _1L, the first transistor T _r1 is turned on. In this case, the current I is supplied to the first circuit 1, so that the first circuit 1 is activated. On the other hand, the first switching signal SW ₁ is input at the base to the low level SW _1L of the first transistor T _r1, based on the high level SW of the second transistor T _r2
When input at _1H , the second transistor _Tr2 is turned on. In this case, the current I is supplied to the second circuit 2,
As a result, the second circuit 2 is activated.

[0036] In contrast, when the base of the third transistor T _r5 second switching signal SW ₂ is input at a high level SW _2H, the first switching signal SW ₁ is in the first transistor T _r1 High level SW _1H is input to the base.
It is input to the base of the transistor T _r2 at low level SW _1L, and bases of the third transistor T _r5 of the first transistor T _r1 have the same potential. At this time,
Since the ratio of the emitter area of the emitter area of the first transistor T _r1 third transistor T _r5 is set to 1: n, of the current I from the constant current source I ₀ {I / (1
+ N)} to the first circuit 1 and {(n · I) / (1)
+ N) flows through the third circuit 3.

Similarly, when the second switching signal SW ₂ is input at the high level SW _2H to the base of the third transistor Tr 5, the first switching signal SW ₁ is supplied to the first transistor T _r5.
r1 base entered at low level SW _1L of, when input in the second transistor T _r2 base high SW _IH of the bases of the third transistor T _r5 of the second transistor T _r2 is It has the same potential. At this time, since the ratio of the emitter area of the emitter area of the second transistor T _r2 and the third transistor T _r5 is set to 1: n, the constant current source I ₀ of the current I by {I / ( 1+
n) flows into the second circuit 2 and｝ (n · I) / (1+
n)｝ flows into the third circuit 3.

[0038] Here, the value of n is a large value to some extent, if, for example, "4", the second switching signal SW ₂ is at the high level SW _2H, current I supply destination of the first or second The circuits 1 and 2 can be satisfactorily switched to the third circuit 3.
As a result, the third circuit 3 is activated.

As described above, according to the present embodiment,
First and second transistor T _r1, a connection midpoint between the emitters of T _r2 comprised transistor differential pair from the third
With parallel connection by connecting the emitter of the transistor T _r5, first and second transistor T _r1, T 1 versus the ratio of the emitter area and the emitter area of the third transistor T _r5 of _r2 n (n> Since it is set to 1), the transistors constituting the switching circuit are not cascaded. Therefore, the constant current source I ₀ is connected to the first
When supplying the current I to the third circuits 1 to 3, the number of transistors to be passed can be minimized, so that the influence of the transistor _Vf can be minimized, and a low power supply voltage such as 2.7V can be used. It can also be applied to working circuits.

The input levels of the first switching signal SW ₁ and the second switching signal ₂ are, as described above, the high level SW _1H of the _first switching signal SW ₁ and the second switching signal SW ₂
Is set to the same level as the high level SW _{2H of} the second
Voltage of the switch signal SW ₂ at the low level SW _2L is required to be set to a lower value with respect to the first switching signal SW ₁ of the low-level voltage SW _1L not always, the second switching signal SW ₂ Of the high level SW _2H of the first switching signal SW
₁ is set to a value equal to or higher than the high level SW _{1H, and} the value of the low level SW _2L of the second switching signal SW ₂ is set to the first switching signal S
If it is set to a value lower than the high level SW _{1H of} W _1, a good switching operation can be realized.

FIG. 3 shows an example in which a so-called T-type flip-flop having a data setting function as shown in FIG. 8 is configured as a bipolar digital integrated circuit by applying the current switching circuit according to the present invention shown in FIG. FIG.

This circuit is a general circuit used for forming a programming counter.
It has a two-stage configuration of a stage (master) and a stage b (slave), and the same components as those in FIG. 7 showing the conventional example are denoted by the same reference numerals. That, 1a, 1b the first circuit, 2a, 2b and the second circuit, 3a, 3b the third circuit, V _CC is the power supply _{voltage, Q 1a ~Q 6a, Q 1b} ~Q 6b is first to
Npn transistors constituting the third circuits _{1a to 3a} and _{1b to 3b} , R _1a , R _2a , R _1b and R _2b are resistance elements, T
_r1a, T _r1b the first transistor, T _r2a, T _r2b the second transistor, T _{r5 a,} T _{r5 b} the third transistor, Q _Ia, Q _Ib is an npn transistor current source, R
_Ia and R _Ib indicate current source resistance elements, respectively.

The collector of the constant current source I _0a transistor Q _Ia of a stage is connected to the connection point between the emitter of the emitter and the second transistor T _r2a of the first transistor T _r1a of a stage. Similarly, the collector of the transistor Q _Ib for the constant current source I _0b at the b stage is the first transistor T at the b stage.
It is connected to the connection point between the emitter of _{r1b and} the emitter of the second transistor _Tr2b .

[0044] Further, the collector of the first transistor T _r1a in a stage is connected to the connection point between the emitters of the transistors Q _1a, Q _2a of the first circuits 1a, second
The collector of the transistor T _r2a the transistor Q _3a of the second circuit 2a, is connected to the connection point between the emitters of Q _4a, the collector of the third transistor T _{r5 a} the transistor Q _5a of the third circuit 3a, It is connected to the connection point between the emitters of Q _6a. Similarly, in the b stage the collector of the first transistor T _r1b is connected to the connection midpoint between the emitters of the transistors Q _1b, Q _2b of the first circuit 1b, the collector of the second transistor T _r2b is second transistor Q _3b of the circuit 2b, are connected to the connection point between the emitters of Q _4b, transistor Q _5b of the collector of the third transistor T _{r5 b} is a third circuit 3b, a connection midpoint between the emitters of Q _6b It is connected.

In such a configuration, the signal D is input to the bases of the transistors Q _5a and Q _5b of the third circuits 3a and 3b in the a-stage and the b-stage, and the signal XD having a complementary level to the signal D is provided. The signal is input to the bases of the transistors Q _6a and Q _6b . Further, the clock signal CK is the first switching signal S
W is input to the base of the first transistor T _r1b base and b stage of the second transistor T _r2a of a stage as _1, signal XCK taking complementary levels to the clock signal CK is first switching signal SW It is input to the base of the second transistor T _r2b base and b stage of the first transistor T _r1a of a stage as _one. Further, the set signal S is input as _{a second} switching signal SW2 to the bases of the third transistors _{Tr5a at} both stages. Then, each transistor Q forming the first to third circuits 1b to 3b of the b stage
_1b to Q _6b output signal Q from the collector of the flip-flop, XQ is output.

For example, a set as a second switching signal
When the signal S is at a high level,
Star T_r5a, T_r5bIf input to the base of
Style I _a, I_bIs supplied to the third circuits 3a and 3b,
The roads 3a and 3b are activated. This allows the input signal
D and XD are output from this circuit as they are.

[0047] In contrast, the set signal S is input at a low level third transistor T _R5a, to the base of the T _{r5 b,} in this state, the clock signal CK as a first switching signal, XCK is high or low level first and second transistor T _r1a, T _r2a and T _r1b, T
is input to the base of _r2b, current I _a, I _b is the first circuit 1a, 1b or the second circuit 2a, is supplied to 2b, circuits 1a, 1b or 2a, 2b is actuated state. In this case, it functions as a T-type flip-flop in which the levels of the output signals Q and XQ are inverted according to the input levels of the clock signals CK and XCK.

FIG. 4 is a circuit diagram showing an example of a driving circuit for supplying each signal to the circuit of FIG. In FIG.
₁₁ to Q ₁₉ denotes an npn transistor, R ₁₁ to R ₁₅ is the resistance element, respectively.

[0049] the emitters of the transistors Q ₁₁ and Q ₁₂ are connected, the collector of the transistor Q ₁₇ to connect the midpoint of emitters each other are connected, the emitter of the transistor Q ₁₇ is connected to the ground GND via a resistor element R ₁₃ is are connected to the power supply voltage V _CC respective collectors of the transistors Q ₁₁ and Q ₁₂ through a resistor R _11, R _12. Connection point between the collector of the transistor Q ₁₁ and the resistor R ₁₁ together with is connected to the base of the transistor Q _13, is connected to the first output terminal of the signal XOUT _1,
Connection point between the collector and the resistance element R ₁₂ of the transistor Q _12, together with being connected to the base of the transistor Q _14, and is connected to the first output signal OUT _1.

The collector of the transistor Q ₁₃ is the power supply voltage V
It is connected to the _CC, an emitter connected to the collector and base of the output end and transistor Q ₁₅ of the second signal XOUT _2. The collector of the transistor Q ₁₄ is connected to the power source voltage V _CC, an emitter connected to the collector and base of the second signal OUT ₂ output terminals and the transistors Q _16. Therefore, the second signal OUT ₂ , XO
Level of UT ₂ has a correspondingly lower by the level of the forward voltage V _f of the first signal OUT _1, transistors than the level of the XOUT ₁ Q _14, Q _13.

The transistor emitter of Q ₁₅ is connected to the collector of the third signal XOUT _third output terminal and the transistor Q _18, the emitter resistance element of the transistor Q ₁₈ R
It is connected to the ground GND through _14. The emitter of the transistor Q ₁₆ is connected to the collector of the third output terminal and the transistor Q ₁₉ of the signal OUT _3, transistor Q
The emitter ₁₉ is connected to the ground GND via a resistor element R _15. The base of the transistor Q ₁₇ to Q ₁₉ is connected to a power source V _BB. Therefore, the third signal O
The level of UT ₃ , XOUT ₃ is equal to the level of the second signal OUT ₂ , XOUT
The level of OUT ₂ has a correspondingly lower by the level of the forward voltage V _f of the transistor Q _16, Q _15.

[0052] In this driving circuit, the driving input signal IN is input to the base of the transistor Q _11, the signal IN
Signal XIN taking complementary level is input to the base of the transistor Q ₁₂ and, together with the differential output by the transistor Q _11, Q ₁₂ are outputted first as the signal OUT ₁ and XOUT _1, transistors Q _13, Q ₁₄ Is entered at the base of The transistors Q ₁₃ and Q ₁₄ to which the differential outputs of the transistors Q ₁₁ and Q ₁₂ are input are turned on / off differentially, and their emitter outputs are output as the second signals OUT ₂ and XOUT ₂ . Transistor Q
₁₅ and Q ₁₆ are input to the collector and the base, respectively. Transistors Q ₁₅ and Q ₁₆ are so-called diode-connected, and are turned on / off according to the levels of _second signals OUT ₂ and XOUT ₂ , and their emitter outputs are output as _third signals OUT ₃ and XOUT _3. You.

The first to third stages a and b of the circuit of FIG.
Circuits 1a to 3a, each of the transistors Q _1a to Q _6a constituting the 1b to 3b, Q _1b high level of the base voltage of the to Q _6b are substantially example to operate with a low power supply voltage, such as 2.7V Set to V _CC . Therefore, FIG.
When the circuit of FIG. 3 is driven using the drive circuit of
First signal OUT ₁ of the circuit of Figure 4 is used as the signal D, the first signal XOUT ₁ is used as a signal XD taking complementary levels to the signal D. The first to third transistors _{T r1a, T r2a, T r5a} , T r1b, T r2b,
As the high level of the base voltage of _Tr5b , the second signals OUT ₂ and XOUT ₂ of the circuit of FIG. 4 are used. In particular,
First switching signal SW ₁ in which the signal CK, a second signal OUT ₂ is used as XCK, the second signal XOUT ₂ is used as a signal S which is a second switching signal SW _2,
(V _CC -V _f ) is set to a high level.
As a result, in the circuit of FIG. 3, since the number of connected transistors is the highest three stages in the supply line of the current and operable even (V _CC ≒ 3V _f). Specifically, assuming that V _f = 0.7 V, the power supply voltage V _CC
= 2.7V, a circuit operable satisfactorily can be realized.

[0054] On the contrary, in the case of the conventional circuit shown in FIG. 7, the transistor _{T r3a, T r4 a, T} r3b, T r4b
It is necessary to use the third signals OUT ₃ and XOUT ₃ of the drive circuit shown in FIG. 4 as the second switching signal to be input to the base of ( ₃ ), and (V _CC ≒ 4V _f ) is a practical limit.

Note that only the a stage of the circuit of FIG.
Transistor Q of the circuit 1a_1a, Q _2aExternal to the base of
By inputting a signal to a predetermined level from the
And as a D-type flip-flop with data setting function
Can work.

[0056]

As described above, according to the present invention,
A circuit which can operate sufficiently even under a low power supply voltage can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a current switching circuit according to the present invention.

FIG. 2 is a diagram showing an example of a setting level of a switching signal according to the present invention.

FIG. 3 is a circuit diagram showing an example in which the current switching circuit according to the present invention shown in FIG. 1 is applied and configured as a bipolar digital integrated circuit.

FIG. 4 is a circuit diagram showing an example of a driving circuit for supplying each signal to the circuit of FIG. 3;

FIG. 5 is a configuration diagram illustrating an example of a conventional current switching circuit.

FIG. 6 is a diagram illustrating an example of a setting level of a switching signal in a conventional circuit.

7 is a circuit diagram showing an example in which the conventional current switching circuit shown in FIG. 5 is applied and configured as a bipolar digital integrated circuit.

FIG. 8 is a diagram illustrating a configuration example of a T-type flip-flop.

[Explanation of symbols]

1, 1a, 1b ... first circuit 2, 2a, 2b ... second circuit 3, 3a, 3b ... third circuit _{T r1, T r1a, T r1b} ... first transistor T _r2, T _r2a, T _r2b ... second transistor _{T r5, T r5a, T r5b} ... third transistor _{I 0, I 0a, I 0b} ... constant current source SW ₁ ... first switching signal SW ₂ ... second switching signal Q _1a ~ _{Q 6a, Q 1b ~Q 6b,} Q Ia, Q Ib, Q 11 ~Q 19 ... n
pn-type transistors R _1a , R _2a , R _1b , R _2b , R _Ia , R _Ib , R _{11 to} R ₁₄ ...

Continuation of the front page (56) References JP-A-59-181804 (JP, A) JP-A-2-39620 (JP, A) JP-A-6-177771 (JP, A) JP-A-3-121726 (JP) , U) Hikaru 1-93817 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 17/00-17/70

Claims (3)

(57) [Claims] 1. A current supply destination is a first circuit and a second circuit.
And a current switching circuit for switching between the third circuit and the third circuit.
The emitters are connected, and these emitters are connected
First and second transistors whose points are connected to a current source
And the emitter is the emitter of the first and second transistors.
The third transistor connected to the connection midpoint between
The collector of the first transistor is connected to the first circuit
And a collector of the second transistor is connected to a second circuit.
And the collector of the third transistor is connected to the third
Connected to the circuitAnd At least one of the first and second transistors
The emitter area of the other transistor and the third transistor
The ratio of the emitter to the emitter area is 1: n (where n> 1)
Set A current switching circuit, characterized in that: 2. A base of each of the first and second transistors is connected to an input line of a first switching signal that takes a high level and a low level complementarily, and a base of the third transistor has a high level. The second switching signal is connected to an input line of a second switching signal having a low level, and the high level value of the second switching signal is set to a value equal to or higher than the high level of the first switching signal. 2. The current switching circuit according to claim 1, wherein a low level value of the switching signal is set to a value lower than a high level of the first switching signal. 3. The first, second and third circuits each have two transistors whose emitters are connected to each other and whose collectors are connected to a power supply voltage, and the connection between the emitters of the two transistors of each circuit. The midpoint is connected to the collectors of the first, second and third transistors, respectively. In one of the first circuit and the second circuit, the collector of one transistor and the base of the other transistor are provided. The two are connected to each other.
Or the current switching circuit according to 2.