JPH06268496A - Current switching circuit - Google Patents

Abstract

PURPOSE:To provide a current switching circuit usable even at a low power supply voltage. CONSTITUTION:This current switching circuit for switching the supply destination of a current I among a first circuit 1, a second circuit 2 and a third circuit 3 is provided with first and second transistors TR1 and TR2 for which emitters are mutually connected and the connection intermediate point of the mutual emitters is connected to a current source I0 and a third transistor TR5 for which the emitter is connected to the connection intermediate point of the emitters of the first and second transistors TR1 and TR2. The collector of the first transistor TR1 is connected to the first circuit 1, the collector of the second transistor TR2 is connected to the second circuit 2 and the collector of the third transistor TR5 is connected to the third circuit 3. Also, the ratio of the emitter area of the first and second transistors TR1 and TR2 and the emitter area of the third transistor TR5 is set at 1 to (n) {(n)>1}.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current switching circuit for switching a current supply destination among a plurality of circuits, and more particularly to a current switching circuit applied to a bipolar digital integrated circuit such as a flip-flop. .

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an example of a conventional current switching circuit. In FIG. 5, 1 is a first circuit, 2 is a second circuit, 3 is a third circuit, V _CC is a power supply voltage, and T _r1 ~
T _r4 is an npn type transistor, and I ₀ is a constant current source.

In the current switching circuit, the emitters of the transistors T _r1 and T _r2 are connected to each other to form a first transistor differential pair and the transistors T _r3 and T _r3.
The emitters of _r4 are connected to each other to form a second transistor differential pair, the middle point of connection between the emitters of the first transistor differential pair is connected to the collector of the transistor T _r3 , and the second transistor differential pair is connected. The midpoint of connection between the emitters of the active pair is connected to the constant current source I ₀ .

The collector of the transistor T _r1 of the first transistor differential pair is connected to the first circuit 1, and the collector of the transistor T _r2 is connected to the second circuit 2.
The collector of the transistor T _r4 of the second transistor differential pair is connected to the third circuit 3, and the switching signal sw ₁ which is a complementary signal is input to the bases of the transistors T _r1 and T _r2 to switch the switching signal sw. ₂ is input to the bases of the transistors T _r3 and T _r4 , and the constant I current source I ₀ supplies the current I to the first to the first destinations according to the input levels of the switching signals sw ₁ and sw _{2 to} the bases. It is switched to any one of the circuits 1 to 3 of No. 3.

FIG. 6 shows a switching signal sw for the circuit of FIG.
_1, the input level of the sw ₂ is a diagram illustrating the like. As shown in FIG. 6, the switching signal sw ₁ has two values, a high level sw _1H and a low level sw _1L . Similarly, the switching signal sw ₂ takes two values of high level sw _2H and low level sw _2L , and these four levels satisfy the following conditions. sw _1H ＞ sw _1L ＞ sw _2H ＞ sw _2L

In such a structure, for example,
Dista T_r4Switching signal sw on the base of ₂Is a high level sw
_2HIs input with the transistor T_r3Switching signal s on the base of
w₂Is low level sw_2LWhen input with
T_r4Turns on. In this case, the current I is the third circuit
3 as a result of which the third circuit 3 is activated.
It

On the other hand, the transistor T_r3Base of
Switching signal sw₂Is a high level sw _2HEntered in the tiger
Register T_r4Switching signal sw on the base of₂Is a low level s
w_2LWhen input at_r3Is turned on
It At this time, the transistor T_r1Switching signal s on the base of
w₁Is a high level sw_1HIs input with the transistor T_r2
Switching signal sw on the base of₁Is low level sw_1LEntered in
Then, the transistor T_r1Turns on. This place
Current I is supplied to the first circuit 1 so that
The circuit 1 of 1 is activated.

On the other hand, when the transistor T _r3 is on, the switching signal sw ₁ is input at a high level sw _IH to the base of the transistor T _r2, switching signal sw ₁ to the base of the transistor T _r1 is at low level sw _1L When input, the transistor T _r2 is turned on. In this case, the current I is supplied to the second circuit 2, so that the second circuit 2 is activated.

FIG. 7 is a circuit diagram showing an example in which the so-called T-type flip-flop with a data setting function as shown in FIG. 8 is configured as a bipolar digital integrated circuit by applying the current switching circuit of FIG. This circuit is a general one used when configuring a programming counter, and is a circuit in which the circuit of FIG. 5 has a two-stage structure of a stage (master) and b stage (slave). Explained.

Constant current source of a stage and b stage in this configuration
I_0a, I_0bEach has a power source V_BBConnected to
npn transistor Q_Ia, Q_IbAnd a transistor
Q_Ia, Q _IbConnected between the ground emitter and the ground
Element R_Ia, R_IbAnd transistor Q_IaThe
Transistor T with a stage a_r3aEmitter and Tran
Dista T_r4aConnect to the midpoint of the
Register Q_IbThe transistor T has a b-stage collector_r3bof
Emitter and transistor T_r4bMidpoint of connection with the emitter of
It is connected to the.

The first circuits 1a in the stages a and b,
1b is composed of a differential pair of npn transistors Q _1a , Q _2a and Q _1b , Q _2b whose emitters are connected to each other,
The midpoint of connection between these emitters is connected to the collectors of the transistors T _r1a and T _r1b , respectively. Also,
The base of the a-stage transistor Q _1a is connected to the collector of the b-stage transistor Q _2b , and the a-stage transistor Q _2a
And the collector of the b-stage transistor Q _1b are connected.

In the second circuits 2a and 2b, the emitters are connected to each other, and the collectors are resistive elements R _1a , R _2a and R _1b ,
It is composed of a differential pair of npn-type transistors Q _3a , Q _4a and Q _3b , Q _4b which are connected to the power supply voltage V _CC via R _2b and whose collectors and bases are connected to each other, and their emitters are connected to each other. The middle point of the connection is the transistor T _r2a ,
Each is connected to the collector of T _r2b .

In the third circuits 3a and 3b, the emitters are connected to each other.
Npn transistor Q connected _5a, Q_6aand
Q_5b, Q_6bConsists of a differential pair of
The middle point of connection of the master is the transistor T_r4a, T_r4bCollector of
Respectively connected to. Also, a-stage transistor
Q_5aIs a collector of the a-stage first and second circuits 1a, 2
a transistor Q_1a, Q_3aConnected to the collector of
And the transistor Q of the b-stage first circuit 1b_1b
Connected to the base of. In addition, a-stage Transis
Q_6aIs a collector of the a-stage first and second circuits 1a,
2a transistor Q_2a, Q_4aConnected to the collector of
And the transistor Q of the b-stage first circuit 1b
_2bConnected to the base of. On the other hand, the b-stage transistor
Q_5bIs also a b-stage first and second circuit
Transistor Q of 1b and 2b_1b, Q_3bConnect to the collector
And transistor Q _6bIs also the first b-stage collector
And the transistor Q of the second circuits 1b and 2b _2b, Q_4b
Connected to the collector.

In such a configuration, the signal D is in the a stage.
And transistors of the b-third third circuits 3a and 3b
Q_5a, Q_5bInput to the base of and complementary level to signal D
The signal XD taking on is the transistor Q_6a, Q_6bEnter the base of
I will be forced. In addition, the clock signal CK is the first switching signal s
w₁As a-stage transistor T _r2aBase and b
Stage transistor T_r1bWhen input to the base of
, A signal XCK having a level complementary to the clock signal CK
Is the first switching signal sw₁As a-stage transistor T
_r1aOf the base and the transistor T of the b stage_r2bBase of
Entered in. Furthermore, the set signal S is the second switching signal.
sw₂As a-stage transistor T_{r4 a}The base of and
b-stage transistor T_r4bWhen input to the base of
And a set signal X having a level complementary to the clock signal S
S is the second switching signal sw₂As a-stage transistor T
_r3aOf the base and the transistor T of the b stage_r3bBase of
Entered in. Then, the b-stage first to third circuits 1b to
Each transistor Q forming 3b_1b~ Q_6bIs it a collector
Output signals Q and XQ of this flip-flop
It

For example, a set as the second switching signal
When the signal S is at high level, the a-stage and b-stage transistors T
_r4a, T_r4bCurrent when input to the base of
I_a, I _bIs supplied to the third circuits 3a and 3b,
3a and 3b are activated. This allows the input signal
D and XD are directly output from this circuit.

On the other hand, the set signal S is low level.
And transistor T_r4a, T_r4bEntered in the base of
When the set signal XS, which takes a complementary level to this, is at a high level
Transistor T_r3a, T_r3bEntered in the base of this
The clock signals CK and X as the first switching signals in the state
Transistor T when CK is high level or low level
_r1a, T_r2aAnd T_r1b, T_r2bEntered in the base of
Then, the current I_a, I_bIs the first circuit 1a, 1b or
2 to the circuits 2a and 2b, and the circuits 1a and 1b or
2a and 2b are activated. In this case, the clock signal
Output signals Q and XQ according to the input levels of signals CK and XCK
Function as a T-type flip-flop that inverts the level of
It

[0017]

In the conventional circuit described above, the transistors T _r1 and T _r2 of the first transistor differential pair and the transistor T _{r3 of} the second transistor differential pair are connected in _{series. Therefore} , it is affected by the forward voltage V _f of the transistors T _r1 , T _r2 and the transistor T _r3 . When actually constructing the circuit, as shown in FIG. 7, the constant current sources I _0a and I _0b are connected to the transistors Q _Ia and
Q _Ib is used and the first to third circuits 1a to 3 are used.
a, 1b~3b also transistor _{Q 1a ~Q 6a, Q 1b ~Q} 6b
Therefore, in order to operate the first circuit 1 and the second circuit 2 particularly under the influence of the forward voltage V _f of these transistors, the power supply voltage V _CC is larger than 4 V _f. However, there is a problem that the usable voltage range is narrow.

Here, when the V _f of the transistor is 0.7 V, the value of the power supply voltage V _CC needs to satisfy the following conditions in order to operate the circuit of FIG. 7 satisfactorily. V _CC > 2.8 V (= 0.7 × 4) With this, it is not possible to meet the demand for a low power supply voltage of around 2.7 V, which has been particularly increasing in recent years.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a current switching circuit that can be used even at a low power supply voltage.

[0020]

To achieve the above object, according to the present invention, there is provided a current switching circuit for switching a current supply destination among a first circuit, a second circuit and a third circuit. First and second transistors connected to each other and having their emitter connection points connected to a current source; and emitters connected to emitter connection points of the first and second transistors. A third transistor, the collector of the first transistor is connected to the first circuit, the collector of the second transistor is connected to the second circuit, and the collector of the third transistor is the third circuit. Is connected to the circuit.

According to the present invention, the bases of the first and second transistors are respectively connected to the input lines of the first switching signal which complements the high level and the low level, and the bases of the third transistor are high. It is connected to an input line of a second switching signal that takes a binary value of a level and a low level, and the high level value of the second switching signal is set to a value equal to or higher than the high level of the first switching signal. The low level value of the second switching signal is set to a value lower than the high level of the first switching signal.

In the present invention, the ratio of the emitter area of at least one of the first and second transistors to the emitter area of the third transistor is set to 1: n.

In the present invention, the first, second and third circuits each have two transistors whose emitters are connected to each other and whose collectors are connected to the power supply voltage. The emitters of the two transistors of each circuit are connected to each other. Connection midpoints are respectively connected to the collectors of the first, second and third transistors, and in either one of the first circuit and the second circuit, the collector of one transistor and the other transistor are connected. The bases of are connected to each other.

[0024]

According to the present invention, switching signals are input to the bases of the first to third transistors, and the current supply destinations of the current sources are set to the first to third transistors according to the input levels of these switching signals.
Can be switched arbitrarily between the circuits. In this case, since the first to third transistors are connected in parallel, even if the first to third circuits and the current source are composed of transistors, the value of the power supply voltage is larger than 3V _f . If so, each circuit operates.

According to the present invention, the first switching signal for complementary high level and low level is input to the bases of the first and second transistors, and the bases of the third transistors are A second switching signal having two levels, a high level and a low level, is input.

Further, according to the present invention, the ratio of the emitter area of at least one of the first and second transistors to the emitter area of the third transistor is set to 1: n (n> 1). Therefore, for example, the first switching signal is input at a high level to the base of the first transistor whose emitter area is set small,
When the second switching signal is input at the high level to the base of the third transistor, {I / (1 + n)} of the current I generated by the current source I ₀ flows to the first circuit, and {(n ·
I) / (1 + n)} flows to the third circuit. Therefore, here, the value of n is rather large,
For example, if it is "4", the supply destination of the current I can be switched from the first or second circuit to the third circuit when the second switching signal is at the high level. As a result, the third circuit is activated.

According to the present invention, for example, the bases of the transistor differential pairs forming the first circuit or the second circuit,
In addition, by inputting a signal of a predetermined level from the outside to the bases of the transistor differential pair forming the third circuit, it functions as a D-type flip-flop.

[0028]

1 is a block diagram showing an embodiment of a current switching circuit according to the present invention, and the same components as those in FIG. 5 showing a conventional example are designated by the same reference numerals. That is, 1 is the first circuit, 2 is the second circuit, 3 is the third circuit, V _CC is the power supply voltage, T _r1 is the first transistor, T _r2 is the second transistor, and T _r5 is the third circuit. Transistor, I ₀ is a constant current source, S
W ₁ is the first switching signal, and SW ₂ is the second switching signal.

The emitter of the first transistor T _r1 and the second
And the emitter of the transistor _Tr2 is connected to form a transistor differential pair. First transistor T _r1
Is connected to the current input line of the first circuit 1 and the collector of the second transistor T _r2 is connected to the second circuit 2
Is connected to the current input line. The emitter of the third transistor T _r5 is connected to the midpoint of connection between the emitters of the transistors T _r1 and T _r2 , and the collector is connected to the current input line of the third circuit 3. A constant current source I ₀ is connected to the midpoint of connection between the emitters of the transistors T _r1 and T _r2 .

Further, the ratio of the emitter area of the first transistor T _{r1 to} the emitter area of the second transistor T _r2 is set to 1: 1 and the emitter area of the third transistor T _r5 is N to 1 with respect to the emitter areas of the first and second transistors T _r1 and T _r2 (where n>
It is set to 1).

This circuit has a complementary first switching signal SW ₁
To the bases of the first and second transistors T _r1 and T _r2 of the transistor differential pair, and the constant current source I ₀ supplies the current I to the first circuit 1 or the second circuit according to the input level. switch to the circuit 2, the second switch signal SW ₂ is input to the base of the third transistor T _r5, switches the third supply state and a non-supply state to the circuit 3 of the current I in accordance with the input level Is configured.

Next, the input levels of the first switching signal SW ₁ and the second switching signal SW ₂ will be considered.

In order for the first to third circuits 1 to 3 to operate
Current flows at the same time as the power supply voltage V_CCAnd first to third
Between the input sides A, B and C of the circuits 1 to 3 of FIG.
It needs to be configured so that the disparity appears. So the first
And the second switching signal SW₁, SW₂High level SW
_1H, SW _2HIs preferably as low as possible. However,
Current source I₀Must be within the range for normal operation. First
1st and 2nd switching signal SW₁, SW₂Low level S
W_1L, SW_2LIs a high level switch_1H, SW_2HAgainst
It is good if the transistor is as low as possible
There are no hard restrictions.

In the present embodiment, for example, in consideration of the case where the first to third circuits 1 to 3 require the same power supply voltage V _{CC to the} potential difference between the points A, B or C, FIG. As shown in, the high level SW _1H of the _first switching signal SW ₁ and the high level SW _{2H of the second} switching signal SW ₂ are set to the same level (voltage, for example, 2V). The voltage of the low level SW _2L of the _second switching signal SW ₂ is lower than the voltage of the low level SW _1L of the first switching signal SW ₁ (for example, 1.8 V) (for example, 1.6 V).
V). As a result, the first destination of the current I is supplied.
It is possible to arbitrarily switch between the first to third circuits 1 to 3 and operate the first to third circuits 1 to 3 well.

Next, the operation of the above configuration will be described. For example, when the second switching signal SW ₂ is input at a low level SW _2L to the base of the third transistor T _r5, first
Of the switching signal SW ₁ is input to the base of the first transistor T _{r1 at} the high level SW _1H , and the second transistor T _r2
When the low level SW _1L is input to the base of the first transistor, the first transistor T _r1 is turned on. In this case, the current I is supplied to the first circuit 1, so that the first circuit 1 is in the operating state. On the other hand, the first switching signal SW ₁ is input to the base of the first transistor T _r1 at low level SW _1L , and the high level SW is input to the base of the second transistor T _r2.
When input at _1H , the second transistor _Tr2 is turned on. In this case, the current I is supplied to the second circuit 2,
As a result, the second circuit 2 is activated.

On the other hand, when the second switching signal SW ₂ is input at the high level SW _2H to the base of the third transistor T _r5 , the first switching signal SW ₁ is transferred to the first transistor T _r1 . The high level SW _1H is input to the base, and the second
When the low level SW _1L is input to the base of the transistor T _r2, the base of the first transistor T _{r1 and} the base of the third transistor T _r5 have the same potential. At this time,
Since the ratio of the emitter area of the emitter area of the first transistor T _r1 third transistor T _r5 is set to 1: n, of the current I from the constant current source I ₀ {I / (1
+ N)} flows into the first circuit 1, and {(n · I) / (1
+ N)} will flow into the third circuit 3.

Similarly, when the second switching signal SW ₂ is input at the high level SW _2H to the base of the third transistor T _r5 , the first switching signal SW ₁ is switched to the first transistor T 1.
_r1 base entered at low level SW _1L of, when input in the second transistor T _r2 base high SW _IH of the bases of the third transistor T _r5 of the second transistor T _r2 is It becomes the same potential. At this time, since the ratio of the emitter area of the second transistor T _{r2 and} the emitter area of the third transistor T _r5 is set to 1: n, {I / (of the current I by the constant current source I ₀ 1+
n)} flows into the second circuit 2, and {(n · I) / (1+
n)} will flow into the third circuit 3.

Here, if the value of n is a relatively large value, for example, "4", when the second switching signal SW ₂ is at the high level SW _2H , the supply destination of the current I is the first or the second. The circuits 1 and 2 can be favorably switched to the third circuit 3.
As a result, the third circuit 3 is activated.

As described above, according to this embodiment,
A third point is formed at the midpoint of connection between the emitters of the transistor differential pair including the first and second transistors T _r1 and T _r2 .
Of the transistors T _r5 are connected in parallel and the ratio of the emitter area of the first and second transistors T _r1 and T _{r2 to} the emitter area of the third transistor T _r5 is 1: n (n> n). Since it is set to 1), the transistors that form the switching circuit are not connected in cascade. Therefore, from the constant current source I ₀ to the first current supply circuit,
-When the current I is supplied to the third circuits 1 to 3, the number of transistors to be passed through can be minimized, so that the influence of the transistor V _f can be minimized and a low power supply voltage such as 2.7 V can be used. It can also be applied to operating circuits.

The input levels of the first switching signal SW ₁ and the second switching signal ₂ are the high level SW _1H of the _first switching signal SW ₁ and the second switching signal SW _{2 as described above.}
The high level SW _{2H of} the
Voltage of the switch signal SW ₂ at the low level SW _2L is required to be set to a lower value with respect to the first switching signal SW ₁ of the low-level voltage SW _1L not always, the second switching signal SW ₂ Value of the high level SW _2H of the first switching signal SW
Is set to the high level SW _IH more values of _1, the value of the second switching signal SW ₂ at the low level SW _2L first switching signal S
If it is set to a value lower than the high level SW _{1H of} W ₁ , good switching operation can be realized.

FIG. 3 shows an example in which a so-called T-type flip-flop with a data setting function as shown in FIG. 8 is configured as a bipolar digital integrated circuit by applying the current switching circuit according to the present invention shown in FIG. It is a circuit diagram shown.

This circuit is a general one used when constructing a programming counter, and the circuit shown in FIG.
It has a two-stage structure of a stage (master) and a b stage (slave), and the same components as those of the conventional example shown in FIG. That, 1a, 1b the first circuit, 2a, 2b and the second circuit, 3a, 3b the third circuit, V _CC is the power supply _{voltage, Q 1a ~Q 6a, Q 1b} ~Q 6b is first to
The npn transistors forming the third circuits _{1a to 3a} and _{1b to 3b} , R _1a , R _2a , R _1b and R _2b are resistance elements, and T is a transistor.
_r1a and T _r1b are first transistors, T _r2a and T _r2b are second transistors, T _r3a and T _r3b are third transistors, Q _Ia and Q _Ib are npn transistors for current source, and R
_Ia and R _Ib are current source resistance elements, respectively.

The collector of the transistor Q _Ia for the a-stage constant current source I _0a is connected to the midpoint of connection between the emitter of the first transistor T _{r1a and} the emitter of the second transistor T _r2a of the a stage. Similarly, the collector of the transistor Q _Ib for the b-stage constant current source I _0b is the first transistor T of the b-stage.
The emitter of _r1b and is connected to a connection point between the emitter of the second transistor T _r2b.

Further, in the a stage, the collector of the first transistor T _r1a is connected to the midpoint of connection between the emitters of the transistors Q _1a and Q _2a of the first circuit 1a, and the second
Of the transistor T _r2a is connected to the connection midpoint between the emitters of the transistors Q _3a and Q _4a of the second circuit 2a, and the collector of the third transistor T _r3a is connected to the transistors Q _5a and Q of the third circuit 3a. It is connected to the midpoint between the emitters of _6a . Similarly, in the b stage, the collector of the first transistor T _r1b is connected to the connection midpoint between the emitters of the transistors Q _1b and Q _2b of the first circuit 1b, and the collector of the second transistor T _r2b is the second. The emitter of the transistors Q _3b and Q _4b of the circuit 2b is connected to the midpoint of connection between the emitters of the third transistor _Tr 3b and the collector of the transistor Q _5b and Q _6b of the third circuit 3b is connected to the midpoint of connection between the emitters thereof. Has been done.

In such a configuration, the signal D is input to the bases of the transistors Q _5a and Q _5b of the third circuits 3a and 3b in the a-stage and the b-stage, and the signal XD having a complementary level to the signal D is generated. It is input to the bases of the transistors Q _6a and Q _6b . In addition, the clock signal CK is the first switching signal S
A signal XCK which is inputted to the base of the second transistor T _{r2a in} the a stage and the base of the first transistor T _{r1b in} the b stage as W _{1 and} has a level complementary to the clock signal CK is the first switching signal SW. ₁ is input to the base of the first transistor T _{r1a in} the a stage and the base of the second transistor T _{r2b in} the b stage. Further, the set signal S is input as the second switching signal SW ₂ to the bases of the third transistors Tr _{3a in} both stages. And each transistor Q which comprises the 1st-3rd circuit 1b-3b of b stage
_1b to Q _6b output signal Q from the collector of the flip-flop, XQ is output.

For example, a set as the second switching signal
Third transition of a stage and b stage when the signal S is at high level
Star T_r5a, T_r5bIf entered in the base of
Flow I _a, I_bIs supplied to the third circuits 3a and 3b, and both times
The paths 3a and 3b are activated. This allows the input signal
D and XD are directly output from this circuit.

On the other hand, the set signal S at a low level is input to the bases of the third transistors T _r5a and T _{r5 b} , and in this state, the clock signals CK and XCK as the first switching signals are at a high level. Or, at low level, the first and second transistors T _r1a , T _r2a and T _r1b , T
_When input to the base of _r2b , the currents I _a and I _b are supplied to the first circuit 1a, 1b or the second circuit 2a, 2b, and the circuit 1a, 1b or 2a, 2b is activated. In this case, it functions as a T-type flip-flop in which the levels of the output signals Q and XQ are inverted according to the input levels of the clock signals CK and XCK.

FIG. 4 is a circuit diagram showing an example of a drive circuit for supplying each signal to the circuit of FIG. In FIG. 4, Q
_{11 to} Q ₁₉ are npn transistors, and R _{11 to} R ₁₅ are resistance elements.

Transistor Q₁₁And Q₁₂Same as the emitter
Is connected, and the emitter is connected to the midpoint between these emitters.
Dista Q₁₇Is connected to the collector of the transistor Q₁₇of
The emitter is a resistance element R₁₃Connected to ground GND via
Transistor Q₁₁And Q ₁₂Each collector of
Resistance element R₁₁, R₁₂Through the power supply voltage V_CCConnected to
There is. Transistor Q₁₁Collector and resistance element R₁₁With
The middle point of connection is transistor Q₁₃Connected to the base of
Together with the first signal XOUT₁Connected to the output of
Transistor Q₁₂Collector and resistance element R₁₂Connecting with
Point is transistor Q₁₂And is connected to the base of
To the first signal OUT₁Is connected to the output end of.

The collector of the transistor Q ₁₃ has a power supply voltage V
_It is connected to _CC and its emitter is connected to the output terminal of the second signal XOUT ₂ and the collector and base of the transistor Q ₁₅ . The collector of the transistor Q ₁₄ is connected to the power supply voltage V _CC , and the emitter is connected to the output terminal of the second signal OUT ₂ and the collector and base of the transistor Q ₁₆ . Therefore, the second signals OUT ₂ , XO
The level of UT ₂ is lower than the levels of the first signals OUT ₁ and XOUT ₁ by the forward voltage V _f of the transistors Q ₁₄ and Q ₁₃ .

The transistor emitter of Q ₁₅ is connected to the collector of the third signal XOUT _third output terminal and the transistor Q _18, the emitter resistance element of the transistor Q ₁₈ R
It is connected to the ground GND through ₁₄ . The emitter of the transistor Q ₁₆ is connected to the output terminal of the third signal OUT ₃ and the collector of the transistor Q ₁₉ ,
The emitter of ₁₉ is connected to the ground GND via the resistance element R ₁₅ . The base of the transistor Q ₁₇ to Q ₁₉ is connected to a power source V _BB. Therefore, the third signal O
The levels of UT ₃ and XOUT ₃ are the second signals OUT ₂ and X.
It is lower than the level of OUT ₂ by the forward voltage V _f of the transistors Q ₁₆ and Q ₁₅ .

In this drive circuit, the drive input signal IN is input to the base of the transistor Q ₁₁ , and the signal IN
A signal XIN having a level complementary to that of the transistor Q ₁₂ is input to the base of the transistor Q ₁₂ , and the differential outputs of the transistors Q ₁₁ and Q ₁₂ are output as the first signals OUT ₁ and XOUT ₁ and also the transistors Q ₁₃ and Q _14. Entered in the base of. The transistors Q ₁₃ and Q ₁₄ to which the differential outputs of the transistors Q ₁₁ and Q ₁₂ are input are differentially turned on / off, and their emitter outputs are output as the second signals OUT ₂ and XOUT ₂ . Transistor Q
_15, respectively collector and base of Q ₁₆ are inputted. The transistors Q ₁₅ and Q ₁₆ are so-called diode-connected, and are turned on / off according to the levels of the _second signals OUT ₂ and XOUT ₂ , and their emitter outputs are output as the third signals OUT ₃ and XOUT _3. It

The first to third stages a and b of the circuit of FIG.
The high level of the base voltage of each of the transistors Q _{1a to} Q _6a and Q _{1b to} Q _6b forming the circuits 1a to 3a and _{1b to 3b} is almost set to operate even under a low power supply voltage such as 2.7V. Set to V _CC . Therefore, FIG.
When driving the circuit of FIG. 3 using the drive circuit of
The first signal OUT ₁ of the circuit of FIG. 4 is used as the signal D, and the first signal XOUT ₁ is used as the signal XD having a complementary level to the signal D. The first to third transistors T _r1a , T _r2a , T _r5a , T _r1b , T _r2b ,
As the high level of the base voltage of T _r5b , the second signals OUT ₂ and XOUT ₂ of the circuit of FIG. 4 are used. In particular,
The second signal OUT ₂ is used as the signals CK and XCK that are the first switching signals SW ₁ , and the second signal XOUT ₂ is used as the signal S that is the second switching signal SW ₂ .
(V _CC -V _f) is set to be high level.
As a result, in the circuit of FIG. 3, the maximum number of transistor connection stages is three in the current supply line, so that the circuit can operate even when (V _CC ≈3V _f ). Specifically, considering V _f = 0.7V, the power supply voltage V _CC
= 2.7V can realize a circuit that can operate sufficiently.

On the other hand, in the case of the conventional circuit shown in FIG. 7, the transistors T _r3a , T _{r4 a} , T _r3b and T _{r4b are included.}
It is necessary to use the third signals OUT ₃ and XOUT ₃ of the drive circuit shown in FIG. 4 as the second switching signal to be input to the base of ( ₃ ), and (V _CC ≈4V _f ) is a practical limit.

It should be noted that only the a stage of the circuit of FIG.
Transistor Q of circuit 1a_1a, Q _2aExternal to the base of
From the input signal to the specified level.
As a D-type flip-flop with data setting function
Can be activated.

[0056]

As described above, according to the present invention,
It is possible to realize a circuit that can sufficiently operate even under a low power supply voltage.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a current switching circuit according to the present invention.

FIG. 2 is a diagram showing a setting level example of a switching signal according to the present invention.

3 is a circuit diagram showing an example in which the current switching circuit according to the present invention shown in FIG. 1 is applied to form a bipolar digital integrated circuit.

4 is a circuit diagram showing an example of a drive circuit for supplying each signal to the circuit of FIG.

FIG. 5 is a configuration diagram showing an example of a conventional current switching circuit.

FIG. 6 is a diagram showing a setting level example of a switching signal in a conventional circuit.

FIG. 7 is a circuit diagram showing an example in which the conventional current switching circuit shown in FIG. 5 is applied to form a bipolar digital integrated circuit.

FIG. 8 is a diagram showing a configuration example of a T-type flip-flop.

[Explanation of symbols]

1, 1a, 1b ... First circuit 2, 2a, 2b ... Second circuit 3, 3a, 3b ... Third circuit T _r1 , T _r1a , T _r1b ... First transistor T _r2 , T _r2a , T _r2b ... second transistor _{T r5, T r5a, T r5b} ... third transistor _{I 0, I 0a, I 0b} ... constant current source SW ₁ ... first switching signal SW ₂ ... second switching signal Q _1a ~ Q _6a , Q _{1b to} Q _6b , Q _Ia , Q _Ib , Q _{11 to} Q ₁₉ ... N
pn-type transistors R _1a , R _2a , R _1b , R _2b , R _Ia , R _Ib , R _{11 to} R ₁₄ ... Resistance element

Claims (4)

[Claims] 1. A current switching circuit for switching a current supply destination among a first circuit, a second circuit and a third circuit, wherein emitters are connected to each other, and a middle point of connection between these emitters is a current source. A first and a second transistor connected to each other, and a third transistor whose emitter is connected to a connection midpoint between the emitters of the first and the second transistors, the collector of the first transistor Is connected to the first circuit, the collector of the second transistor is connected to the second circuit, and the collector of the third transistor is connected to the third circuit.
The current switching circuit is characterized in that it is connected to the circuit. 2. The bases of the first and second transistors are respectively connected to the input lines of the first switching signal which complements the high level and the low level, and the bases of the third transistor are set to the high level. It is connected to an input line of a second switching signal that takes a low level binary value, and the high level value of the second switching signal is set to a value equal to or higher than the high level of the first switching signal. The current switching circuit according to claim 1, wherein the low level value of the switching signal is set to a value lower than the high level of the first switching signal. 3. The ratio between the emitter area of at least one of the first and second transistors and the emitter area of the third transistor is set to 1: n. Current switching circuit. 4. The first, second, and third circuits each have two transistors whose emitters are connected to each other and whose collectors are connected to a power supply voltage. The two transistors of each circuit have their emitters connected to each other. The middle point is connected to the collectors of the first, second and third transistors, respectively, and in either one of the first circuit and the second circuit, the collector of one transistor and the base of the other transistor are connected. The current switching circuit according to claim 1, wherein the current switching circuits are connected to each other.