JPS61140218A - Inputting circuit - Google Patents

Abstract

PURPOSE:To enable the titled circuit to select either of ECL and TTL level input by controlling action of two current source circuits and changing the value of power source voltage supplied to a power source terminal. CONSTITUTION:Current source circuits 54, 58 consists of NPN type transistors 91, 92 respectively, resistances 93, 94 for restricting current inserted between emitters of transistors 91, 92 and a power source terminal 46 and a controlling circuit 95 that supplies controlling signals to bases of transistors 91, 92. A change-over signal is inputted to the controlling circuit 95, and when the change- over signal is made to '1' level, the controlling circuit 95 outputs the voltage of, for instance 1V, to the transistor 91, and outputs voltage of '0' V to the transistor 92. The transistor 91 in the current source circuit 54 is made operating state, and current is made to flow through the transistor 91. On the other hand, when the change-over signal is made to '0' level, the controlling circuit outputs voltage of OV to the transistor 91, and outputs the voltage of 1V to the transistor 92.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a digital signal input circuit capable of selecting input characteristics corresponding to both ECL logic and TTL logic and outputting an ECL logic signal. Regarding.

[Technical background of the invention and its problems] When processing digital signals, there are cases in which signals are handled at TTL level and signals at ECL level. In particular, when processing digital signals, there are cases in which signals are handled at TTL level and signals at ECL level. In the converting circuit, if the operating speed is relatively low (clock pulse frequency is 20 MHz or less), the input signal is handled at TTL level, and if the operating speed is relatively high (clock pulse frequency is 50 MHz or higher), it is handled at ECL level.
It is preferable to treat it at the level.

FIG. 3 is a circuit diagram of a conventional input circuit that handles signals at the ECL level. This input circuit includes a differential circuit 13 consisting of two npn transistors 11 and 12, and a collector of one of the transistors 11 and an earth voltage (OV) GND.
The resistance value is, for example, 4 Ω.
The load resistance 14 is set to , and the other transistor 1 is set to
A load resistor 15 is inserted between the collector of No. 2 and the application point of the earth voltage GND, and the resistance value is also set to 4Ω, and the common connection point of the emitters of both transistors 11 and 12 is set to, for example, −5 V. a current source 16 whose value is set to, for example, 75 μA; and a current source 16 inserted in series between the application point of the ground voltage GND and the application point of the power supply voltage VEE; It is composed of a pair of resistors 17 and 18 that divide the voltage VEE.

An input signal is supplied to the base of the transistor 11, and resistors 17 and 18 are supplied to the base of the transistor 12.
For example, a voltage of -1°3V divided according to the resistance ratio of is supplied, and the threshold voltage for the input signal of this circuit is set to -1.3V.

Therefore, when the absolute value of the input signal voltage decreases by -1.3cm, the transistor 11 is turned on, and the voltage at the collector of the transistor 11 is 0.3V lower than the ground voltage.
Only the lower voltage will be applied. On the other hand, since the transistor 12 is turned off at this time, the transistor 1
The voltage on the collector of No. 2 is set to OV.

Next, when the absolute value of the input signal voltage rises from -1.3V, the transistor 12 is turned on, and the voltage at the collector of the transistor 12 is 0.3V higher than the ground voltage.
The voltage is lowered by 3V, while the voltage at the collector of transistor 11 is brought to OV.

In this way, the threshold voltage of the above input circuit is set to -1°3V, and the voltage amplitude of the output signal is set to 0.3■.As a result, this circuit is an input circuit with an ECL level input and an ECL level output. As a child.

FIG. 4 is a circuit diagram of a conventional input circuit that converts a TTL level input to an ECL level input. This input circuit is a differential circuit 2 consisting of two npn type transistors 21 and 22.
3. The collector of one of the transistors 21 and, for example, +
A load resistor 24 is inserted between the application point of the power supply voltage Vcc set to 5■, and whose resistance value is set to, for example, 4Ω.
, the collector of the other transistor 22 and the voltage l! Voltage Vc
A load resistor 25, which is inserted between the application point of c and whose resistance value is also set to 4Ω, and both transistors 21
．． A current source 26 is inserted between the common emitter connection point of 22 and the application point of the earth voltage GND, and the value is set to, for example, 75 μA, and an npn type transistor whose emitter is connected to the application point of the earth voltage GND. 27, an npn type transistor 2 whose emitter is connected to the application point of the ground voltage GND, whose base and collector are short-circuited, and whose base is connected to the base of the transistor 27;
8. An npn type transistor 29 whose emitter was connected to the collector of the transistor 27, the emitter was connected to the collector of the transistor 28, the base and collector were short-circuited, and the base was connected to the base of the transistor 29. an npn-type transistor 30, a pair of resistors 31 and 32 inserted in series between the collector of the transistor 30 and the application point of the power supply voltage Vcc;
The collector of the transistor 29 and the power supply voltage Vcc
and an npn type transistor 34 whose collector is connected to the application point of the power supply voltage Vcc, whose emitter is connected to the emitter of the transistor 29, and whose base is supplied with the input signal. It is configured.

The base of the transistor 21 is connected to the resistors 31 and 32.
The base of the transistor 22 is connected to the connection point between the resistor 33 and the collector of the transistor 29.

In such a configuration, the transistors 34 and 29 constitute a differential circuit, and the base voltage of the transistor 29 is set to the sum of the base-to-emitter voltages of the transistors 28 and 30. Therefore, if the voltage between the base and emitter of one npn type transistor is 0.7V, the threshold voltage of the transistor 34 to which the input signal is supplied is set to 1.4V. Here, the input signal voltage is 1.
If the voltage is below 4V, transistor 34 is turned off and transistor 429 is turned on. At this time, two resistors 31 and 32 connected in series
A current corresponding to the sum of the resistance values of the resistors 31 and 32 and a voltage of 3.6 mm obtained by subtracting a voltage of 1.4 V, which is equal to the base voltage of the transistor 29, from 5 V, flows through the transistor.

Now, the value of one of the resistors 31 is 1Ω, and the value of the other resistor 32 is
If the value of is set to 10Ω, these two resistors 31
A current of approximately 360 mA flows through and 32. In the resistor 31, a voltage drop of about 0.3 V is generated depending on the current of 360 mA and the resistance value 1 of the resistor 31, so that the base voltage of the transistor 21 is set to about 4.7 Ω.

On the other hand, when the above-described current flows through both the resistors 31 and 32, a current having a value equal to this current is passed through the resistor 33 by the current mirror circuit consisting of the transistors 29 and 30.
It also flows. If the value of this resistor 33 is set to 2Ω, this resistor 33 has a current of 360 mA and its resistance value 2
Since a voltage drop of about 0.6V occurs depending on Ω, the base voltage of the transistor 21 is set to about 4.4V. That is, when the transistor 34 is turned on,
The base voltage of one transistor 21 constituting the differential circuit 23 is set to 4.7 cm, and the base voltage of the other transistor 22 is set to 4°4 cm. Therefore, transistor 2
1 is turned on, and transistor 22 is turned off.

Here, the value of the current source 26 is set to 75 μA,
Since the value of the load resistor 24 is set to 4Ω, the voltage at the collector of the transistor 21 is set to 4.7Ω, which is 300 mV lower than the power supply voltage Vcc of 5Ω, that is, by 0.3Ω, and The voltage of the collector is set to 5μ of the 74 source voltage.

Next, when the input signal voltage rises from 1.4■, the transistor 34 is turned on and the transistor 29 is turned off, so that the current that has been flowing through the resistor 33 stops flowing. As a result, the base voltage of the transistor 22 is set to 5■, and the transistor 21 is now turned off and the transistor 22 is turned on. Therefore, at this time, the voltage at the collector of the transistor 22 is set to 4.7V, which is lower than the 5'R source voltage Vcc by 0°3V, and the voltage at the collector of the transistor 21 is set to 5', which is the power supply voltage.

In this way, the input circuit has a threshold voltage of 1°4■,
The voltage amplitude of the output signal is set to 0.3V, and as a result, this circuit operates as an input circuit with a TT level input and an ECL level output.

By the way, the above-mentioned A conversion circuit is required to handle both TT level and ECL level signals.
In order to meet such requirements, the above figures 3 and 4 should be met.
It is necessary to provide an input circuit IC as shown in the figure and use it properly.

For this reason, conventionally, input circuits have been developed in which a single circuit can handle both TTL input and ECL input. However, such a circuit requires a power supply with both positive and negative polarity when used with TTL input, and if the circuit at the front stage that generates the input signal operates with a single power supply, This is inconvenient because a new power source with negative polarity must be prepared.

[Purpose of the invention] This invention was made in consideration of the above circumstances, and its purpose is to operate with a single power supply and to combine ECL logic and T
An object of the present invention is to provide an input circuit with an ECL level output that can select input characteristics corresponding to both rings of TL logic.

[Summary of the Invention] In order to achieve the above object, an input circuit of the present invention includes a first transistor of a first polarity and a second transistor of a second polarity.
The bases of the transistors are connected in common, an input signal is supplied to this base common connection point, and the emitters of the third transistor and the fourth transistor of the first polarity are connected in common to form a first differential circuit. A first current source circuit whose operation is controlled according to the IIIt signal is inserted between the first differential circuit and the first power supply voltage application point, and a fifth current source circuit of the first polarity is inserted. A second differential circuit is configured by connecting the emitters of the transistor and the sixth transistor in common, and an operation is performed between the second differential circuit and the first power supply voltage application point according to a control signal. Insert a second current source circuit to be controlled,
The base of the third transistor is coupled to the emitter of the first transistor, the collectors of the third and sixth transistors are connected to each other, and the collectors of the fourth and fifth transistors are connected to each other, 4th above
and a common constant DC bias voltage is supplied to the bases of the fifth transistor, and the collector connection points of the third and sixth transistors and the collector connection points of the fourth and fifth transistors are respectively connected to the second power supply voltage. A load means is inserted between the application point and the application point.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an input circuit according to the present invention. In the figure, the collector of an npn type transistor 42 is connected to the first power supply terminal 41. The emitter of this transistor 42 is an npn type transistor 43
connected to the collector and base. The emitter of the transistor 43 is connected to a second power supply terminal 46 via two resistors 44 and 45 in series. A signal input terminal 41 to which an input signal is supplied is connected to the base of the transistor 42.
The base of a pnp type transistor 48 is connected to. The collector of this transistor 48 is connected to the second power supply terminal 46.

Two npn type transistors 51 and 52 have their emitters connected in common to form a differential circuit 53, and there is a connection point between the common emitter connection point of the differential circuit 53 and the second power supply terminal 46. A current source circuit 54 is inserted in which the current output operation can be controlled. Similarly, the emitters of the two npn transistors 55 and 56 are commonly connected to form a differential circuit 57, and the emitter common connection point of the differential circuit 57 and the second power supply terminal 46 are connected to each other. A current source circuit 58 whose current output operation can be controlled is inserted between the two. The base of the transistor 51 is connected to the series connection point 49 of the resistors 44 and 45, and the base of the transistor 56
The bases of transistors 52 and 55 are connected to the emitters of transistor 48, respectively, and the bases of transistors 52 and 55 are connected in common. Roughly speaking, the collectors of the transistors 51 and 56 are connected in common, and the collectors are connected to a first signal output terminal 59, which is a common connection point, and the first power supply terminal 41.
A load resistor 60 is inserted between them. Further, the collectors of the transistors 52 and 55 are connected in common, and a load resistor 62 is inserted between the second signal output terminal 61, which is a common connection point between the collectors, and the first power supply terminal 41.

Furthermore, the base and collector of an npn transistor 71 are commonly connected to the first power supply terminal 41, and three resistors 72 and 73 are connected between the emitter of this transistor 71 and the second power supply terminal 46. .74 are connected in series. The base of an npn transistor 76 is connected to the series connection point 75 between the resistors 12 and 73.
The bases of npn type transistors 78 are connected to the series connection points 77 of the transistors 3 and 74, respectively. The collector of the transistor 76 is connected to the first power supply terminal 41, and the emitter is connected to the second power supply terminal 4 through a resistor 79.
6.

Similarly, the collector of the transistor 78 is connected to the first power supply terminal 41, and the emitter is connected to the second power supply terminal 46 via a resistor 80. The emitter of the transistor 76 is further connected to a common connection point 82 between the base of the transistor 56 and the emitter of the transistor 48 via a resistor 81, and the emitter of the transistor 78 is further connected to the common connection point 82 between the base of the transistor 56 and the emitter of the transistor 48.
It is connected to the base common connection point 83 of No. 5.

In the circuit of FIG. 1, for example, load resistors 60 and 62
It is assumed that the values of both are set to 4 and Ω, and the current values of the current source circuits 54 and 58 are both set to 75 μA. Further, in the following description, it is assumed that the voltage between the base and emitter of one transistor is, for example, 0.7V.

When using such an input circuit as an ECL level input circuit and an ECL level output circuit, the first power supply terminal 4
1 is supplied with an earth voltage of OV, and a negative polarity 'II source voltage, for example -5V, is supplied to the second power supply terminal 46. At the same time, one current source circuit 54 is brought into operation, and the other current source circuit 58 is brought into non-operation state. This enables only one differential circuit 53 to operate.

At this time, a voltage drop of 0.7V occurs between the base and emitter of the transistor 71, and a voltage of 4.3V is applied across the three resistors 72 and 13.14 connected in series. has been done. Therefore, these resistances 72.73
．． A current of approximately 1 mA, which is obtained by reducing this voltage of 4.3 V by the sum of the resistance values of the resistors 72 and 73.74, flows through γ4. As this current flows through the resistor 74, approximately 2.
A voltage drop of 9 cm occurs, and the base potential of the transistor 78 is set to about 2.9 cm with respect to the second power supply terminal 46. The emitter potential of this transistor is 0 from the base potential
．． Since the voltage is reduced by 7V, the transistor 52
The potential of the base common connection point 83 of and 55 is set to about 2.2V with respect to the second power supply terminal 4G. This potential is the first
Based on the voltage of OV supplied to the power supply terminal 41 of , it is approximately -2.8V.

In this state, the voltage at the signal input terminal 41 is O.
When the voltage is set to V, the emitter potential of the transistor 43 is set to a voltage lower than OV by 1.4 cm, which is the base-emitter voltage of two transistors, and the voltage between the resistors 44 and 45 is approximately 3 cm. A voltage of .6v is applied. The above voltage 3.6cm is applied between both ends of the resistor 44.
A voltage drop of approximately 0.3v occurs, divided based on the resistance ratio of and 45. Therefore, at this time, the base voltage of the transistor 51 is set to about -1.7.

Now, as mentioned above, the base voltage of the transistor 51 is -1
, 7■, the base voltage of the transistor 52 is -2.8V.
, transistor 51 is turned on and transistor 52 is turned off. As a result, a voltage drop of 0.3 V occurs between both ends of the load resistor 60, which is equal to the resistance value W1 of the resistor 60 and the voltage II of the current source circuit 54, and the voltage at the first signal output terminal 59 is - 0.3V
be made into On the other hand, as the voltage of the second signal output terminal 61, the voltage OV of the power supply terminal 41 is output as is.

Next, from this state, the voltage of the input signal is lowered from OV, and when the value reaches -1.3V, the voltage at the series connection point 49 of resistors 44 and 45 becomes -2.8V, and the differential circuit 53 becomes balanced. become a state.

When the voltage of the input signal is further lowered, the transistor 51 is turned off and the transistor 52 is turned on. As a result, the voltage of the first signal output terminal 59 is set to Ov, and the voltage of the second signal output terminal 61 is set to 10.
It is set to 3V. Therefore, in this case, this circuit is -1,3■
When the ECL level input is set to the threshold voltage, the circuit performs EC with an output amplitude of 0.3V and operates as a level output input circuit.

Next, when using such an input circuit as a circuit with TTL level input and ECL level output, a positive power supply voltage, for example 5■, is supplied to the first power supply terminal 41, and the second
A ground voltage of OV is supplied to the power supply terminal 46 of. At the same time, one current source circuit 53 is rendered inactive, and the other current source circuit 58 is rendered operational. This now enables only the difference 1!1 circuit 51.

At this time, as above, there is approximately 2.9
A voltage drop of (2) occurs, and the base potential of the transistor 78 is set to approximately 2°9 (2) with respect to the second power supply terminal 46.

The emitter potential of this transistor is 0.0.
Since the voltage is lowered by 7V, the potential at the common base connection point 83 of the transistors 52 and 55 is the same as the second power supply terminal 4.
It is approximately 2°2■ based on 6. That is, the voltage at the common base connection point 83 of transistors 52 and 55 is approximately 2
．． 2■

In this state, the voltage at the signal input terminal 47 is O.
When the voltage is set to V, the potential of the connection point 82 to which the emitter of the transistor 48 is connected is 0.7cm which is the base-emitter voltage of the transistor 11i1, which is lower than OV.
is set to a higher voltage, that is, 0.7V. Therefore, at this time, transistor 55 is turned on and transistor 56 is turned off. As a result, the voltage at the first signal output terminal 59 is set to 5V, and the voltage at the second signal output terminal 61 is set to 5V.
The voltage is set to 4°7V.

Next, from this state, the voltage of the input signal is increased by ov, and when the value reaches 1.5V, the emitter voltage of the transistor 48, that is, the voltage at the connection point 82, becomes 2.2V.
The differential circuit 57 is in a balanced state.

When the voltage of the input signal is further increased, transistor 55 is turned off and transistor 56 is turned on. As a result, the voltage at the first signal output terminal 59 is set to 5■, and the voltage at the second signal output terminal 61 is set to 4.7.
■ be made into. Therefore, in this case, this circuit has a TTL level input with a threshold voltage of 1.5V and an output amplitude of 0.
Operates as an input circuit for ECL level output at 3V.

In this way, the input circuit of the above embodiment controls the operation of the two current source circuits 54 and 58, and also controls the power supply terminals 41 and 461.
By changing the value of the power supply voltage supplied to il, the EC
Either L level input or TTL level input can be selected. Therefore, ECL level input and T
When operating with either TL level logic, a single N source may be used.

FIG. 2 is a circuit diagram showing a specific configuration of current source circuits 54 and 58 used in the circuit of the above embodiment. Current source circuit 54
and 58 are npn type transistors 91.92, respectively, and a current limiting resistor 93.9 inserted between the emitter of each of these transistors 91.92 and the power supply terminal 46.
4 and a control circuit 95 that supplies control signals to the bases of each of the transistors 91 and 92. A switching signal is input to the control circuit 95, and when this switching signal is at the "1" level, the control circuit 95 outputs, for example, a voltage of 1 to the transistor 91, and a voltage of 0 to the transistor 92. As a result, the transistor 91 in the current source circuit 54 is activated, and the current is caused to flow through the transistor 91.On the other hand, when the switching signal is at the “''O゛° level, The control circuit 95 outputs a voltage of Ov to the transistor 91 and a voltage of 1V to the transistor 92.

This causes the transistor 92 in the current source circuit 58 to be activated, and the current flows through the transistor 92.

It goes without saying that this invention is not limited to the above-mentioned embodiment, and that various modifications are possible. For example, in the above embodiment, the means for supplying a constant DC bias voltage to the base common connection point 83 of the transistors 52 and 55 is a circuit consisting of resistors 72, 73, 74, the transistor 78, etc., and has sufficient current supply capability. Although the explanation has been made for the case of a multi-bit signal, this takes into consideration the fact that such an input circuit is provided for a plurality of bits. That is, when such input circuits are provided for a plurality of bits, the emitter voltage of the transistor 18 is supplied in parallel to the connection point 83 of each input circuit. Therefore,
If such input circuits are provided for only a few bits at most, a constant DC bias voltage obtained by resistor division may be directly supplied to the connection point 83 of each input circuit.

[Effects of the Invention] As explained above, the present invention provides an input circuit with an ECL level output that operates with a single power supply and can select input characteristics compatible with both ECL logic and TTL logic. can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an input circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram specifically showing a part of the above embodiment circuit;
FIGS. 3 and 4 are circuit diagrams of conventional input circuits, respectively. 41...first power supply terminal, 42.43.51.52.
55.56°71, 76, 78... nDn type transistor, 44.45°72, 73.74.79.80.
81...Resistor, 46...Second 'R power supply terminal 48.
...pno! ! ! transistor, 53.57...differential circuit, 54.58...current source circuit, 59.61...
・Signal output terminal, 60.62...Load resistance.

Claims (1)

[Claims] a first transistor of a first polarity and a second transistor of a second polarity, the bases of which are commonly connected and an input signal is supplied to the common base connection point; and a third transistor of the first polarity, whose emitters are commonly connected. a first differential circuit including a transistor and a fourth transistor, and a first differential circuit that is inserted between the first differential circuit and a first power supply voltage application point and whose operation is controlled according to a control signal. a current source circuit, a second differential circuit comprising a fifth transistor and a sixth transistor of a first polarity whose emitters are commonly connected; a second current source circuit inserted between the points and whose operation is controlled according to the control signal; means for coupling the emitter of the first transistor to the base of the third transistor; means for connecting the collectors of the sixth transistor; means for connecting the collectors of the fourth and fifth transistors; and supplying a common constant DC bias voltage to the bases of the fourth and fifth transistors. and a load means inserted between the collector connection point of the third and sixth transistors, the collector connection point of the fourth and fifth transistors, and the second power supply voltage application point. An input circuit characterized by: