JPS59146226A - Differential circuit - Google Patents

Differential circuit

Info

Publication number
JPS59146226A
JPS59146226A JP59007149A JP714984A JPS59146226A JP S59146226 A JPS59146226 A JP S59146226A JP 59007149 A JP59007149 A JP 59007149A JP 714984 A JP714984 A JP 714984A JP S59146226 A JPS59146226 A JP S59146226A
Authority
JP
Japan
Prior art keywords
current
transistor
base
circuit
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59007149A
Other languages
Japanese (ja)
Inventor
Teruo Isobe
磯部輝雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59007149A priority Critical patent/JPS59146226A/en
Publication of JPS59146226A publication Critical patent/JPS59146226A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/603—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors with coupled emitters

Landscapes

  • Static Random-Access Memory (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To obtain a pulse current source driven by a small amplitude pulse, operated stably in high speed and suitable for circuit integration by applying a pulse signal to an input of a current switching type circuit and driving a circuit supplying a current to a load by the collector side output of an n-p-n transistor (TR). CONSTITUTION:A reference voltage VBB is applied to a base of a TRQ1 of a current switch, a pulse voltage Vin is applied to a base of the other TRQ2 and a constant voltage Vc3 is applied to a base of a constant current TRQ7. Further, a p-n-p TRQ3 having an impedance Z4 is provided and a base of the TR is connected to one output point of a current switch. Further, a drive circuit comprising n-p-n TRQ41 (Q42-Q4n) and an emitter resistor Z51 (Z52-Z5n) is provided. A slight bias is given to the base of a p-n-p TRQ3 at all times and the on-operation is quickened, then the high speed operation is expected as the entire circuit.

Description

【発明の詳細な説明】 本発明いよパルス電流源、特に複数の負荷に同時に所定
のパルス電流を供給するのに適する・クルレス電流源等
に有効な差動回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse current source, and particularly to a differential circuit that is effective for a pulseless current source that is suitable for simultaneously supplying a predetermined pulse current to a plurality of loads.

一般に、磁気コアメモリ、ＩＣメモリ等の周辺回路では
パルス軍１流源が利用されている。磁気コア等に所定の
パルス電流を供給するＴこめでちる。Generally, a pulse source is used in peripheral circuits such as magnetic core memory and IC memory. A T-column that supplies a predetermined pulse current to the magnetic core, etc.

このようなパルス電流源として、従来は、第１図に示す
ような不飽和形スイッチが用いられていた。Conventionally, an unsaturated switch as shown in FIG. 1 has been used as such a pulse current source.

このスイッチは、入力電圧■・　が低レベル■５のｎ ときトランジスタ３が非導通状態となり、それが高レベ
ルＶ□のとき導通状態となって負荷（磁気コア）４に電
流を供給するものである。In this switch, the transistor 3 becomes non-conducting when the input voltage ■ is at a low level ■5, and becomes conductive when it is at a high level V□, supplying current to the load (magnetic core) 4. be.

し、かじながら、このようなスイゾチング回路では、温
度変化等のため動作が不安定となり、また、出力電流レ
ベルが入カバルスの振幅レベルの変動により変動し易い
欠点を有している。これらの点で、この回路はパルス電
流源としては不利益を免かれえない。この欠点を除くに
は、エミッタに接続されたフィードバック抵抗５を大な
るものとずればよいが、これでは太きブよパルス入力を
要することにブより、ひいてはトランジスタの所要耐圧
の増大及び消費電力の増大さらには集積度の低下を招く
結果となってしまう。However, such a swiss-charging circuit has the disadvantage that its operation becomes unstable due to changes in temperature and the like, and that the output current level easily fluctuates due to fluctuations in the amplitude level of the input pulse. In these respects, this circuit is inevitably disadvantageous as a pulse current source. To eliminate this drawback, it is possible to increase the feedback resistor 5 connected to the emitter, but this requires a thicker pulse input, which in turn increases the required withstand voltage of the transistor and increases power consumption. This results in an increase in the amount of data and a decrease in the degree of integration.

したがって本発明の目的とするところは、小振幅パルス
で駆動でき、高速且つ安定に動作し、集積化するのに適
するパルス電流源を提供することにある。Therefore, an object of the present invention is to provide a pulsed current source that can be driven with small amplitude pulses, operates at high speed and stably, and is suitable for integration.

上記Ｌ１的を達成づ−るための本発明の一実施例は、電
流リノ替型回路と、この電流切替型回路の出力によって
駆動される１、）　ｎ　ｐ　トランジスタと、このｐｎ
　ｐ　）ランジスタのコ１／クタ側に設けられたインピ
ーダンス十段とからｆＪ、す、−」二記゛杷流切替型回
路の人力にはパルス信号を印加し、上記ｎ　ｐ　ｎ　ト
ランジスタのコレクタ側出力によって負荷に電流を供給
する回路を駆動してなることを特徴とするものである。An embodiment of the present invention for achieving the above L1 goal includes a current switching circuit, a 1) n p transistor driven by the output of the current switching circuit, and a pn transistor driven by the output of the current switching circuit.
p) From the ten stages of impedance provided on the collector side of the transistor f This is characterized in that the output drives a circuit that supplies current to a load.

以−ト実施例にそって図面を参照ｊ〜本発明を具体的に
説明′炙る。The present invention will now be described in detail with reference to the drawings in accordance with embodiments.

第２図は本発明のパルス電流源の一例を示す回路図であ
る。同図に示すように、エミッタ結合型の差動対ｎｐｎ
ｈランジスタＱ、、Ｑ、と、このトランジスタのコレク
タに接続されたインピーダンスＺｚ　、　　Ｚ２及び定
電流ｎｐｎトランジスタＱ？　＋エミッタ抵抗Ｚ？によ
ってカレントスイッチを構成味このカレントスイッチの
一方のトランジスタＱ１のベースには基準電圧■ＢＢを
印加し、他方のトランジスタＱ２のベースにはパルスｉ
［圧Ｖ、ｎを印加し、定電流トランジスタＱ７のベース
Ｋｕ定電圧■。８を印加する。またエミッタ抵抗Ｚ、を
有（〜、コレクタ側に負荷たるインピーダンスＺ４（ダ
イオードＤＩ、Ｄ２を直列接続したもの）を有するｐｎ
ｐトランジスタＱ、を設け、このトランジスタのベース
を上記カレントスイッチの一方の出力点（トランジスタ
Ｑ１のコレクタ）に接続する。さらに、ｎｐｎ）ランジ
スタＱ、、　（Ｑ４□〜Ｑ　）とエミッタ抵抗Ｚｌｌｌ
　（ＺＩ１２〜ｚ５ｎ）からなるｎ 駆動回路を設け、上記ｐｎｐ）ランジスタＱ、のコレク
タ側出力を駆動回路の駆動ｌ・ランジスタＱ４Ｉ（Ｑ４
．〜Ｑ４ｎ）のベースに印加し、駆動回路によってそれ
ぞれの負荷Ｚ、１〜ｚｎを駆動するものとする。なお、
電源ＶＥｌｉ、−−５，２Ｖとする。FIG. 2 is a circuit diagram showing an example of the pulse current source of the present invention. As shown in the figure, an emitter-coupled differential pair npn
h transistor Q, , Q, impedance Zz, Z2 connected to the collector of this transistor, and constant current npn transistor Q? +Emitter resistance Z? A current switch is constructed by applying a reference voltage BB to the base of one transistor Q1 of this current switch, and applying a pulse i to the base of the other transistor Q2.
[Apply voltages V and n, and constant voltage Ku at the base of constant current transistor Q7. Apply 8. It also has an emitter resistance Z (~, a pn with an impedance Z4 (diodes DI and D2 connected in series) as a load on the collector side).
A p-transistor Q is provided, and the base of this transistor is connected to one output point of the current switch (collector of transistor Q1). Furthermore, npn) transistor Q,, (Q4□~Q) and emitter resistance Zllll
An n drive circuit consisting of (ZI12 to Z5n) is provided, and the collector side output of the transistor Q (pnp) is connected to the drive l of the drive circuit, transistor Q4I (Q4
．． ~Q4n), and the respective loads Z, 1 to zn are driven by the drive circuit. In addition,
The power supply VEli is set to −5.2V.

上記構成の本発明によれば、以下の動作説明により、そ
の目的が達成できる理由が理解されよう。According to the present invention having the above configuration, the reason why the object can be achieved will be understood from the following explanation of the operation.

第３図は上記回路の動作を説明するためのタイミングチ
ャートである。FIG. 3 is a timing chart for explaining the operation of the above circuit.

（１）■ｉｎが高レベル″Ｈ”のとき。(1) When ■in is at a high level "H".

カレントスイッチの接地電位側に接続されたインピーダ
ンスＺ１を流れる電流を１として、この点の電圧降下１
×Ｚｌの値がｐｎｐ　トランジスタＱ、の■ＢＥ　（ベ
ース・エミッタ間電圧）よりも極めて小さなものどなる
ように設定すれば、入力電圧■　がＨ″であることより
、カレントスイソ１１ チのトランジスタＱ１には殆んど電流が流れない。Assuming that the current flowing through the impedance Z1 connected to the ground potential side of the current switch is 1, the voltage drop at this point is 1
If the value of ×Zl is set to be extremely smaller than the BE (base-emitter voltage) of the pnp transistor Q, then since the input voltage is H'', the current iso-11 transistor Q1 Almost no current flows.

し、たがって、このカレントスイ・ンチの出力点の電位
■１は殆んどインピーダン２２１部の電圧降下ＴＸ、Ｚ
、　　であり、このためｐｎｐトランジスタＱ３はカッ
トオフか又はごく僅かの電流しか流れないものとなる。Therefore, the potential (1) at the output point of this current switch is almost equal to the voltage drop TX, Z at the impedance 221 section.
, Therefore, the pnp transistor Q3 is cut off or only a small amount of current flows through it.

かかる状態でのトランジスタＱ、のコレクタ電圧■、は
殆んど電源電圧ｖＥＥに近（、その差（■２−■Ｆ、Ｅ
）は■ＢＥ以下程度となる。この結果、駆動回路のトラ
ンジスタＱ４１〜Ｑ４ｎはカットオフか又は僅かにオン
するのみであるから電流■　１〜■１ｎは殆んど流れな
いものとなる。In such a state, the collector voltage (■) of the transistor Q is almost close to the power supply voltage vEE (and the difference (■2 - ■F, E
) will be less than ■BE. As a result, the transistors Q41 to Q4n of the drive circuit are cut off or only slightly turned on, so that almost no currents 1 to 1n flow.

】 （２）■・　が低レベル”Ｌ“のとき。] (2) When ■・ is at the low level "L".

ｎ 入力信号■・　がｎ　Ｌ　＋＋になると、カレントスイ
ｎ ノチを流れる電流１はインピーダンス２．．２゜の双方
に流れる。このため、トランジスタＱ、のコレクタの電
位Ｖｌは次式（１）となる。When the n input signal becomes n L ++, the current 1 flowing through the current switch n has an impedance of 2. ．． Flows to both sides of 2°. Therefore, the potential Vl of the collector of the transistor Q is expressed by the following equation (1).

Ｖ、　＝Ｉ　−（Ｚ、　＋Ｚ、　）　　　　　　　−＝
−（ｌｉこのとき、次式（２）の関係が成り立つように
インピーダンス２．−、−２．を設定する。V, =I −(Z, +Z, ) −=
-(li) At this time, impedances 2.- and -2. are set so that the following equation (2) holds.

Ｖ、＝Ｉ・（Ｚｌ　＋Ｚ、　）≧■ＢＥ　（Ｑｓ　）　
＋Ｚ３・Ｉ３・・・・・・・・・（２） この結果、ｐｎｐトランジスタＱ、はオン状態となり寛
流工、を流すものとなり、ダイオードＤＩ。V, = I・(Zl +Z, )≧■BE (Qs)
+Z3・I3 (2) As a result, the pnp transistor Q is turned on and current flows through the diode DI.

Ｄ、に電流が流れる。したがって、ｐｎｐトランジスタ
Ｑ、のコレクタ点の電位Ｖ、は２■Ｂ３の値になる。こ
のような電位のＶ、によって駆動回路の駆動トランジス
タＱ４．〜Ｑ４ｎはオンとなり、負荷Ｚ６１−Ｚ６ｎに
次式（３）のような電流を流ず。A current flows through D. Therefore, the potential V at the collector point of the pnp transistor Q has a value of 2.times.B3. With such a potential V, the drive transistor Q4. of the drive circuit. ~Q4n is turned on, and no current flows through the loads Z61-Z6n as shown in the following equation (3).

上記電流１□１〜■１ｎによって負荷Ｚ６．〜Ｚ６ｎが
駆動される。The load Z6. ~Z6n is driven.

上記のような本発明によれば、入力パルス゛Ｈ”レベル
のときは殆んど負荷に電流を流さず、入力パルス“ｌ　
１ｊ、　Ｉ＋レベルのときに負荷に電流を供給すること
ができるバ、Ｊｌ・スミ流源が得られる。According to the present invention as described above, when the input pulse is at the "H" level, almost no current flows through the load, and the input pulse "L"
1j, a current source capable of supplying current to the load at the I+ level is obtained.

また、本発明は力Ｌ／ントスイノチを用いるとともに、
インピーダンスＺ、を接地端子側に設けるＪ−どに、上
り常にｐｎｐ　トランジスタＱ１．のベースに僅かのバ
・イアスを与えておき、オン動作を迅速にづ゛るように
１−であるから回路全体どして高速動作が期待できる。In addition, the present invention uses force L/tosuinochi, and
Impedance Z is provided on the ground terminal side of J-, and a pnp transistor Q1. A slight bias is applied to the base of the transistor, and it is set to 1- so that the on-state is quickly turned on, so that the entire circuit can be expected to operate at high speed.

回路構成が簡単であるということも高速動作に寄与する
ことになるが、それに加郊て集積度の向上二が図れる。A simple circuit configuration also contributes to high-speed operation, but it also allows for an improvement in the degree of integration.

さらに、ｐ　ｎ　ｐ　ｈランジスタＱ、のコレクタに設
けられたダイオードＩ）、、Ｄ２は定電圧特性を有１−
るため、入力端子■ｉ　ｎのバラツキ、又はインピ・−
ダンスＺ２のバラツキに基づ＜　ｉｆＪ　Ｉ　ｓのバラ
ツキに影響されない駆動電流１１〜工１ｎが得もれるも
のとなる。したがって、小振幅の入カパルスでも十分に
複数の負荷を駆動することができるものとなる。さらに
また、回路構成が簡単であることより誤動作のおそれが
なく、安定動作が期待できる。Furthermore, the diodes I), D2 provided in the collector of the p n p h transistor Q have constant voltage characteristics.
Therefore, variations in the input terminal ■i n or impedance -
Based on the variation in the dance Z2, drive currents 11 to 1n that are not affected by the variation in <ifJ Is can be obtained. Therefore, even input pulses of small amplitude can sufficiently drive a plurality of loads. Furthermore, since the circuit configuration is simple, there is no risk of malfunction, and stable operation can be expected.

本発明は上記実施例に限定されず種々の変形を用いるこ
とができる。The present invention is not limited to the above embodiments, and various modifications can be made.

例えば、上記実施例ではパルス信号を印加する回路とし
てカレントスイッチを用いたが、これに限らず、他のス
イッチング回路を用いてもよい。For example, in the above embodiment, a current switch is used as a circuit for applying a pulse signal, but the present invention is not limited to this, and other switching circuits may be used.

まブこ、ｐｎｐ　トランジスタＱ、のインピーダンス手
段ｚ４は上記実施例のように２つのダイオードによって
構成されたものに限らず、第４図のようにｎ　ｐ　ｎ　
）−ランジスタＱ、と２つの抵抗ＲＩ。The impedance means z4 of the Mabuko pnp transistor Q is not limited to the one constructed of two diodes as in the above embodiment, but is also composed of n p n as shown in FIG.
) - transistor Q, and two resistors RI.

Ｒ７によって構成してもよく、また、第５図のようにダ
イオードＤ３とツェナーダイオードＤ２を直列接続した
ものを用いてもよい。前者（第４図）の場合は゛、抵抗
Ｒ，，Ｒ，の値を自由に選ぶことによって出力電圧を変
化させることができ、後者（第５図）の場合は低い電圧
を得ることができるという利点をそれぞれ有する。The diode D3 and the Zener diode D2 may be connected in series as shown in FIG. 5. In the former case (Fig. 4), the output voltage can be changed by freely selecting the values of the resistors R,, R, and in the latter case (Fig. 5), a low voltage can be obtained. Each has its own advantages.

さらに、上記実施例では、入力信号■ｉｎに対して逆相
の出力電圧■２を得るものとしたが、これに限らず、カ
レントスイッチを構成するトランジスタＱ、にパルス信
号を印加し、他方のトランジスタＱ２に基準電圧■ＢＢ
を印加すれば、入力信号に対し７で正相の出力゛電圧を
得ることができる。Furthermore, in the above embodiment, the output voltage ■2 having the opposite phase with respect to the input signal ■in is obtained, but the present invention is not limited to this, and a pulse signal is applied to the transistor Q constituting the current switch, and the other Reference voltage ■BB to transistor Q2
By applying , it is possible to obtain an output voltage with a positive phase of 7 with respect to the input signal.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のバフＬス電流源の一例を示１′回路図、
第２図一本発明のパルス電流源の一例を示す［１図、第
３図はその動作説明のためのタイミングチャー　ト、第
４図及び第５図は本発明の他の例の一部をポず回路図で
ある。 １・・・入力端子、２・・・電源端子、３・トランジス
タ、４−・インピーダンス、５・抵抗、Ｑ１〜Ｑｓ　。 Ｑ４１〜Ｑ、Ｑ、、Ｑ８・・・トランジスタ、Ｒ，、Ｒ
２ｎ ・抵抗、Ｚ、〜Ｚ４．Ｚ、１〜Ｚ５ｎ、Ｚ６．〜Ｚ６ｎ
・・インビ・−タ゛ンス、１）、、Ｄ２山ダイオード、
Ｄ２　・・ツェナーダイオ−ド。 η９１　図 ］−−］−−ｒ　、−、ｉ 第　　３　　図 一゛−１・ 第　　４　　図　　　　　　第　　５　　図「　１−−
−。 −１ 丈・　　　７゛１ １　１、−□ ７１″、３　　　　“ｙ”′ｔ′−＝Figure 1 shows an example of a conventional buff current source.
Figure 2 shows an example of the pulse current source of the present invention [Figures 1 and 3 are timing charts for explaining its operation, and Figures 4 and 5 show some of the other examples of the present invention. It is a Pozu circuit diagram. 1. Input terminal, 2. Power supply terminal, 3. Transistor, 4. Impedance, 5. Resistance, Q1 to Qs. Q41~Q,Q,,Q8...transistor,R,,R
2n ・Resistance, Z, ~Z4. Z, 1 to Z5n, Z6. ~Z6n
...invitence, 1), D2 mountain diode,
D2...Zener diode. η91 Figure]--]--r,-,i 3rd figure 1-1, 4th figure 5th figure 1--
−. -1 length・7゛1 1 1, -□ 71'', 3 "y"'t'-=

Claims (1)

【特許請求の範囲】[Claims] １、　−ｊｊの出力端子が共通接続され定電流手段を介
し、−〇第一・の電源端子に接続された第１および第２
のトランジスタよりなり、前記第１σ−）トランジスタ
の他方の出力端子は第１のインピーダンス手段を介１〜
て第２の電源端子に接続され、前記第２のトランジスタ
の他方の出力端子には第２のインピーダンス手段の第１
の端子が接続され、第２のインピーダンス手段の第２の
端子は上記第１のインピーダンス手段を介して上記第２
の電源端子に接続されてなることを特徴とする差動回路
。1, the output terminals of -jj are commonly connected and the first and second
The other output terminal of the first σ-) transistor is connected to the transistor 1 to 1 through the first impedance means.
and the other output terminal of the second transistor is connected to the first power supply terminal of the second impedance means.
The second terminal of the second impedance means is connected to the second terminal of the second impedance means via the first impedance means.
A differential circuit characterized in that it is connected to the power supply terminal of.
JP59007149A 1984-01-20 1984-01-20 Differential circuit Pending JPS59146226A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59007149A JPS59146226A (en) 1984-01-20 1984-01-20 Differential circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59007149A JPS59146226A (en) 1984-01-20 1984-01-20 Differential circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP52044462A Division JPS606039B2 (en) 1977-04-20 1977-04-20 pulsed current source

Publications (1)

Publication Number Publication Date
JPS59146226A true JPS59146226A (en) 1984-08-22

Family

ID=11658011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59007149A Pending JPS59146226A (en) 1984-01-20 1984-01-20 Differential circuit

Country Status (1)

Country Link
JP (1) JPS59146226A (en)

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