JP3262869B2 - Image coding method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary image encoding method and apparatus, and more particularly to a binary image encoding method and apparatus suitable for a still image filling apparatus and the like.

[0002]

2. Description of the Related Art In a facsimile apparatus which is a typical example of a conventional still image communication apparatus, a binary image is encoded using an MH method, an MR method, or the like. In these encoding methods, it is necessary to transmit all of the image data in order to grasp the entire image. For this reason, it has been difficult to apply the image database service, the video technique, and the like to an image database service that requires quick image judgment.

[0003] Therefore, in these apparatuses, a method different from the encoding method employed in the facsimile apparatus has been used. That is, in transmitting one image, a sequential reproduction method has been proposed in which rough image information is first transmitted, additional information is transmitted thereafter, and a detailed image is gradually generated. An encoding method for achieving this is a hierarchical encoding method. In many cases, a reduced version of the original image is used as the rough information, and a hierarchy is formed by repeating this reduction process several times.

[0004] For example, when a reduction process of 1/2 in length and width is repeated, an image having an area of 1/4 and 1/16 is generated. Therefore, first, a small 1/16 size image is encoded and sent first, and then additional information for generating a 1/4 size image is encoded and sent, and finally, an original image is generated. This is a method of sending additional information. In the above method, reducing the additional information for creating a high-resolution image from a low-resolution image as much as possible has a great effect on shortening the transmission time. Therefore, where the prediction can be roughly made from a small-sized image, a number of pre-coding processes that are excluded from the coding target are considered.

In this case, the unambiguous prediction process (DP) is also an effective means of the pre-coding process. In this method, when there is a rule determined in an image reduction method, the rule is inferred from the rule and the image is reduced from the reduced pixel (low-resolution image data) and the pixels surrounding the coded pixel (high-resolution image data). ON of coded pixel
Those that can predict / OFF are extracted in advance. Then, at the time of encoding, if the encoded pixel can be uniquely determined, this pixel is excluded from the encoding target pixel.

Further, at the time of decoding, a method is used in which ON / OFF of a decoding target pixel is uniquely determined from already decoded low-resolution pixel data and high-resolution pixel data.

[0007]

However, in the conventional unambiguous prediction processing method, as shown in FIG. 16, first, in step S1000, the reduction processing is performed on all the images, and all the reduced images are temporarily stored in the frame memory. After that, an unambiguous prediction (DP) was made in step S1001.
For this reason, there is a problem in that the processing time is increased and the scale of the hardware is increased because a memory for storing the reduced image is required.

[0008]

SUMMARY OF THE INVENTION The present invention has been made for the purpose of solving the above-mentioned problems, and the following structure can be provided as one means for solving the above-mentioned problems. That is, the apparatus according to the present invention provides a code for hierarchically encoding image information.
An encoding device for encoding a plurality of continuous lines of pixels to be encoded
Input method for inputting the original encoded image data including
Stage and the original coded image input by the input means
Reducing the original encoded image data based on the
Reducing means for forming small image data;
In parallel with the formation of the reduced image data,
Image data and image data of peripheral pixels formed by
The encoding target image data inputted from the
Determining means for determining whether the state of the data can be uniquely predicted
And the encoding target based on the determination result of the determination unit.
Encoding means for encoding image data;
The encoding means comprises an unambiguous prediction among the encoding target image data.
Characteristically excludes possible image data from encoding
And Further, the method according to the present invention includes the steps of:
A coding method for encoding, in which a plurality of
Based on the original encoded image data of the continuous line
Reduced image data to form reduced image data,
In parallel with the formation of the reduced image data,
Reduced image data with the state formed and image data of peripheral pixels
Data to determine whether they can be uniquely predicted, based on the results of the determination.
And encodes the image data according to the
It is characterized by being excluded from encoding targets.

[0009]

In the above arrangement, the processing speed can be improved and the hardware scale can be reduced.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing the basic principle of a coding apparatus for performing hierarchical coding according to the present embodiment. FIG.
In the original image data I ₁ is input to the reduction processing unit a101, 1/2 is reduction processing to the size reduced image I ₂ is generated. Reduced image I ₂ is input to the reduction processing unit b 102, the reduced image I ₃ are further reduction processing to 1/2 size
Is generated. This reduced image I ₃ has a size of 1/16 of the data amount of the original image. These reduced images are further encoded and compressed by encoders a to c (103 to 105), respectively, and encoded outputs C ₁ , C ₂ , C
Output as ₃ . For this reason, compared with the case where the original picture is sent as it is, the transmission of the data amount is very small.

That is, the reduced image I ₃ is encoded by the encoder 103 to generate encoded data C ₃ . By transmitting the code data C ₃ first decodes the code of the code data C ₃ is the receiving side, the image size is small it is possible to know the outline of the transmission image. Also, encoder b
At 104, the reduced image I ₂ is referred to while referring to the reduced image I _3.
The encoding, and outputs the code data C _2. Encoder c10
In 5, the original image I ₁ with reference to the reduced image I ₂ is coded, and outputs the code data C _1.

FIG. 2 is a block diagram showing the basic principle of the decoding apparatus according to the present embodiment for decoding hierarchically encoded data.
Code data C ₃ is the decoding processing at the decoder a201, decoded image data I ₃ 'is temporarily frame - are frame memory a204 to storage. The decoded image I ₃ ′ read from the frame memory a 204 has a required size (for example, 4
) And is stored in the video memory 210 through the selector 209.

The image data stored in the video memory 210 is displayed on a monitor 211. The selector 209 switches the display image size, and selects and outputs one of the input data by switching from a controller (not shown). The code data C ₂ is output from the decoder b
Decryption processing is performed at 202. At this time, the decoded image data I ₃ ′ is added to the prediction reference. The decoded image I ₂ ′ is temporarily stored in the frame memory b206. Frame memory b
The decoded image I ₂ ′ read from 206 is input to the interpolator b2
At 08, interpolation processing is performed to a required size (for example, 2 times), and stored in the video memory 210 through the selector 209.

The code data C ₃ is decoded by the decoder c 203. At this time, the decoded image data I
Add ₂ '. The decoded image I ₁ ′ is stored in the frame memory c2.
06 is stored. The image I ₁ ′ read from the frame memory c 206 is stored in the video memory 210 through the selector 209. Since the decoded image I ₁ ′ is exactly the same as the original image, it is possible to make a hard copy from the printer 212.

FIG. 3 shows a detailed configuration of the encoder shown in FIG. The encoder of the present embodiment shown in FIG.
This is an encoder that performs unambiguous prediction continuously without a memory. 3, reference numeral 110 denotes a reduction processing unit, 111 denotes an unambiguous prediction unit, 112 denotes a prediction encoding unit, 113 denotes an input pixel line buffer N, 114 denotes a reduction line buffer M,
Reference numeral 15 denotes a timing adjustment circuit.

The input image data In is first input to an input pixel line buffer N113, and a reference pixel output from the input pixel line buffer N113 is input to a predictive coding unit 112.
And output to the reduced line buffer M114. Therefore, the surrounding pixels of the coded pixel data In are also stored in the input pixel line buffer N113. The reduction result of the reduction processing unit 110 is a reduction line buffer M114.
Is stored in Therefore, the reduced line buffer M114
Stores several line data of reduced pixel data I (n + 1). And the reduced line buffer M114
, The reference pixel data is output to the reduction processing unit 110, the unambiguous prediction unit 111, and the prediction encoding unit 112.

FIG. 4 shows the reduction processing in the reduction processing section 110.
This will be described with reference to FIG. In FIG. 4, pixels a, b, c, d, e, f, g, h, and i shown by squares represent high-resolution pixels, and pixels A, B, and C shown by circles have already been reduced. Represents a pixel. Pixel? Represents a pixel for which ON / OFF of the pixel is to be determined by the reduction processing of the present embodiment.

In the reduction processing section 110 of the present embodiment,
Pixel? Is determined with reference to the surrounding reduced pixels and high resolution pixels to prevent the thin lines from disappearing in the reduced image and to maintain the image quality of the reduced image in consideration of preserving the density. Decide the rules, put them in the look-up table, and refer to this look-up table? Determine the pixel.

FIG. 5 shows an example of the unambiguous prediction (DP) in the unambiguous prediction unit 111. In FIG. 5, pixels a, b, c, d, e, f, g, h, and i shown by squares represent high-resolution pixels, and pixels A, B, C, and D shown by circles represent reduction processing. Pixels that have already been reduced by the unit 110 are shown. In FIG. 5, D is ON / O in the reduction processing unit 110.
The pixel shown in FIG. 4 where the FF is determined? It corresponds to.

The DP value indicates whether a unique prediction can be made or not.
In this embodiment, when unambiguous prediction can be performed, the predictable pixel is excluded from the pixels to be encoded. The DP value of pixel “e” is pixel A,
B, C, D and pixels a, b, c, d.

The DP value of the pixel "f" is represented by pixels A, B, C, D
And pixels a, b, c, d, and e. The DP value of the pixel “h” is determined by pixels A, B, C, D and pixels a, b,
It is determined by c, d, e, f, and g. D of pixel “i”
The P value is calculated for pixels A, B, C, D and pixels a, b, c, d,
It is determined by e, f, g, h.

On the decoding side, when it can be further performed, whether it is white or black is indicated by one bit, and the result is used as decoded pixel data. A process of encoding an input image and determining a DP value according to the present embodiment having the above configuration will be described below with reference to a flowchart of FIG. In step S1, the reduction processing unit 110 first reads three low-resolution pixels that have already been reduced. However, it is all white at the beginning of the processing. Then, in step S2, 9 high-resolution pixels are read. Similarly, the whole of the processing is completely white at the beginning. Then, in step S3, the above 9
One reduced pixel is determined from + 3 = 12 pixels.

Subsequently, the DP values of the pixels "e" to "i" are determined in steps S4 to S7. That is, step S
4, the DP value of the pixel "e" is determined, the DP value of the pixel "f" is determined in step S5, the DP value of the pixel "h" is determined in step S6, and the pixel "i" is determined in step S7.
Is determined. When this process ends, the next predictive coding unit 112 performs a predictive coding process.

FIG. 7 is a detailed block diagram of the predictive encoding unit shown in FIG. 7, reference numeral 120 denotes the predicted state memory 12
2 of the initialization circuit of the prediction state memory 122.
The NDEX and MPS storage areas are initialized to “0”. 12
Reference numeral 1 denotes a predictor for determining a prediction state. Surrounding pixel data 1020 from a line buffer is input to the predictor 121, and a prediction signal 1021 and a coded symbol Xn (1
022) is output. The prediction signal 1021 is sent to and stored in the prediction state memory 122. Predicted state memory 1
22 outputs the INDEX 1023 indicating the prediction state and the dominant symbol MPS (1024) corresponding to the index.

The prediction signal 1021 is an arithmetic parameter RO
The arithmetic parameter ROM 123 outputs a probability (probability of misprediction) P (1025) of the inferior symbol corresponding to the index. P (102
5), the dominant symbol MPS (1024) and the coded symbol Xn (1022) are input to an arithmetic encoder 124 that dynamically performs arithmetic coding, and the arithmetic encoder 124 performs coding.

In the UPDATE unit 125, the MPS (1024) from the prediction state memory 122 and the arithmetic encoder 1
24, the match / mismatch signal YN (10
32), the dominant symbol M corresponding to the index
Update PS value, update MPS (1028) and Inde
x (1029) is output. The LS 1031 input to the arithmetic encoder 124 is a signal indicating the last bit of the encoded signal, and is supplied to the arithmetic encoder 124 from a controller (not shown). Further, NS1027 from the arithmetic encoder 124 is a request signal for the next encoded symbol, and is also supplied to the predictor 121. Cn1026 is arithmetic code data encoded by the arithmetic encoder 124.

FIG. 8 shows a detailed configuration of the arithmetic encoder 124 shown in FIG. 8, 130 is a multiplier, 131 is a subtractor, 132 is a selector, 133 is a latch, 134 is a comparator, 135 is a multiplier, 136 is a sign output unit, and 137
Is an adder, and 138 is an EXOR circuit. The arithmetic coding method of the present embodiment having the above configuration will be described below with reference to the flowcharts of FIGS.

FIG. 9 is a flowchart showing the overall control of the encoding process in this embodiment, FIG. 10 is a flowchart showing the initialization control of the encoder, FIG. 11 is a flowchart showing the encoding control, and FIG. FIG. 13 is a flowchart showing byte output control, FIG. 14 is a flowchart showing output control, and FIG.
Is a flowchart showing final code output (FLUSH) control.

First, the overall control of the encoding process in this embodiment will be described with reference to FIG. In the encoding process, first, in step S51, an initialization subroutine shown in FIG. 10 for initializing the encoder is executed. Then, in step S52, the encoded symbol Xn is read, and an encoding control subroutine shown in FIG. 11 described later in step S53 is executed.

Next, in step S54, it is determined whether or not the processing pixel is the last pixel. If it is not the last pixel, step S52
Returning to step S55, if it is the last pixel, the process proceeds to step S55. In step S55, a final process control subroutine shown in FIG. 15 to be described later is executed, and the process ends. Hereinafter, the details of each of the above-described subroutines will be described.

In the initialization control subroutine shown in FIG. 10, in step S61, for example, the latch C133 through which the signal C1033 passes is set to "0", and the buffer B and the counter SC, which are the internal registers of the byte output 136, are set to "0". Each is initialized, and for example, the signal A10
The latch A 133 through which the 32 passes through is set to “FFFF”, and the flag STF which is an internal register of the byte output 136 is output.
LG is set (# 0), the counter CT is initialized to "11", and the routine returns.

FIG. 11 is a flowchart showing an example of the encoding control subroutine. 11, at step S71, the above-mentioned superior symbol MPS and index INDEX are read from the prediction state memory 122 shown in FIG. 7, and the above-mentioned inferior symbol P is determined from the read INDEX. Then, in step S72, the register A1 is updated by the multiplier 130 (A1.
31 to update the register A0 (A0 ← A-A1). Then, in step S73, Xn and MPS are compared. This is performed using EXOR 138. Then, when Xn = MPS (that is, when the predictions match)
Goes to step S74.

At step S74, the register A is updated (A ← A0), and at the next step S75, the most significant bit (hereinafter, referred to as "MSB") of the register A is determined. If MSB = "0", the process proceeds to step S76, where M
If SB = "1", the encoding control subroutine ends, and the process returns to the main routine. On the other hand, when the process proceeds to step S76 with MSB = "0", INDEX is changed to NMPS.
Update according to the table, and proceed to step S85.

On the other hand, if the prediction is incorrect in step S73 (Xn ≠ MPS), the process proceeds to step S81, where the adder 1
Update of the latch C (C ← C + A0) and update of the latch A (A ← A1) by 37 are executed, and in step S82,
The switch SWITCH corresponding to INDEX is determined. If SWITCH = "0", step S
Proceed to 84.

If SWITCH = "1", the flow advances to step S83 to invert the MPS (MPS ← 1-MP
After S), the process proceeds to step S84. Note that these S
The WITCH process is performed by UPDATE 125. Subsequently, in the present embodiment, INDEX in step S84.
Is updated according to the NLPS table, and then step S8 is performed.
Go to 5. In step S85, a RENORME control subroutine shown in FIG. 12 to be described later is executed. This ends the encoding control subroutine and returns to the main routine.

FIG. 12 is a diagram showing the renorme control (RENOR control).
(ME) is a flowchart showing an example of a subroutine. In FIG. 12, first, the MSB of the latch A is determined in step S91, and if MSB = "0", step S91 is executed.
92, and if MSB = "1", RENO
The RME control subroutine ends, and the process returns to the encoding control subroutine.

When the process proceeds to step S92 with MSB = "0", the latch 135 updates the latches A and C by shifting them to the left, and decrements and updates the counter CT. In the following step S93, the counter C
Determine the value of T. Here, when CT = 0, the process proceeds to step S94, and when CT ≠ 0, the process returns to step S91.

If CT = 0, step S94
After executing the byte output control subroutine shown in FIG. 13 which will be described later, the flow returns to step S91. That is, in this embodiment, in the RENOMEME control subroutine, the latches A and C are shifted to the left and the counter CT is decremented until the MSB of the latch A becomes "1".

The byte output control subroutine of FIG.
Mainly executed by the byte output unit 136, the register te
mp and the like are included in the byte output unit 136. First, in step S401, for example, a result obtained by logically ANDing a value obtained by shifting the value of the latch C to the right by 19 bits and “1FF” is obtained.
The value is stored in the register temp. That is, the register te
mp is, for example, bits 19 to 27 of the latch C
Up to 9 bits are stored.

Subsequently, at step S402, the register te
Determine the value of mp. If temp> “FF”, the process proceeds to step S403, and if temp ≦ “FF”, the process proceeds to step S410. For example, if the carry of the bit 27 has been set (temp> FF), the process proceeds to step S403, and an output (output) subroutine shown in FIG. 14 described later is used as an argument with a value obtained by adding 1 to the value of the register BUFFER. Execute Subsequently, in step S404, the counter S, which is an internal register for byte output, is output.
Determine the value of C. If SC> 0, step S40
Proceed to 5 to decrement the counter SC. Subsequently, in step S406, an output control subroutine is executed using, for example, "00" as an argument, and the process returns to step S404. That is, in the present embodiment, steps S404 to S406 are repeated until the counter SC reaches 0.

Then, the counter SC becomes "0" and SC
If it is not> 0, the process proceeds to step S421. For example, if the carrier of the bit 27 is not set (temp ≦ “FF”), the step S
From step 402, the process proceeds to step S410, where the register temp
It is determined whether or not “FF”. And, for example, tem
If p = "FF", the counter S is set in step S411.
After incrementing C, the process proceeds to step S422.

On the other hand, in step S410, temp <“F
F ", the process proceeds to step S412 and the register BU
The output control subroutine is executed using the value of FFER as an argument. Subsequently, in step S413, it is determined whether or not the value of the counter SC is SC> 0. If SC> 0, the process proceeds to step S414, and if SC = 0, the process proceeds to step S421.

If SC> 0, the present embodiment performs step S
At step 414, the counter SC is decremented, and at step S4
At 15, the "output" subroutine is executed with "FF" as an argument, for example, and the process returns to step S413. That is, in the present embodiment, steps S413 to S415 are repeated until the counter SC reaches 0. In step S421, for example, the value of the register temp and “F
The result of the logical AND of F "is stored in the register BUFFER. That is, for example, the lower 8 bits of the register temp are stored as the register BUFFER. Then, in step S422, for example, the value of the latch C and the value of" 7F "are stored.
By storing the result of logical AND of FFF "in the latch C, the bit of the output latch C is cleared, and, for example, the counter CT is set to 8, and then the byte output control subroutine is terminated. Return to routine.

FIG. 14 is a flowchart showing an example of the output control subroutine. In FIG. 14, in the present embodiment, the flag STFLG is determined in step S431.
If STFLG = "0", step S4
The program proceeds to step 33, where the data given as the argument is output, and thereafter the output control subroutine ends and returns.

Also, in step S431, the STFLG @
If it is "0", the flow advances to step S432, and STFLG
After "=", the output control subroutine ends and the routine returns. This is to invalidate the initial value of the latch C included in the first "output" process, and to output data given as an argument from the second time on. FIG.
Numeral 5 is a flowchart showing an example of a final code output control subroutine. This subroutine is a routine for performing a final output of the code remaining on the latch C.

In FIG. 15, first, in step S501,
Then, for example, the operation result (C + A-1) and "FFFF00
00 "is stored in the register temp. That is, the register temp stores, for example, the upper 16 bits of the operation result (C + A-1). In the next step S502, the value of the register temp and the latch C are stored. Then, if temp <C, the flow advances to step S507 to update the latch C (C ← temp + “8”).
000 ") and the process proceeds to step S505.

On the other hand, if temp ≧ C in step S502, the flow advances to step S504 to update the latch C (C
<← temp) and the process proceeds to step S505. Step S
At 505, the latch C is shifted to the left by the value of the counter CT, and the value of the counter C is determined at the following step S506. If the counter C is greater than "7FFFFFF", the flow advances to step S507 to execute the output control subroutine shown in FIG. 14 using the value obtained by adding 1 to the value of the register BUFFER as an argument.

Subsequently, the counter SC is set at step S508.
Is determined. If SC = 0, step S
Proceed to 515. On the other hand, if SC> 0 in step S508, the flow advances to step S509 to decrement the counter SC. Subsequently, in step S510, for example, "0"
After executing the output control subroutine with 0 ”as an argument,
It returns to step S508. That is, in the present embodiment, steps S508 to S510 are repeated until the counter SC reaches 0.

On the other hand, in step S506, C ≦ “7FFFF”
In the case of "FF", the process proceeds to step S511,
The output control subroutine is executed using the value of UFFER as an argument. Subsequently, in step S512, the value of the counter SC is determined. If SC> 0, the flow advances to step S513 to decrement the counter SC. Subsequently, in step S514, an output control subroutine is executed using, for example, "FF" as an argument, and the flow returns to step S512. That is, in the present embodiment, steps S512 to S514 are repeated until the counter SC reaches 0.

On the other hand, if SC = 0 in step S511, the flow advances to step S515. In step S515,
For example, 8 from bit 19 to bit 26 of latch C
The output control subroutine is executed using the bit as an argument. Then, in step S516, an output control subroutine is executed using the eight bits from bit 11 to bit 18 of the latch C as arguments. Then, the final code output control subroutine ends and the process returns.

[0051]

Other Embodiments In the above description, an example has been described in which the present invention is achieved by software using a flow chart. However, the present invention can also be implemented by dedicated hardware. The present invention may be applied to a system including a plurality of devices or to an apparatus including a single device. Needless to say, the present invention can be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus.

[0052]

As described above, according to the present invention, the processing speed can be improved and the hardware scale can be reduced. Also,
In particular, image data that can be uniquely predicted
By excluding image data from encoding,
Rate can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic principle of a coding apparatus for performing hierarchical coding according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a basic principle of a decoding device for decoding hierarchically encoded data in the embodiment.

FIG. 3 is a block diagram showing a detailed configuration of the encoder shown in FIG.

FIG. 4 is a diagram for explaining a reduction process in a reduction processing unit shown in FIG. 3;

FIG. 5 is a diagram for explaining a unique prediction (DP) in a unique prediction unit shown in FIG. 3;

FIG. 6 is a flowchart illustrating a process of encoding an input image and determining a DP value according to the embodiment;

FIG. 7 is a detailed block diagram of the prediction encoding unit in FIG. 3;

FIG. 8 is a diagram showing a detailed configuration of the arithmetic encoder shown in FIG. 7;

FIG. 9 is a flowchart showing overall control of an encoding process in the embodiment.

FIG. 10 is a flowchart illustrating initialization control of an encoder according to the present embodiment.

FIG. 11 is a flowchart illustrating encoding control in the present embodiment.

FIG. 12 is a flowchart illustrating RENOMEME control in the present embodiment.

FIG. 13 is a flowchart showing byte output control in the embodiment.

FIG. 14 is a flowchart showing output control in the present embodiment.

FIG. 15 is a flowchart showing final code output (FLUSH) control.

FIG. 16 is a diagram showing a conventional unambiguous prediction process.

[Explanation of symbols]

 Reference Signs List 100 Reduction processing unit 101 Encoder 102 Decoder 103 Frame memory 104 Interpolator 110 Reduction processing unit 111 Unique prediction unit 112 Prediction encoding unit 113 Input pixel line buffer N 114 Reduction line buffer M 115 Timing adjustment circuit 120 Initialization circuit 121 prediction Unit 122 Prediction state memory 123 Arithmetic parameter ROM 124 Arithmetic encoder 125 UPDATE unit 130 Multiplier 131 Subtractor 132 Selector 133 Latch 134 Comparator 135 Multiplier 136 Code output unit 137 Adder 138 EXOR circuit 209 Selector 210 Video memory 211 Video memory 212 Printer

Claims (14)

(57) [Claims] An encoding apparatus for hierarchically encoding image information, comprising: input means for inputting, for each line, original encoded image data including a plurality of continuous lines of pixels to be encoded; Reducing means for reducing the original coded image data based on the obtained original coded image data to form reduced image data; and in parallel with formation of the reduced image data by the reducing means, the reducing means A determining unit that determines whether the state of the encoding target image data input from the input unit is uniquely predictable from the formed reduced image data and the image data of the peripheral pixels, and a determination result of the determining unit. based an encoding means for encoding the encoding target image data, said encoding means, one of said coded image data
An encoding apparatus characterized in that image data that can be uniquely predicted is excluded from encoding targets. 2. The encoding apparatus according to claim 1, wherein said determining means generates data indicating whether or not the state of said encoding target image data can be uniquely predicted. 3. The encoding apparatus according to claim 1, wherein said reduction means forms reduced image data based on a plurality of said original encoded image data and a plurality of reduced image data. . 4. The apparatus according to claim 1, wherein said determining means determines whether or not a plurality of image data related to the predetermined reduced image data can be uniquely predicted. Encoding device. Wherein said encoding means, according to claim 1 to claim 4, characterized in that encode the pixel data is determined uniquely unpredictable states of the coded pixel in said determination means The encoding device according to any one of the above. 6. The apparatus according to claim 1, wherein said encoding means predictively encodes said original encoded image data based on said reduced image data and said original encoded image data. An encoding device according to any one of the above. 7. A system according to claim 1, further comprising delay means for delaying input of the original coded image data from said input means during a time required for said determination means to determine whether or not the state of said image data to be coded can be uniquely predicted. The encoding device according to any one of claims 1 to 6, characterized in that: 8. An encoding method for hierarchically encoding image information, wherein the original encoded image data is reduced based on the original encoded image data of a plurality of continuous lines input for each line, and the reduced image data is reduced. Is formed, and in parallel with the formation of the reduced image data, it is determined whether or not the state of the encoding target pixel can be uniquely predicted from the reduced image data in which the state has been formed and the image data of the peripheral pixels. To encode the image data
A coding method characterized in that pixels that can be uniquely predicted are excluded from coding targets. 9. The encoding method according to claim 8, wherein data representing a determination result as to whether or not the state of the encoding target pixel is uniquely predictable can be generated and output. 10. The method according to claim 8, wherein in forming the reduced data, reduced image data is formed based on a plurality of the original coded image data and a plurality of reduced image data. Encoding method. 11. The method according to claim 1, wherein the determination of the state of the pixel to be encoded includes determining a plurality of image data associated with predetermined reduced image data.
The encoding method according to any one of claims 8 to 10, wherein the determination is made based on whether or not unambiguous prediction is possible. 12. The image data encoding method according to claim 8, wherein only the pixel data for which it is determined that the state of the encoding target pixel cannot be uniquely predicted is encoded. The encoding method according to any one of the above. 13. The image data encoding apparatus according to claim 8, wherein said original encoded image data is predictively encoded based on said reduced image data and said original encoded image data. 13. The encoding method according to any one of 12. 14. A state of the image data to be encoded is defined.
Predictability whether time required for determination, the encoding device according to any one of claims 8 to 13, characterized in that delaying processing for the original encoded image data.