JPH046948A - Binarizing method for color picture - Google Patents

Abstract

PURPOSE:To attain efficient coding by using a binarizing signal through the binarization so that the probability of overlap of components dots is increased. CONSTITUTION:Three color R, G, B 8-bit signals are inputted from a picture reader to a binarizing circuit 10 and a sequence discrimination circuit 11. The circuit 11 discriminates the amplitude of the R, G, B signals and outputs a sequence command signal 106 to the circuit 10. The circuit 10 uses the signal 106 to apply binarization processing to the R, G, B signals in the larger order by the error dispersion method and outputs binarized RGB signals 103-105 to a prediction coder 12. The coder 12 generates a code word 108 by the entropy coding and sends it to a decoder 14. The R, G, B binary data 109-111 decoded by the decoder 14 are stored in a memory 15. Outputs 112-114 of the memory 15 are displayed on a display device 16 to confirm the picture.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image binarization method in an image communication device or an image filing device.

[Conventional technology]

Conventionally, various image data compression methods have been used to shorten data transmission time and reduce data file capacity.

For example, in the field of facsimile, compression techniques such as the Modified Huffman method (MH method), which is an encoding method that uses run lengths of white pixels and black pixels, which are image features, are frequently used.

These compression methods were mainly proposed for efficiently transmitting document images.

However, recently, opportunities to transmit halftone images such as photographs have increased. In the dither method used as a halftone reproduction method, a run of a binarized image is cut into pieces.
The MH code is not suitable for this dithered image.

In addition, the error diffusion method, which is a method of the dither method, disperses the density error caused by binarization to unprocessed peripheral pixels.
Although this is a method of proceeding with value conversion, black dots occur irregularly.

When applying these methods to color images, R1G, B
Since each data is binarized independently, there is a problem that color correlation is lost.

[Problem that the invention is trying to solve]

In this way, when encoding a binarized image for halftone reproduction, runs are fragmented and the efficiency of the MH code cannot be improved. Furthermore, since color correlation cannot be used, there is a problem that encoding efficiency cannot be improved.

[Means to solve the problem]

The present invention has been made in view of the above points, and is a method for binarizing a color signal represented by a plurality of color component signals. It provides a binarization method for color images in which the binarization process is performed in descending order of color component signals and the binarized data of other color components are controlled according to the binarized data of the first color component. The present invention provides a binarization method, and also provides a color image binarization method that performs binarization using an error diffusion method.

〔Example〕

FIG. 1 is a block diagram of a color transmission system to which the present invention is applied.

R (red) and G (green) from an image reading device (not shown)
, B (blue), each of the 8-bit signals is sent to the binarization circuit 10,
It is input to the order determination circuit 11.

The order determining circuit 11 determines the magnitude of RSG and B, and outputs an order instruction signal 106. For the case where the data of R and GSB are equal, for example, R(1), G(
Prioritize items like 2) and B(3).

In the binarization circuit IO, the R, G, and B signals are binarized in descending order of their values by the error diffusion method described later using the signal 106, and binary RGB signals 103 to 105 are output. These signals are input to a predictive encoder 12.

The encoder 12 performs encoding processing using an arithmetic code that is considered to be efficient in entropy encoding, generates a code word 108, and transmits this to the decoder 14.

The decoder 14 performs arithmetic code decoding processing and outputs decoded R, G, and B binary data 109 to 111, which are stored in the bitmap memory 15. Outputs 112 to 114 from the bitmap memory 15 are input to an image display 16, allowing confirmation of the image.

FIG. 2 is a block diagram of the binarization circuit 10.

According to the signal 106 indicating the magnitude of RSG and B, the RGB signals 100 to 102 are processed by the signal exchanger 20 such that the maximum signal is 130,
The second signal is switched to 131 and the minimum signal to 132, and the binarization process is performed in the order of signals 130, 131, and 132.

The signal 130 is corrected by adding the previous binarized error signal E1 in the adder 22. This signal D, 133 is compared with a threshold value T129 by a comparator 25, and a binary signal E, 136 is output, which is ON (1) when D1≧T and OFF (0) otherwise.

The subtracter 32 takes a difference signal E, 139, between the correction signal D1 and the binarized signal B1. However, in the subtraction process, the B1 signal is calculated after level conversion (0→0.1→255).

Similarly, the signal 131 is corrected using the error signal E2 in the adder 23, and the correction signal D2134 is binarized in the comparator 26 to obtain the signal 142. In the AND circuit 28, the signal B
Gate processing is performed such that B2137 becomes 1 only when 1=1 and signal 142=1.

This makes it possible to increase the probability that binary dots overlap.

The subtracter 29, like the subtracter 32, receives the difference signal E214.
0 is calculated.

Similarly, the signal 132 is corrected by adding the error signal E3 in the adder 24, and the correction signal D3135 is binarized in the comparator 27 to obtain the signal 143. In the AND circuit 30, the signal B
Gate processing is performed so that the signal B3 becomes 1 only when 2=1 and the signal 143=1.

This makes it easier for the third color dot to overlap the previous dot.

The respective processed three color signals are rearranged in the exchanger 21 and outputted as R and GSE signals 103 to 105.

In this way, in order to control the 0N10FF of each color component R, G, and B dot during the binarization process, the binarization process is performed in the order of increasing R, G, and B density data, and the dots of colors with large density data are By performing control such that the dots of the other two colors with low density data are not turned on in the place where it is turned off, the secondary colors (R+G=Y (yellow), G+B=C (cyan), B+R=M (magenta) ) has a high probability that the dots will overlap.

Therefore, as a result, the encoded predictions are more likely to match, and the encoding efficiency of predictive encoding is improved.

In other words, in Figure 5, (a
This figure shows typical examples of () side-by-side dot type and (b) overlapping dot type, which in principle show the same color. Table 1 shows the respective coincidence probabilities when predicting a pixel of interest (G in this example) while referring to pixels of other colors (R in this example).

In the case of the dot juxtaposition type, when the pixel of another color is O, the probability that the pixel of interest is 0 is 2/3.1, and the probability is 1/3, and the prediction error occurs with a probability of 1/3.

However, in the case of the dot overlapping type, when the pixels of other colors are 0, the pixel of interest is always 0, and conversely, when the pixels of other colors are 1, the pixel of interest is always 1. In other words, in the case of an overlapping type,
If pixels of other colors are referred to, the predictions will completely match.

Although the explanation has been given above using an extreme example, by having such a rule during general image binarization processing, the predicted matching rate can be improved.

FIG. 4 is an explanatory diagram when the difference signal E' (EI SF3, E3) is diffused to surrounding unprocessed pixels.

That is, 1/3 of the difference signal E' is distributed to the next pixel 50 and the pixel 51 one line ahead, and 1/3 of the difference signal E' is distributed to the next pixel 50 and the pixel 51 one line ahead.
3 indicates that 1/6 of the difference signal E' is distributed. When the cumulative value for each pixel reaches the binarized pixel position, the correction signal E (E, , E2, E3) is generated.
becomes.

FIG. 3 is a block diagram of a circuit for obtaining correction signals E1, E2, E3 from the difference signals E1', 2, E3, which are prepared separately for each of the three colors.

The difference signal E' 120 is divided into a signal 150 processed by 1/3 by the 1/3 processor 33 and a signal 151 processed by 1/6 by the 1/6 processor 38.

Signal 151 is input to latch 34 and adder 40.42. Signal 150 is also input to adders 41.43. The latches 34, 35, 36, and 37 sequentially transfer data using signals synchronized with the binarized pixel clock. Further, the 1-line memory 44 delays 1-line data.

As a result, the output value of the latch 37 becomes the correction signal E121.

FIG. 6 is a block diagram of encoder 12.

Input data 103 to 10 of 1 bit each in RSGSB representing each pixel of a color image inputted from the binarization circuit 10
5 is a parallel/serial converter 60 that converts RGBRGB/
It is converted into a serial signal in the order of... This order is
The order of RGB is not limited as long as the sending and receiving sides match.

The serial signal D203 output from the parallel-to-serial converter 60 is sent to the encoder 61.

On the other hand, the input data 103 to 105 are stored in a line memory 62 having a capacity for a plurality of lines, and are output to the state prediction circuit 63 as an output signal 205 together with information from several lines before.

The state prediction circuit 63 determines the state of each pixel to be coded based on the output signal from the line memory 62, and outputs a state signal 5t206 indicating the coding state.

The encoder 61 generates a code 108 based on the serial signal D203 and the status signal St by encoding using, for example, an arithmetic code, as described later, and transmits it to the decoder 64.

The decoder 64 performs a decoding process on the transmitted code 207 to produce a decoded serial signal D' 208. This signal D' is converted to a serial/parallel converter 65.
Then, R', G', and B' are returned to 1-bit binary color, and color images are displayed and recorded based on this.

FIG. 7 is an explanatory diagram of reference pixels for determining the encoding state St.

FIG. 7(a) shows the reference pixel of the first encoded color (R in this example), and indicates that seven encoded pixels around the encoded pixel shown in cloudy color are referred to. There is.

In addition, FIG. 7(b) shows the encoded second color (G in this example).
This shows that eight pixels are referred to, including the same seven pixels as in (a) and the pixels at the same position of the first color.

Further, FIG. 7(C) shows reference pixels of the third color (B in this example), including the same seven pixels as in FIG. 7(a) and the first color,
This indicates that a total of nine pixels of the second color at the same position are referred to.

Since the binarization method adds processing that causes dots to overlap, the predicted matching rate when referring to pixels of other colors is improved.

FIG. 8 is a block diagram of a circuit for obtaining the reference pixel shown in FIG. 7. Line memory 62 and state prediction circuit 6
3, and this circuit determines the state using the reference pixel position shown in FIG.

RGB signals 103 to 105 are stored in line memories 70, 71.
72 holds data delayed by one line.

Furthermore, the latches 73 to 80 hold data delayed for each pixel clock. The data in R103 is outputted from the latches 73 to 76 and the line memory 70, so that the data of the previous five pixels of the encoded line can be referenced. Further, the outputs of the latches 79 and 80 allow reference to the two encoded pixels of the encoded line.

Together, these become the reference pixel signal 210. Furthermore, the latch 78 outputs R data 211 of the encoded pixel.

The same circuit 84.85 as this latch group 83 is G104, B
105 signals, and similar seven pixel data 212 and 214 are output from these circuits.

Furthermore, the latch 54 outputs G data 213 of the encoded pixel.

The selector 81 switches the reference pixel signal according to the color instruction signal 219.

When the color signal is R, the reference pixel signal 210 and a 2-bit zero signal (not shown) are selected. When G, reference pixel signal 21
2 and R signals 212 and 1 bit of zero signal are selected.

When B, reference pixel signal 214 and R signal 211, G
Signal 213 is selected. The selection signal 215 and color instruction signal 219 are combined in the backing circuit 82 to form a status signal 5t206.

FIG. 9 is a block diagram of the encoder 61.

Before explaining FIG. 9, the arithmetic codes used in this embodiment will be explained.

As is conventionally known, arithmetic coding is a method in which a code is formed by arithmetic operations so that an input signal string becomes a code expressed in binary decimal numbers. This method uses Lang
The document by Don and R15sanen et al.
Reaction of Black/White
Images with Arithmetic Co.
ding, IEEEET r an Com
, COM-29, 6, (1981, 6), etc. According to this document, the encoded input signal string is S, the probability of occurrence of a less common symbol (LPS) is q1, the arithmetic register Augend is A (S), and the code register is C
(S), perform the following arithmetic operations for each input signal.

A(Sl)=A(S)Xq=A(S)X2-Q...
(1) A(So) = <A(S)-A(Sl)>7
...(2) <>1 indicates truncation with 42 significant digits c(so) = c(s)
...(3) C(Sl)=C(S)+A(So)
...(4) Here, if the encoded data is a dominant symbol (MPS: O in the above example), A (So)
, C(So) is used to encode the next data. In addition, in the case of a less powerful symbol (LPS: 1 in the above example), A (S
l), C(Sl) is used to encode the next data.

The new value of A is multiplied by 28 (S is an integer greater than or equal to 0) and 0.
It falls within the range of 5≦A<1.0. This processing corresponds to shifting the calculation register A eight times in hardware. The code register C is also shifted the same number of times, and the shifted out signal becomes the code. The above process is repeated to form a code.

Further, as shown in equation (1), the occurrence probability q of LPS is approximated by a power of 2 (2-Q: Q is a positive integer), thereby replacing the multiplication calculation with a shift calculation. In order to further improve this approximation, q is approximated by a polynomial of a power of 2, such as equation (5). This approximation improves the worst point of efficiency.

q#2-" +2-02...
(5) Furthermore, since the arithmetic code allows the value of Q to be switched for each encoded data, the probability estimator can be separated from the encoding.

In this embodiment, as described above, a dynamic method is used in which the probability is estimated while performing encoding.

A block diagram of the encoder 61 shown in FIG. 9 that performs the above arithmetic coding will be explained.

The state signal 5t206 from the state prediction circuit 63 is input to the counter memory 93 and the encoding condition memory 94.

The encoding condition memory 94 stores, for each state represented by the state signal 5t206, a dominant symbol MP3308, which is a symbol that is likely to appear, and an index l307 indicating the encoding condition including the probability of appearance of LPS of an arithmetic code, which will be described later. has been done. The MPS308 is input to the prediction conversion circuit 97, and the binary code D203 is input to the prediction conversion circuit 97.
A YN signal 301 is generated which becomes 0 when it matches S308. The YN signal 301 is input to the update circuit 95, and the update circuit 95 increments the count of the corresponding state among the count values stored in the counter memory 93 when the YN signal is 0. And counter memory 93
If the count value 0306 stored in the count table ROM 92 matches the set value MC305 from the count table ROM 92, the index 307 is updated in the direction of increasing (in the direction of decreasing the LPS appearance probability q). (The MPS is not inverted.) The count table ROM 92 supplies the update circuit 95 with the number MC305 of MPS shown in Table 2, which is determined corresponding to the index ■ representing the probability of appearance q of the LPS. .

Furthermore, in the update circuit 95, the MPS 308 and the pixel signal D2
03 does not match, that is, Y from the prediction conversion circuit 97
When the N signal is 1, the index 307 is updated in a direction that decreases (in a direction that increases the LPS appearance probability q). Furthermore, when a YN signal with a value of O comes when the index is 1, processing is performed to invert the MPS (0→l or 1-0). The outputs I' 309 and MPS' 310 are the updated index values and are stored again in the encoding condition memory 94.

In the encoding parameter determination circuit 96, the index ■3
Coding parameter Q31 of arithmetic code based on the value of 07
1 is set in the arithmetic encoder 98. This arithmetic encoder 98
Now, the YN signal 301 from the predictive conversion circuit 97 is arithmetic encoded using the parameter Q311 to obtain a code 302.

Note that an initial value is given to the encoding condition memory 94, and I,
By not updating the MPS, static encoding can be easily achieved.

FIG. 10 is a block diagram of the predictive conversion circuit 97.

Binary number D203 and MPS308 are EX-OR circuit 99
A YN signal 301 is output which becomes 0 when the binary code D203 and the MPS 308 match, and becomes 1 when they do not match.

FIG. 11 is a block diagram of the update circuit 95. When the YN signal 301 is 0, the count value C306 from the counter memory 93 is incremented by +1 by the adder 431,
The signal becomes C' 312. This value is compared with MC305 from count table ROM92 in comparator 433,
If the value of C' matches the value of MC, update signal UP
Set A313. Further, the YN signal 301 becomes an update signal UPB 314, and UPA and UPB enter the index change circuit 435. Further, UPA and UPB are logically ORed by an OR circuit 437, and the output signal 315 of the OR circuit 437 becomes a switching signal for the selector 432. When the signal 315 is 1, the selector 432 selects the 0 signal 319 to reset the counter value, and otherwise selects the 0 signal 319.
31 output signal C'312 is selected, and the counter update signal C'312 is selected.
"316, and store this in the counter memory 93."

The index change circuit 435 includes a signal d317 (standardly, d=1) that controls the index update step.
and UPA313. The current index 1307 is input from the UPB 314 and the encoding condition memory 24.

Table 4 is a table showing the index update method in the index change circuit 435 (Table 4 shows cases where the update increments are d=1 and d=2.) Input this table ■1 condition d, The updated index ■' is determined by referring to UPA and UPB. Also, I
When UPB=1 and UPB=1, EX signal 318 is set.

When the EX signal is 1, the inverter 436 outputs the current MPS30.
8 symbols (0→1 or l→0) to obtain the updated MPS′ 310. Also, when the EX signal is O,
MPS' is not changed. The updated I' 309 and MPS' 310 are stored in the encoding condition memory 94, and used as the index (2) and MPS for the next processing. Note that the updating method shown in Table 4 can be configured as a table using a ROM or the like, or it can be configured as a logic using an adder/subtractor.

As described above, when MPSs for the number of MPSs determined according to the value of the index I representing the appearance probability q of an LPS approximated by a polynomial of a power of 2 are generated, d is added to the index I and the arithmetic code is The appearance probability q of the LPS used is made small, and on the other hand, when an LPS occurs,
The index I is subtracted by d to increase the appearance probability q of the LPS used for the arithmetic code. Furthermore, if an LPS occurs in a state where the index I representing the LPS appearance probability q is 0.5 is 1, the MPS is inverted.

In this way, the index I and MP are adaptively applied to the input image.
By updating S, arithmetic coding with high coding efficiency can be achieved.

FIG. 12 is a coding efficiency curve of the arithmetic code used in this embodiment. Hereinafter, the value of index I will be indicated by a lowercase letter i.

This curve is expressed by equation (6) when the LPS appearance probability is the approximate probability q ei at the time of 91 encoding. And L
The index I is sequentially set to 1. 2. It is given as 3゜...

Here, the numerator is entropy, and qei is the value shown by equation (7).

qei=q1+q2...(7
) qIl The value of q2 is a power of 2 polynomial approximation value and is given in Table 5. For example, it is shown by (8) to (io).

q el ""2-'
...(8) qe2=2-Ku-2-4...(9) q e3 ” 2-” + 2-”
...(1o), and the peak point qei at which the efficiency η becomes 1.0 in this probability will be hereinafter referred to as the effective probability. Furthermore, it is clear that the efficiency is improved by calling the intersection of the efficiency curves the boundary probability qbi, and encoding using the effective probabilities adjacent to this probability.

In this embodiment, the effective probability qei shown in Table 5 is selected from the probabilities that can be approximated by two terms as shown in equation (5). Also, Ql, Q2 in Table 5. Q3 is arithmetic encoder 9
Parameter Q sent to 8. It is 311. That is, Ql, Q
2 is the shift amount given to the shift register, and this shift operation is used to calculate the power of 2. Also, Q3
indicates the coefficient of the second term, and switches between + and -.

The MC values in Table 2 are determined as follows.

That is, when the number of LPS is NL and the number of MPS is NM,
The probability of LPS occurrence is given by equation (11).

This equation is solved in NM (and becomes equation (12).

NM=LNL (1/Q 1)J...
(12) However, LXJ represents rounding up to the nearest whole number.

By giving qbi shown in FIG. 12 to q in equation (12), the number of dominant symbols (MPS) there
Mi is calculated. Therefore, MC is calculated from equation (13).

MC1= NMt++ −NMl
... (13) The value of MC in Table 2 is N from equations (11), (12), and (13).
It was calculated assuming t, = 2.

In this way, the number NMi of dominant symbols MPS corresponding to each index I is determined based on each boundary probability qbi as shown in FIG. shall be.

The value of this MC and the number of generated dominant symbols are compared as described above, and if the value of MC and the number of dominant symbols match, the state is suitable for encoding using the neighboring index I. It is determined that index I is changed. As a result, the index I can be changed at a good timing based on the number of dominant symbols generated, and encoding using the optimum index I can be adaptively achieved.

FIG. 13 is a block diagram of arithmetic encoder 98.

Of the control signals Qc311 (Table 5) determined by the code parameter determination circuit 96, shift register A3
Ql to 70, Q2 to shift register B, selector 57
Q3 is input to 2. Ql and Q2 are Augend signals As72 for shift registers A and B, respectively.
Indicates how many bits to shift 3 to the right. The shifted results become output signals 730 and 731.

The signal 731 is complemented by an inverter 576, and the selector 572 selects the signal 731 or the output signal of the inverter 576 using the control signal Q3 to obtain an output signal 732. Adder 573 adds signal 730 from shift register A 370 and signal 732 from selector 572, and outputs ASI signal 724. Subtractor 574
Now, subtract the ASI signal 724 from the AS signal 723,
An Aso signal 725 is obtained. In the selector 575, As.

Either signal 725 or As+ signal 724 as YN signal 3
Select by 01. That is, when the YN signal is O, the ASO signal becomes the A' signal 726, and when the YN signal is 1, the ASI signal becomes the A' signal 726. In the shift circuit 580, the MSB of the A' signal
A process of shifting to the left until becomes 1 is performed, and as a result of this shift, an As' signal 727 is obtained. A shift signal 732 corresponding to the number of shifts is sent to the code register 57.
9, a number of bits corresponding to the number of shifts are output from the code register 579 in order from the MSB to become code data 108.

The code data 108 is processed using a bit processing method (not shown).
The bitl sequence is processed to be within a finite number of bits, and is transmitted to the decoder 64 side.

Further, the contents CR728 of the code register 579 are added to the ASO signal 725 by the adder 577 and input to the selector 78. In addition, the signal CR728 to which the Aso signal 725 is not added also enters the selector 578, and when the YN signal 301 is 0, CR' = CR, and when the YN signal is 1, CR' =
It is output as a CR' signal 729 which is CR+Aso. The shift processing described above regarding code register 579 is performed on the CR' signal.

As explained above, during binarization processing, RSG.

Control the 0N10FF of the B dot to create the secondary color (R+G=
Y (yellow), G+B=C (cyan), B+R=M(
By increasing the probability of dots overlapping in magenta), the encoded pixel predictions are more likely to match, which is effective in improving the encoding efficiency in predictive encoding.

Effects of the Invention As explained above, according to the present invention, in a method for binarizing a color signal represented by a plurality of color component signals, the probability that color component dots overlap is reduced. Since the binarization is performed to increase the number of signals, it is possible to achieve efficient encoding using this binarized signal.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a color transmission system to which the present invention is applied, Figure 2 is a block diagram of a binarization circuit, Figure 3 is a block diagram of an error diffusion circuit, and Figure 4 shows pixel positions for error diffusion. Figure 5 is an explanatory diagram of two representative examples of dot positions expressing yellow (25%), Figure 6 is a block diagram of the predictive encoder, Figure 7 is a diagram showing reference pixels, Figure 8 is a block diagram of the state prediction circuit, FIG. 9 is a block diagram of the encoder, FIG. 10 is a block diagram of the prediction conversion circuit, FIG. 11 is a block diagram of the update circuit, and FIG. 12 is a diagram showing the encoding efficiency curve. FIG. 13 is a block diagram of the arithmetic encoder, in which IO is a binarization circuit, 11 is an order determining circuit, 12 is an encoder, 20 is a signal exchanger, and 25, 26, and 27 are comparators. Torigimi (Shishun inch:'V Rimata Kyousha)

Claims (3)

[Claims] (1) A method for binarizing a color image, which is characterized in that the binarization is performed so that the probability that color component dots overlap is increased in a method for binarizing a color signal represented by a plurality of color component signals. (2) A color image according to claim 1, characterized in that the color component signals are binarized in ascending order, and the binarized data of other color components are controlled in accordance with the binarized data of the first color component. Binarization method. (3) A color image binarization method according to claim 1, characterized in that the binarization is performed using an error diffusion method.