JP2675903B2 - Image coding method - Google Patents

Description

The present invention relates to an image coding system in a color facsimile apparatus or the like for communicating a color image.

[Prior Art] As a conventional image coding method, a run-length coding method typified by G3 and G4 facsimiles recommended by CCITT (International Telegraph and Telephone Consultative Committee) is generally used. This encoding method is a method of counting the length (run length) of a pixel in which white or black continues, and determining a code corresponding to the count value from a code table prepared in advance. The code table used here is characterized by assigning relatively short codes to long white lines that are often found in document images.

On the other hand, recently, development of inexpensive color printers has progressed, and color images, especially 1 bit of red (R), green (G), blue (B) or yellow (Y), cyan (C), magenta (M). Binary color image communication with separate data has been proposed.

As such a binary color encoding method, a method of encoding three colors for each bit plane and using an MH and MR encoding method for black and white is considered.

However, there is a limit in obtaining sufficient compression efficiency for a color image by encoding with the MH and MR encoding methods.

Therefore, a proposal has been made to encode a color image using an encoding method that is predictive encoding instead of MH and MR encoding. According to this, the compression efficiency is improved, and the transmission and storage of a color image having a large amount of data can be efficiently performed.

[Problems to be solved by the invention]

In such predictive coding, the pixel of interest is predicted from a pixel state in the vicinity of the pixel of interest according to a predetermined parameter, and the parameter for prediction is given such that the prediction matching probability becomes high.

However, if the given parameters are not suitable for the image to be coded, the predictive match probability will be low,
The compression efficiency will deteriorate.

[Means for solving the problem]

The present invention has been made in view of the above points, and an object thereof is to achieve predictive coding with high compression efficiency. Specifically, the value of a pixel of interest predicted by a plurality of pixels in the vicinity of the pixel of interest to be encoded and An image encoding method for encoding the coincidence or non-coincidence of the value of a pixel of interest, which is set as a parameter for predicting the value of the pixel of interest, and which is set to have a high prediction probability for a specific image. Provided is an image coding method that includes a parameter and a second parameter whose prediction probability is approximately the center of a general image, and switches the first and second parameters according to the number of times the prediction results match or mismatch. To do.

〔Example〕

FIG. 2 shows an embodiment of a color image transmission system to which the present invention is applied.

The R-, G-, and B-bit 1-bit input data 200 to 202 representing each pixel of the color image are converted by the parallel-serial converter 10 into a dot-sequential serial signal of RGB order for each pixel. The serial signal D203 output from the parallel / serial converter 10 is sent to the encoder 11.

On the other hand, the input data 200 to 202 are stored in the line memory 12 having a capacity of one or more lines corresponding to the pixel position to be referred to for the state prediction, and as the output signal 205 together with the information of several lines before. It is output to the state prediction circuit 13 for determining the coding condition. In the state prediction circuit 13, the state of each pixel to be coded is determined from the output signal from the line memory 12, and the state signal St206 indicating the coded state is output.

The encoder 11 encodes the serial signal D203 based on the state signal St by encoding, for example, using an arithmetic code, as described later, and the code 207 from the encoder 11 is transmitted to the decoder 14 via the transmission path. It

The decoder 14 performs a decoding process on the transmitted code 207 and produces a decoded serial signal D'208 in the order of RGB for each pixel. This serial signal D'is converted back into 1-bit binary color data of R ', G', and B'by the serial / parallel converter 15, and based on this, color image display and recording are performed.

FIG. 4 shows the line memory 12 and the state prediction circuit 13 shown in FIG.
5 is a circuit block diagram showing the configuration of FIG. 5, and FIG. 5 shows pixel positions for each color referred to for state prediction.

That is, FIG. 5A shows the reference pixel of the encoded first color (R in the present embodiment), and it is possible to refer to the seven encoded pixels around the encoded pixel indicated by *. It represents.

Further, FIG. 5B shows a reference pixel of the coded second color (G in the present embodiment), and a total of 8 pixels including the same 7 pixels as in FIG. It refers to referring to a pixel.

Further, FIG. 5C shows a reference pixel of the third color (B in this embodiment), and 7 pixels and a first pixel similar to FIG.
This indicates that a total of nine pixels of the pixels at the same position of the color and the second color are referred to.

In the configuration shown in FIG. 5, by referring to the plurality of pixels at the reference pixel position for each color shown in FIGS. 6A and 6B,
The state of each color is determined. Hereinafter, the operation of FIG. 5 will be described.

The RGB data 200 to 202 are input to the latch groups 67 to 69 and also to the line memories 40, 41, 42, and the line memories 40 to 42 hold the RGB data delayed by one line. Also, latches 43-50, latches 51-58 and latches
Data delayed for each pixel clock are held in 59 to 66.

In the latch group 67, the latches 43, 44, 45, 46 to which the output of the line memory 40 is input and the output of the line memory 40 can refer to the data of 5 pixels on the preceding line of the encoded line. Also, with the outputs of the latches 49 and 50,
Two coded pixels on the coding line can be referred to. The data of these seven pixels is combined to form a reference pixel signal 210 for determining the state of R, which is the first color to be encoded. Also, from the latch 48, the R data 211 of the encoded pixel is the other colors G and B.
It is output for determining the state of.

Latch groups 68 and 69 with the same configuration as this latch group 67 are data
It is provided for G201 and B202, and these latch groups
Data of 7 pixels similar to that of the latch group 67 are output as reference pixel signals 212 and 214 from 68 and 69, respectively.

Further, the G data 213 of the encoded pixel is output from the latch 54 in the latch group 68 for determining the B state.

In the selector 81, the reference pixel signal is switched according to the 2-bit color instruction signal 219 indicating the color corresponding to the output of each RGB color data from the parallel-serial converter 10. That is, when the color instruction signal 219 is R, the reference pixel signal 210 and the zero signal 2 bits are selected. Further, in the case of G, the reference pixel signal 212, the R signal 212 and the zero signal 1 bit are selected.
In the case of B, the reference pixel signal 214, the R signal 211, and the G signal 213 are selected. The 9-bit selection signal 215 and the 2-bit color designating signal 219 are combined into an 11-bit signal by the packing circuit 82 and become a status signal St206. Accordingly, the state signal St represents the state of the color and the surrounding pixels to be encoded, 2 ⁷
Shows +2 ⁸ +2 ⁹ states.

In this way, when predictively encoding a color image signal represented by a plurality of color component signals, in addition to referring to surrounding pixels of the same color, the already-encoded multicolor pixel in the means for predicting the encoded pixel. Refer to.

That is, when R is first coded, the color of the coded pixel is not determined to be any of W, R, G, B, Y, M, C, and Bk.

On the other hand, when the encoded R pixel is referred to when the second G is encoded, when the color of the encoded pixel is R = 1,
That is, it becomes easy to predict the value of G by dividing into W, R, Y and M groups or when R = 0, that is, into Bk, G, B and C groups.

Furthermore, referring to encoded R and G pixels when encoding B, (W, Y), (R, M), (G, C),
It is divided into 4 groups (Bk, B), and the value of B becomes easier to predict.

Therefore, adding the color information in addition to the information from the spatial correlation improves the predictive matching rate and improves the coding efficiency.

 FIG. 1 is a block diagram of the encoder 11 shown in FIG.

Before explaining FIG. 1, the arithmetic code used in this embodiment will be explained.

As conventionally known, the arithmetic code is a method in which a code is formed by an arithmetic operation so that an input signal sequence becomes a code represented by a decimal binary number. This method is Langdo
n and Rissanen et al. “Compression of Black /
White Images with Arithmetic Coding ", IEEE Tran Co
m.COM-29, 6, (1981.6) etc. According to this document, when the already encoded input signal sequence is S, the probability of occurrence of the inferior symbol (LPS) is q, the arithmetic register Augend is A (S), and the code register is C (S), Performs the arithmetic operation of.

A (S1) = A (S) × q≈A (S) × 2- ^Q …… (1) A (S0) = 〈A (S) −A (S1)〉 _l …… (2) 〈〉 _l Indicates truncation with the significant digit l bit.

C (S0) = C (S) (3) C (S1) = C (S) + A (S0) (4) Here, the encoded data is the dominant symbol (MPS: 0 in the above example). In the case of, A (S0) and C (S0) are used for encoding the next data. Further, in the case of a less-probable symbol (LPS: 1 in the above example), A (S1) and C (S1) are used for encoding the next data.

The new value of A is multiplied by 2 ^S (S is an integer greater than or equal to 0), and 0.5
A is within the range of 1.0. This processing corresponds to shifting the operation register A S times in hardware. The same number of shifts are performed on the code register C, and the shifted-out signal becomes a code. The above processing is repeated to form a code.

Also, by approximating the appearance probability q of LPS by a power of 2 (2 ^−Q : Q is a positive integer) as shown in the equation (1),
Multiplication calculation is replaced by shift operation. In order to further improve this approximation, q is approximated by a power-of-two polynomial, for example, as in equation (5). This approximation improves the worst efficiency.

^{q≈2− Q1} + 2− ^Q2 (5) Since the arithmetic code can switch the value of Q for each coded data, the probability estimator can be separated from the coding.

In the present embodiment, a dynamic method of estimating a probability while performing encoding as described above is employed.

A block diagram of the encoder 11 that performs the above arithmetic codes will be described with reference to the first drawing.

The state signal St206 from the state prediction circuit 13 is input to the counter memory 23 and the encoding condition memory 24.

In the coding condition memory 24, a code including a dominant symbol MPS108 that is a symbol that is likely to appear and a probability of appearance of an LPS of an arithmetic code described later for each of the 2 ⁷ +2 ⁸ +2 ⁹ states represented by the state signal St206. An index I107 indicating the conversion condition is stored. The MPS 108 read according to the color and state of the image to be encoded from the encoding condition memory 24 is input to the prediction conversion circuit 27, and the prediction conversion circuit 27 outputs the serial signal 20.
A YN signal 101 that becomes 0 when 3 matches the MPS 108 is created. YN
The signal 101 is input to the update circuit 25, where the YN
When the signal is 0, the count of the corresponding state among the count values stored in the counter memory 23 is incremented. Then, the count value C106 stored in the counter memory 23 is the set value MC1 from the count table ROM22.
If it matches with 05, the index I107 is updated in a direction in which it becomes large (a direction in which the appearance probability q of LPS becomes small).
(The MPS is not inverted.) Note that the count table ROM 22 supplies the update circuit 25 with the number of MPSs MC105 shown in Table 1 determined in correspondence with the index I representing the appearance probability q of the LPS. .

Also, in the updating circuit 25, when the MPS 108 and the pixel signal D203 do not match, that is, when the YN signal from the predictive conversion circuit 27 is 1, the index I107 decreases (the LPS appearance probability q increases). Update. When a YN signal with a value of 0 comes when the index is 1, the MPS is inverted (0 →
1 or 1 → 0). The outputs I'109 and MPS'110 of the updating circuit 25 are the updated index values and are stored again in the coding condition memory 24.

In the coding parameter determination circuit 26, the index I107
The arithmetic parameter Q111 of the arithmetic code is set in the arithmetic coder 28 based on the value of. The arithmetic encoder 28 arithmetically encodes the YN signal 101 from the prediction conversion circuit 27 using the parameter Q111 to obtain a code 102.

Random start data RO is stored in the encoding condition memory 24.
M20 and initial value data ROM are connected. In addition, the number of consecutive values (0 or 1) of the YN signal from the predictive conversion circuit 27,
That is, the switching determination unit 29 that counts the number of times of coincidence and the number of times of non-coincidence of the prediction result is provided, and the initial value of the encoding condition memory 24 is switched as follows according to the count result.

That is, as the initial value before the encoding of the encoding condition memory 24, the values (I and M) of the initial value data ROM 21 which are set to the state of each reference pixel by training the document image are trained.
Enter the initial value of PS).

Then, as the encoding progresses, the YN signal is lost (YN =
When it is determined by the switching determination unit 29 that 1) continues, the initial value switching signal 250 enters the coding condition memory 24,
Random start data ROM20 value (I = 1 and MPS = 0)
Are written in the coding condition memory 24. In other words, the coding condition suitable for the document image is switched to the coding condition with which the probability of coincidence / mismatch with the general image is approximately 50%. Then, the encoding parameters are reset accordingly.

On the contrary, when the initial value before encoding is the value of the random start data ROM 20 corresponding to the general image, the switching determination unit 29 determines that the YN signal coincidence (YN = 0) continues, Initial value data RO for images, that is, document images
It is also possible to control so as to reset to the value of M21.

As described above, by rewriting all the values of I and MPS corresponding to each state in the encoding condition memory 24, the encoding parameters are accelerated so as to reach a stable state quickly.

In the above-described embodiment, all the initial value data are changed according to the prediction result. However, since the prediction state is separated for each color, it is possible to change the initial value of only a specific color. According to this, encoding efficiency is further improved for an image in which a character image of a specific color and an image of another color are mixed.

FIG. 8 is a block diagram of the predictive conversion circuit 27. The serial signal D203 and MPS108 are input to the EX-OR circuit 29, and the YN signal 101 which becomes 0 when the serial signals D203 and MPS108 match and is 1 when they do not match is output according to the logical expression in Table 2.

FIG. 3 is a block diagram of the updating circuit 25. YN signal 10
When 1 is 0, the count value C106 from the counter memory 23 is incremented by +1 in the adder 31 to become a signal C'112. This value is calculated by the comparator 33 as M from the count table ROM22.
If it is compared with C105 and the value of C ′ matches the value of MC,
The update signal UPA113 is set to 1. The YN signal 101 becomes the update signal UPB114, and UPA and UPB are the index change circuit.
Enter 35. Further, UPA and UPB are logically ORed by the OR circuit 37, and the output signal 115 of the OR circuit 37 becomes the switching signal of the selector 32. When the signal 115 is 1, the selector 32 selects the 0 signal 119 for resetting the value of the counter memory 23, outputs it as the counter update signal C ″ 116, and stores it in the counter memory 23. Therefore, the serial signal D203 and MP
When S108 does not match, and when the matching state continues for a predetermined number of times, the count value of the counter memory 23 is reset.

The index change circuit 35 includes a signal d117 (typically d = 1) for controlling the index update interval and the UPA11.
3. The current index I107 is input from the UPB 114 and the encoding condition memory 24.

Table 3 is a table showing an index updating method in the index changing circuit 35 (Table 3 shows the case where the updating step is d = 1 and d = 2.) This table is updated with the current index I. Step condition d, UPA, U
The updated index I'is determined by referring to PB. Also, I = 1 and UPB = 1 (serial signals D203 and M
If the PS108 does not match), the EX signal 118 is set.
When the EX signal 118 is 1, the inverter 36 inverts the symbol of the current MPS 108 (0 → 1 or 1 → 0) and updates MPS'110.
Get. When the EX signal is 0, MPS 'is not changed. The updated I'109 and MPS'110 are stored in the coding condition memory 24 and are used for the next processing index I and MPS.
Used as The update method shown in Table 3 is based on ROM
For example, it can be configured as a table, or can be configured as logic using an adder / subtractor.

As described above, it is determined according to the value of the index I representing the appearance probability q of LPS approximated by a power of 2 polynomial.
When the number of MPSs equal to the number of MPSs occurs, the index I is added by d to reduce the appearance probability q of LPS used for arithmetic code. The appearance probability q of the LPS used is increased. Further, when LPS occurs in a state where the appearance probability q of LPS is 0.5 (state where index I is 1), MPS is inverted.

In this way, the index I and MP are adaptively applied to the input image.
By updating S, arithmetic coding with good coding efficiency can be achieved.

FIG. 6 is an encoding efficiency curve of the arithmetic code used in this embodiment. Hereinafter, the value of the index I is indicated by a small letter i.
This curve shows the appearance probability of LPS as q and the approximate probability q at the time of encoding.
_When expressed as _ei , it is expressed by equation (6). Then, the indexes I are sequentially assigned as 1, 2, 3,... From the larger value of the appearance probability q of the LPS to the smaller value.

Here, the numerator is entropy, and q _ei is a value represented by Expression (7).

q _ei = q ₁ + q ₂ (7) The values of q ₁ and q ₂ are polynomial approximation of powers of 2 and are given in Table 5. For example, they are shown in (8) to (10).

q _e1 ′ ＝ 2 ^-1 …… (8) q _e2 ′ ＝ 2 ⁻¹ −2 ^-4 …… (9) q _e3 ′ ＝ 2 ⁻¹ +2 ^-3 …… (10) and the efficiency η at this probability The peak point q _ei at which 1.0 becomes 1.0 is hereafter called the execution probability. Also, it is clear that the efficiency is improved by coding the intersection of the efficiency curves as the boundary probability q _bi and using this execution probability as a boundary and using the adjacent execution probabilities.

In the present embodiment, the execution probability q _ei shown in Table 4 is selected from the probabilities that can be approximated by the term of 2 as shown in the equation (5). Further, Q ₁ , Q ₂ , and Q _{3 in} Table 4 are parameters Q _c 111 sent to the arithmetic encoder 18. That is, Q ₁ and Q ₂ are shift amounts given to the shift register, and two power calculations are performed by this shift calculation. Further, Q ₃ indicates the count of the second term, and switches between + and −.

 The MC values in Table 1 are determined as follows.

That is, when the number of LPS N _L, the number of MPS was N _M, the probability of LPS is given by equation (11).

Solving this equation with N _M gives equation (12).

However Represents rounding up after the decimal point. By giving q _bi shown in FIG. 7 to q in the equation (12), the number N _Mi of the dominant symbols (MPS) there is calculated. Therefore MC
Is calculated from equation (13).

MCi = N _{Mi + 1} −N _Mi (13) The value of MC in Table _{1 is} calculated from equations (11), (12) and (13) as N _L =
It is calculated as 2.

Thus, the number N _{Mi of} the dominant symbols MPS corresponding to each index I based on each boundary probability q _bi as shown in FIG.
The calculated, the difference between the dominant symbol N _M between adjacent Indetsukusu and MC for each Indetsukusu I.

The value of MC is compared with the number of dominant symbols MPS to be generated as described above. If the value of MC matches the number of dominant symbols MPS, the state is suitable for encoding using the adjacent index I. Then, the index I is changed. As a result, the index I is changed at a good timing based on the number of occurrences of the dominant symbol MPS, and the encoding using the optimal index I can be adaptively achieved.

 FIG. 7 is a block diagram of the arithmetic encoder 28.

Of the control signal Q111 (Table 4) determined by the sign parameter determination circuit 26, Q ₁ is assigned to the shift register A70,
Q ₂ is input to the shift register B71, and Q ₃ is input to the selector 72. Q ₁ and Q ₂ are Au for shift registers A and B, respectively.
Indicate how many bits to shift As123, which is a gend signal, to the right. The shifted results are output signals 130 and 131.

The signal 131 is complemented by the inverter 76 and
2 selects the output signal of the signal 131 or the inverter 76 by the control signal Q _3, to obtain an output signal 132. The adder 73 outputs a signal 130 from the shift register A70 and a signal from the selector 72.
The 132 is added and the A _S1 signal 124 is issued. Subtractor 74
Now, subtract the A _S1 signal 124 from the As signal 123 to _obtain the A _S0 signal 125
Get. One of the selectors 75 in the A _S0 signal 125 and A _S1 signal 124 selected by the YN signal 101. That is A _S0 signal when the YN signal is 1, also the A _S1 signal when the YN signal is 0 is A 'signal 126. In the shift circuit 80, a process of shifting to the left until the MSB of the A 'signal becomes 1 is performed.
As' signal 127 is obtained. The shift signal 132 corresponding to the number of shifts enters the code register 79, and the code register 79 becomes the code data 130 in which a number of bits corresponding to the number of shifts are sequentially output from the MSB.

The code data 130 is converted into a bit by a bit processing method (not shown).
Are processed so as to be within a finite number, and are transmitted to the decoder 14 side.

The contents CR128 code register 79 by the adder 77 A _S0
The signal is added to the signal 125 and the result is input to the selector 78. Also, the A _S0 signal
The 125 non-added signal CR128 also enters the selector 78,
CR '= CR when YN signal 101 is 1, C when YN signal is 0
It is output as a CR 'signal 129 that _satisfies R' = CR + A _S0 . The shift processing described above for the code register 79 is performed on the CR 'signal.

In the above description, encoding of R, G, B3 bit color signals has been described, but for Y, M, C3 bit color signals and 4 bit color signals of Y, M, C, Bk (black). However, it can be easily expanded.

Furthermore, even for color signals in which each color is 2 bits or more,
It goes without saying that it can be easily expanded.

Further, it is needless to say that the present invention can be applied not only to the transmission of color image signals such as a color facsimile, but also to the encoding for storage of color image signals in an electronic file system or the like.

Further, although the above description is an example for a color signal input / output in a dot-sequential manner, the same prediction can be made for a signal input / output in a frame-sequential manner.

FIG. 9 shows an embodiment of the frame sequential system. The buffer memories 90, 91 and 92 store color signals of RGB full screen.

The buffer memory 90 now contains the color signals to be encoded. It is assumed that the other color signals are stored in the buffer memory 91 and the buffer memory 92 as already encoded.

The signal 300 from the buffer memory 90 is sent to the encoder 11. In addition, line delay is performed by the line memory 93, and several lines are collectively sent to the state prediction circuit 94.

Further, the already transmitted color pixel signals 301 and 302 are sent from the buffer memories 91 and 92 to the state prediction circuit 94. The prediction state signal St206 is generated from these signals, and the encoder 11
Sent to

The encoder 11 uses the image signal 300 and the St signal to generate a code 2
07 will be generated.

[Effects of the Invention] As described above, according to the present invention, as the parameter for predicting the value of the pixel of interest, the first parameter determined so that the prediction probability is high for a specific image,
A second parameter having a prediction probability approximately in the center of a general image is provided, and the first and second parameters are switched according to the number of coincidences and non-coincidences of prediction results, which is suitable for an image to be encoded. Predictive coding using parameters can be performed, and the coding efficiency of images can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of an encoder to which the present invention is applied, FIG. 2 is a block diagram of a color image transmission system, FIG. 3 is a block diagram of an update circuit, and FIG. 4 is a block diagram of a state prediction circuit. 5 shows a reference pixel, FIG. 6 shows a coding efficiency curve, FIG. 7 is a block diagram of an arithmetic encoder, FIG. 8 is a block diagram of a predictive conversion circuit, and FIG. It is a block diagram of a transmission system that performs encoding by means of 10-parallel / serial conversion circuit 11-encoder 12-line memory 13-state prediction circuit 20-random start data ROM 21-initial value data. ROM

Claims (1)

(57) [Claims] 1. An image encoding method for encoding a match / mismatch between a value of a target pixel predicted by a plurality of pixels in the vicinity of the target pixel to be coded and a value of the target pixel, wherein the value of the target pixel is predicted. As a parameter for this, a first parameter determined so that the prediction probability is high for a specific image, and a second parameter where the prediction probability is approximately the center for a general image
The image coding method is characterized in that the first parameter and the second parameter are switched according to the number of times the prediction results match or mismatch.