JPH03102967A - Color image encoding system - Google Patents

Abstract

PURPOSE:To promote the efficiency of encoding by using color corraltivity by converting a binary color signal is series according to the frequency of occurrence of an objective color to be encoded. CONSTITUTION:R, G, B signals 200 to 202 are inputted to a counter 16, and the frequencies of occurrence of three colors are counted, and each color is numbered in order of the size of the frequency of occurrence, and a control signal 300 is sent to a binary sequential transducer 10. The allotment of a binary sequential signal to the combination of the color signal (R, G, B) is changed by this control signal 300 so as to rearrange them in order of the frequency of occurrence, and the binary serial signal D203 is supplied in order of color starting from the highest frequency of occurrence.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a color image encoding method in a color facsimile device that communicates color images.

[Conventional technology]

In a facsimile machine, which is a typical example of a conventional image communication device, the method for encoding black and white binary information is as follows:
MH, MR codes, etc. are used.

On the other hand, recently, the development of inexpensive color printers has progressed, and color images, especially red (R), green (G), blue (B), yellow (Y), cyan (C), magenta (M), etc. 1b
Binary color image communication with data for each IT has been proposed.

As such a binary color encoding method, a method has been considered in which three colors are encoded for each bit brain and a monochrome MI{,MR encoding method is used.

However, in the above method, (1) By encoding each R, G, and B bit plane, the amount of information held by the original R, G, and B information sources increases, resulting in poor encoding efficiency. There is a problem. Simply put, this means that color correlation information is not used.

(2) Furthermore, since the MH and MR codes perform encoding using a fixed code table, there is a problem that the encoding efficiency of color pseudo-intermediate images and the like deteriorates.

On the other hand, the conventionally known arithmetic code is a method in which the code form of an input signal string is changed by arithmetic operations so that it becomes a code expressed in binary decimal numbers. This method uses Lan
References by Gdon and Rissanen et al. “Com
Pression of Black/White
eImages with Arithmetic
Coding, IEEETran Com, C
OM-29. 6 (1981.6), etc. According to this document, the already encoded input signal sequence is
, the probability that the inferior symbol (LPS) will appear is q1, the arithmetic register Augend is A (s), the code register C (s)
Then, perform the following arithmetic operations for each input signal.

A(sl)=A(s)xqhA(s)X2-Q -・-
(i) A(so) = <A(s)-A(sl)>l-
(2) <>1 is a significant digit I! C representing truncation in bits
(sO) = C(s)
- (3)C(sl)=C
(s)+A(so)... (4)
Encoded data is the dominant symbol (MPS: 0 in the above example)
In this case, A (so) and C (so) are used to encode the next data. In addition, in the case of a less powerful symbol (LPS: 1 in the above example), A (sl) and C (sl) are used to encode the next data.

The new value of A is multiplied by 28 (S is an integer greater than or equal to O) and 0.
It falls within the range of 5<A<1.0. This processing corresponds to shifting to the left S times in hardware. The code register C is also shifted the same number of times, and the shifted out signal becomes the code. The above process is repeated to form a code.

Also, as shown in equation (1), the probability of LPS appearance q is set to 2
By approximating with a power of (2-Q: Q is a positive integer), the multiplication calculation is replaced with a shift calculation. In order to make this approximation more accurate, q is approximated by a polynomial of a power of 2 as shown in equation (5). This approximation improves the worst point of efficiency.

q42-Q'+2 噌 (5) Or, since the arithmetic code can switch the value of Q for each encoded data, the probability estimator can be separated from the encoding.

When applying this dynamic encoding of binary signals to RGB signals, there is a method of converting the RGB signals into binary sequence signals. Here, the binary sequence signal is, for example, as shown in Table 4, white, black, (1) for white, (01) for black, etc.
The signal has a length of 1 bit to 7 bits for each pixel of red, green, blue, cyan, magenta, and yellow. When the t-th bit (MsB) of the binary series signal is 1, the color signal is determined to be white, and conversely, when it is O, it is determined to be other than white. When it is other than white, look at the second bit and when it is 1, it is black, and when it is 0, it is other than black. By repeating this, when the 7th bit is 1, it is magenta, and when it is O, it is yellow.

[Problem that the invention is trying to solve]

However, in the conventional technology, encoding was performed according to the fixed conversion table shown in Table 4, so when the document contains only white and black, the binary sequence signal is the shortest, but as the number of colors such as yellow and magenta increases, There was a drawback that the binary sequence signal became long. In other words, when using the above-mentioned encoding method, the average code length during encoding does not increase in proportion to the binary sequence signal, but compared to when the shortest signal is given, the average code length during encoding does not increase in proportion to the binary sequence signal. It is inevitable that the average code length when encoding becomes longer.

SUMMARY OF THE INVENTION In view of the above-mentioned circumstances, it is an object of the present invention to provide a color image encoding method that can efficiently encode binary color images.

[Means and effects for solving the problems] In order to solve the above problems, the color image encoding method of the present invention is a color image encoding method that encodes a color image signal represented by a plurality of color component signals. The present invention is characterized in that, for the colors represented by the plurality of color component signals, short binary series signals are provided in descending order of appearance frequency.

〔Example〕

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

R, G, B each 1 bit input data 200~2o2
is converted into a binary sequence signal D203 by the binary sequence converter 10. For example, as shown in Table 4, the binary sequence signal is 1bi, such as (1) for white and (Oi) for black.
The signal has a length of t~7 bits. When the first bit (MSB) of the binary sequence signal is 1, the color signal is determined to be white, and conversely, when it is 0, it is determined to be other than white. When it is other than white, look at the second bit and when it is 1, it is black, and when it is 0, it is other than black. By repeating this, when the 7th bit is 1, it is magenta, and when it is 0, it is yellow. However, the bit allocation for series conversion is not limited to this table. The binary sequence signal D203 is sent to the encoder 1l. Also, from the binary sequence converter 1o, how many bits of sequence signal
A Bt signal 204 indicating whether the t-th signal is being output is output to the state prediction circuit l3.

On the other hand, input data 200 to 202 are input to the line i memory 12.
is stored in the output signal 2 along with the information from several lines earlier.
It is output to the state prediction circuit l3 as 05.

In the state prediction circuit l3, the coding state of each bit of the binary sequence signal to be coded is determined based on the output signal from the line memory 12 and the Bt signal 204, and a state signal St206 indicating the coding state is output.

In the encoder 1l, a code 207 is generated based on the signal D and the state signal St by encoding using, for example, an arithmetic Markov model code, as described above, and is transmitted to the decoder l4.

In the decoder 14, decoding processing is performed and a decoded binary sequence signal D' 208 is generated. RG this signal D' 208
The B converter 15 converts the signals into binary color signals of 1 bit each for R', G', and B', and based on this, a color image is displayed.
A record must be made. D' in RGB converter l5
It is clear from Table 4 that the color signals R', G', and B' can be determined by counting the number of O's following 1 in the 208 signal.

Here, in this embodiment, the counter 16 receives the RGB signal 2.
Input 00 to 202 and count the appearance frequency of 8 colors. Further, the counter 16 numbers each color in descending order of appearance frequency and sends a control signal 300 to the binary sequence converter IO.

This control signal 300 causes the color signal (
The assignment of binary sequence signals to the combination of R, G, B) is changed. Table 5-1 is an example of the frequency of appearance of eight colors. Assuming that there is a relationship f,>f2≧f,>...≧f8, the probability of appearance of white and black is relatively high. Therefore, this appearance frequency is counted by a counter l6, and the colors are rearranged in order of appearance frequency, and the shortest binary series signal D20
3 is given as shown in Table 5-2. The aforementioned control signals 300 are sent to the binary sequence converter 10 for color identification in order of priority, and the conversion table 91 (FIG. 9) is reconfigured.

Further, Table 6-1 is an example when the appearance frequency of yellow is high, and a binary series signal D203 as shown in Table 6-2 is given.

Here, the appearance frequency can be counted by a known counting means. For example, the number of appearances of eight colors within a range of a certain number of pixels may be counted, or the change in the appearance rate of each color may be calculated from the cumulative number of appearances from the start of signal input.

Further, information as to whether or not the table 9l has been reconfigured and the allocation of binary sequence signals has been changed can be included in the code 207 as a special code. It is necessary to process it as if it has been completed, and there is also a possibility that the encoding efficiency will deteriorate due to the insertion of a special code.

Therefore, in this embodiment, a counter 17 is provided on the decoding side as well, and the frequency of appearance of a color is counted using the same structure and rules as the counter 16 on the encoding side, thereby eliminating the need for the above-mentioned special code. This can prevent deterioration in encoding efficiency.

FIG. 9 is a block diagram of the binary sequence converter 10.

Input data 200-202 is a conversion table 9 such as ROM
1, each pixel is converted into a 7-bit signal 212 shown in Table 4, and input to the signal output device 92. Here, the conversion table 9l has a plurality of ROMs prepared according to the appearance frequency of colors, and a predetermined ROM according to the control signal 300.
is selected. Note that instead of the ROM, a RAM may be used for the conversion table 91, and the contents of the RAM may be rewritten in accordance with instructions from the CPU.

The signal output device 92 has a shift register configuration,
A 7-bit input signal 212 is input in parallel, and the MSB
Serially outputs l bits from
Get 3. When the sequence signal becomes 1, the signal output device 92 outputs
Alternatively, if seven O's are output, the output of the color signal of one pixel is finished and the next input data is received. Further, the signal output device 92 outputs a signal Bt204 indicating which bit of the sequence signal the currently outputted bit is.

In this way, by converting and encoding a color image signal represented by a 1-bit color component signal for each of R, G, and H into a binary series, it is possible to encode R, G, and B, which have a correlation, separately. It is possible to encode while preserving the color correlation without changing the pixel, and when encoding is performed while predicting the pixel of interest, such as in arithmetic encoding, it is possible to perform encoding while predicting the pixel of interest. The color information can be predicted and encoded without being predicted and encoded separately, improving the efficiency of encoding.

In addition, since each color component of R, G, and B representing the color of each pixel is represented as one data, in decoding, 1
By decoding the two data, R,
G and B signals can be obtained at the same time, and color images can be reproduced quickly.

FIG. 2 is a block diagram of the encoder 11.

This encoder 11 performs arithmetic encoding as described above.

The state signal St206 from the state prediction circuit 13 is input to the counter memory 23 and the encoding condition memory 24.

The coding condition memory 24 stores, for each state represented by the state signal St206, a dominant symbol MPS108 which is a symbol that is likely to appear, and an index I107 indicating a coding condition including the probability of appearance of an arithmetic code LPS to be described later. has been done. MP3108 is input to the predictive conversion circuit 27, and the predictive conversion circuit 27 generates a YN signal 101 that becomes 1 when the binary sequence signal D203 matches MPS108. The YN signal 101 is input to the update circuit 25, and in the update circuit 25, when the YN signal is 1, the counter memory 2
Among the count values stored in 3, the count of the corresponding state is incremented. When the count value C106 stored in the counter memory 23 matches the set value MC105 from the count table ROM 22, the index I107 increases in the direction (LPS
(in the direction in which the appearance probability q of q becomes smaller). (MPS
is not inverted. Note that the count table ROM 22 supplies the update circuit 25 with the number MC105 of MPS shown in Table 1, which is determined corresponding to the index {circle around (2)} representing the probability of appearance q of LPS.

Furthermore, in the update circuit 25, the MP3108 and the pixel signal D2
03 does not match, that is, Y from the prediction conversion circuit 27
When the N signal is O, the index 1107 is updated in the direction of decreasing (in the direction of increasing the LPS appearance probability q). Furthermore, when a YN signal with a value of 0 comes when the index is 1, processing is performed to invert the MPS (O→1 or 1→0). The outputs I' 109 and MPS' 110 are the updated index values and are stored again in the encoding condition memory 24.

In the encoding parameter determination circuit 26, the index I1
The coding parameter Q11 of the arithmetic code is based on the value of 07.
1 is set in the arithmetic encoder 28. This arithmetic encoder 28
Then, the YN signal 101 from the predictive conversion circuit 27 is arithmetic encoded using the parameter Qllll to obtain a code 207.

Incidentally, an initial value is given to the encoding condition memory 24, and I,
By not updating the MPS, static encoding can be easily achieved.

FIG. 8 is a block diagram of the predictive conversion circuit 27.

The binary series signal D203 and MPS108 are input to the EX-OR circuit 29, and according to the logical formula in Table 3, a YN signal 101 is output which becomes 1 when the binary series signal 0203 and MPS108 match, and becomes O when they do not match. be done.

FIG. 3 is a block diagram of the update circuit 25. When the YN signal 101 is 1, the count value C106 from the counter memory 23 is incremented by +1 by the adder 3l, and becomes the signal C'll2. This value is compared with MC105 from count table ROM 22 in comparator 33, and if the value of C' matches the value of MC, update signal UPA113 is set. Further, the YN signal 101 passes through the inverter 34 and becomes an update signal UPB 114, and UPA and UPB enter the index changing circuit 35. Also, UPA and UPB are OR
A logical OR is performed in the circuit 37, and the output signal 115 of the OR circuit 37 becomes a switching signal for the selector 32. When the signal 115 is 1, the selector 32 selects the 0 signal 119 to reset the counter value, and otherwise selects the output signal C'll2 of the adder 31 and updates the counter update signal C'll.
6, and this is stored in the counter memory 23.

The index change circuit 35 includes a signal dll7 (standardly d=1) that controls the index update step, UPA113, UPB114, and encoding condition memory 2.
4 to the current index I107 is input.

Table 2 is a table showing the index update method in the index change circuit 35 (Table 2 shows cases where the update increments are d=1 and d=2). The updated index I' is determined by referring to UPA and UPB. Further, when UPB=1 in Ico 1, EX signal 118 is set. E
When the X signal is 1, the inverter 36 inverts the symbol of the current MPS 108 (0 → l or 1 → O) and updates the MP
Obtain S'110. Also, when the EX signal is O, the MPS
' is not changed. Updated I' 109 and MP
S' 110 is stored in the encoding condition memory 24 and used as index I and MPS for the next processing.

Note that the updating method shown in Table 2 can be configured as a table using a ROM or the like, or it can be configured as a logic using an adder/subtractor.

As described above, when the number of MPSs determined according to the value of the index ■ representing the probability of occurrence q of an LPS approximated by a polynomial of a power of 2 is generated, the index I@d is added and the arithmetic code is The appearance probability q of the LPS used is made small, and on the other hand, when an LPS occurs,
The index I is subtracted by d to increase the appearance probability q of the LPS used for the arithmetic code. Furthermore, if an LPS occurs in a state where the index ■, which indicates that the LPS appearance probability q is 0.5, is 1, the MPS is inverted.

In this way, the index and MPS are adaptively applied to the input image.
By updating , arithmetic coding with high coding efficiency can be achieved.

FIG. 4 is a block diagram of the state prediction circuit l3.

The reference pixels for state prediction are A, B, and
It consists of four pixels, C and D, and three bits each representing R, G, and B I/O. * indicates the position of the pixel of interest to be encoded. 42 in Figure 4. 43, 44.
45 is a latch, and the A latch 42 holds 3-bit data of R, G, and B of one pixel before the encoded pixel, and B, C, and D are the 3-bit data of the one pixel before the encoded pixel, as shown in FIG. , one pixel before the pixel of interest, the pixel of interest, and one pixel after the pixel of interest. These latch data are input to the ROM 41. The output from ROM41 is status signal St206
become. Note that the number of reference pixels is not limited to four pixels.

That is, the state prediction circuit l3 predicts the color of the pixel of interest (which of the eight colors in Table 1) is based on the latch data of the latches 42 to 45, and calculates each of the binary series signals indicating the predicted color. A status signal St206 indicating the status of the bit is output.

FIG. 6 is a coding efficiency curve of the arithmetic code used in this embodiment. Hereinafter, the value of the index ■ will be indicated by a lowercase letter i. This curve is expressed by equation (6), where q is the probability of appearance of LPS, and qel is the approximate probability at the time of encoding.

Then, the index ■ is sequentially set to 1. 2, 3,...
・Assigned.

Here, the numerator is entrobi, and qei is the value shown by equation (7).

qel"Q 1+q 2...(
7) The value of qIl q2 is a polynomial approximation value of a power of 2 and is given in Table 5. For example, it is shown by (8) to (10).

qel =2-'...
・(8) qe2 = 2-'-2-'
・-(9) qa3 = 2-"+2-3- (1
0), and qe+, which is the peak point at which the efficiency η becomes 1.0 in this probability, is hereinafter referred to as the effective probability. Furthermore, the intersection of the efficiency curves is called the boundary probability qb+, and it is clear that the efficiency is improved by encoding using the effective probabilities adjacent to this probability.

In this embodiment, the effective probability qel shown in Table 7 is selected from the probability that can be approximated by two terms as shown in equation (5). Furthermore, Q l+ Q2, Q3 in Table 7 are parameters Q, 111 sent to the arithmetic encoder l8. That is, QI
．． Q2 is the shift amount given to the shift register, and a power of 2 calculation is performed by this shift operation. Also,
Q3 indicates the coefficient of the second item and switches between + and -.

MC in Table I (number of MPS required for index update)
The value of is determined as follows.

That is, when the number of LPS is NL1 and the number of MPS is NM,
The probability of LPS occurrence is given by equation (1l).

Solving this equation using NM yields equation (l2).

NM=LNL (1/Q 1)J
... (l2) However, LXJ represents rounding up to the nearest whole number.

By giving qbl shown in FIG. 6 to q in equation (12), the number of dominant symbols (MPS) there can be
i is calculated. Therefore, MC is calculated from equation (13).

MC i = N MITI − N Ml
...(13) The value of MC in Table 1 is expressed by the formula (11
), (12), and (13) with NL=2.

In this way, the number NM+ of dominant symbols MPS corresponding to each index ■ is determined based on each boundary probability qbl as shown in Figure 6, and the difference in dominant symbols NM between adjacent indices is calculated as MC for each index ■. do.

Then, compare this MC value and the number of generated dominant symbols as described above, and if the MC value and the number of dominant symbols match, the state is suitable for encoding using the adjacent index ■. Judging that, the index ■ is changed. As a result, the index I can be changed at a good timing based on the number of dominant symbols generated, and encoding using the optimum index I can be adaptively achieved.

FIG. 7 is a block diagram of the arithmetic encoder 28.

Of the control signals Q0111 (Table 7) determined by the code parameter determination circuit 26, shift register A7
Q+ is input to 0, Q2 is input to shift register B, and Q3 is input to selector 72. QI. Q2 is the Augend signal Asl23 for shift registers A and B, respectively.
Indicates how many bits to shift to the right.

The shifted results become output signals 130 and 131.

The signal 131 is complemented by the inverter 76, and the selector 72 selects the signal 131 or the output signal of the inverter 76 using the control signal Q3 to obtain the output signal 132.

Adder 73 receives signal 130 from shift register A70.
and the signal 132 from the selector 72 are added, and As
+ signal 124 is output. The subtracter 74 subtracts the ASI signal 124 from the As signal 123 to obtain the Aso signal 12.
Get 5. In the selector 75, the Aso signal 125 and the ASI
One of the signals 124 is selected by the YN signal 101. That is, when the YN signal is 1, the Aso signal is activated, and when the YN signal is O, the AS! The signal becomes the A' signal 126. In the shift circuit 80, processing is performed to shift the A' signal to the left until the MSB becomes 1, and this shift causes the As' signal to become 1.
27 is obtained. The shift signal 132 corresponding to the number of shifts enters the code register 79, and from the code register 79, bits corresponding to the number of shifts are sent to the KSB.
The code data 207 is output in order from the beginning.

The code data 207 is processed using a bit processing method (not shown).
The bitl sequence is processed so that it is within a finite number of bits, and is transmitted to the decoder 14 side.

Further, the content CR128 of the code register 79 is stored in the adder 7
7, it is added to the Aso signal 125 and enters the selector 78. Also, the signal CR to which the ASO signal 125 is not added is
128 also enters the selector 78, and the YN signal 101 becomes 1 (7
) when CR' = CRSYN signal is 0 (7)
=CR+Aso is output as a CR' signal 129.

The shift processing described above regarding the code register 79 is CR
'Do this for the signal.

As explained above, according to this embodiment, by performing sequence conversion to give a short sequence in descending order of appearance frequency to a binary color signal, an increase in sequence signals can be prevented, and this binary sequence signal can be It becomes possible to efficiently encode a binary color image by performing arithmetic encoding.

[Second Embodiment] Although the first embodiment has been described using, as an example, a color signal of 1 bH of color component signals RGB, the present invention is not limited to RGB, and may be a color component signal such as MMC.

Furthermore, for example, in the case of an injet printer that has four color inks of yellow, magenta, cyan, and black, it may be necessary to overlay black ink on top of the color ink (ink printing technology in the printing field). Equivalent to). In this case, YMC
By similarly creating a binary series conversion table for 4-bit data of 1 bit for each K, exactly the same effect as the first embodiment can be expected. In that case, since the number of colors is 24, the binary series code will have a maximum of 15 digits.

[Third Embodiment] In the above embodiment, the encoding of a color image has been described, but the present invention is characterized by good compatibility with a system that encodes only black and white binary image signals. That is, black and white binary information (when it is 1, it is white; when it is O, it is other than white, that is, black) information can be encoded by using only MS81 bit of the binary series signal shown in Table 1. become.

FIG. 10 is a block diagram showing a configuration added to the configuration of FIG. 1 for switching between black and white binary and binary color. The B/W signal 300 and the binary series signal D203 are switched by the selector 80 in response to a switching signal 301 from a controller (not shown).

As shown in FIG. 11, on the decoding side, the decoding process is switched by sending identification information of black and white or binary color using header information HD at the beginning of the transmission data TD.

In addition, if the average appearance probability of each color is known to some extent as shown in Table 8, even if the binary series converted signals shown in Table 4 are sent without further encoding, It goes without saying that simple encoding can also be achieved by transmitting this signal with other encoding, such as run-length encoding, instead of using the arithmetic code described above.

According to the embodiment of the present invention described above, (1) means for counting the frequency of color occurrence, (2) means for ranking in descending order of frequency of occurrence, and (3) means for providing short binary series signals in descending order of occurrence frequency. (4) It has a means to perform predictive encoding on the binary sequence converted signal, and (5) By using adaptive arithmetic codes during predictive encoding, short binary sequence signals are given in order of the frequency of appearance of colors. In this way, it is possible to adaptively generate sequence signals, minimize the number of encoded symbols, and achieve extremely efficient encoding.

Table 1 Table 2 (-) indicates don't care. Table 5-1 Table 5-2 Table 3 Table 4 Table 6-1 Table 6-2 Table 7 [Effects of the Invention] As explained above, according to the present invention, the color to be encoded By serially converting the binary color signal according to the frequency of appearance, efficient encoding can be performed using color correlation.

[Brief explanation of drawings]

Figure 1 is a block diagram of a color image transmission system, Figure 2 is a block diagram of a color image transmission system.
Figure 3 is a block diagram of the encoder, Figure 3 is a block diagram of the update circuit, Figure 4 is a block diagram of the state prediction circuit, Figure 5 is a diagram showing reference pixels, Figure 6 is a diagram showing the encoding efficiency curve. , Fig. 7 is a block diagram of the arithmetic encoder, Fig. 8 is a block diagram of the predictive conversion circuit, Fig. 9 is a block diagram of the binary sequence conversion circuit, Fig. 10 is a block diagram of the switching mechanism, and Fig. 11 is the block diagram of the binary sequence conversion circuit. It is a diagram showing an example of transmission data, where 10 is a binary sequence conversion circuit, 11 is an encoder, l2 is a line memory, and 13 is a state prediction circuit. Average code length I

Claims (3)

[Claims] (1) A color image encoding method that encodes a color image signal represented by a plurality of color component signals, in which short binary series signals are encoded in descending order of frequency of appearance for the colors represented by the plurality of color component signals. A color image encoding method characterized by giving. (2) The color image encoding method according to claim 1, characterized in that predictive encoding is used. (3) The color image encoding method according to claim 2, wherein arithmetic coding is used for encoding the predicted symbols.