JP2000350043A - Arithmetic coder and arithmetic decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain arithmetic code processing at a high speed, while flexibly coping with complicated state of the image of a coding object. SOLUTION: A plurality symbol processing discriminator 1100 discriminates whether batch processing of consecutive symbols is available and adaptively executes consecutive coding depending on the situation. This discrimination is conducted using a plurality of detectors, e.g. that are operated in parallel and detecting that consecutive context/superior symbols and normalization processing area not caused to each of consecutive symbol numbers which are an object of batch coding.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an arithmetic coding device and an arithmetic decoding device.

[0002]

2. Description of the Related Art In arithmetic coding, a method of modeling a binary image with a Markov information source, predicting a coded symbol according to the state of neighboring pixels, and arithmetically coding a prediction result is the best in terms of a compression ratio. It is known to exhibit the following characteristics.

[0003] QM-c adopted in JBIG (ITU recommendation T.82)
oder is an example. However, such a method has an excellent compression ratio, but has a problem that the processing time is long because the generation of the context, the estimation of the occurrence probability information of the symbol, and the arithmetic coding operation are repeated for each symbol.

FIG. 13 shows a main configuration of the QM-coder.

As shown in the figure, a QM-coder includes a context generation unit 200 and a context table (RAM) 210.
, A probability estimating unit 220, and an arithmetic encoder 230, and operate as follows.

First, in the context generation unit 200,
1024 states created by the 10 surrounding pixels of the encoded pixel are detected. Each state is called a context (s), and the predicted value MPS (s) of the dominant symbol and the state number of the probability estimator are read from the context table 210 for each context,
Output to probability estimation section 220. The probability estimating unit outputs the region width Qe (s) from the information to the arithmetic encoder. Arithmetic encoder 230 calculates the coded symbol value, the predicted value MPS (s) of the superior symbol, and the region width corresponding to the generation probability of the inferior symbol.
Perform arithmetic coding operation from Qe (s).

Next, the arithmetic code operation will be described with reference to FIG.

In arithmetic coding, a number line having an initial value of 0 to 1 is divided into an area width of a dominant symbol (MPS) and an area width of a recessive symbol (LPS). In the QM-coder, the LPS width is assigned to the upper side of the number line, and the MPS width is assigned to the lower side. The width obtained by adding the widths of the two regions is called an agent, and is hereinafter referred to as Areg.

FIG. 14 shows a state of area division for "0100". In the figure, A (X) represents the width of the area corresponding to the symbol sequence X. For example, the subsection A (0100) is
It corresponds to the symbol sequence “0100” and the generation probability. The encoding target symbol sequence is made to correspond to a representative point in the divided area. The representative point is set at the bottom of the partial section.

When the coded symbol and the predicted value are the same, the MPS width is selected for coding the next symbol;
PS width is selected. As described above, a representative point is provided in this area width, and the binary decimal point represents a code.

In the arithmetic coding operation, the area width is "predetermined value".
When the value is less than 2, the doubling process is repeated until the value becomes equal to or more than a predetermined value in order to prevent a decrease in precision of the decimal point (this process is called a normalization process). Here, the “predetermined value” is 1/2 of the initial value.

The normalization process is also performed when LPS is encoded. In the normalization processing, the state transition of the probability estimating unit is updated, and the value of Qe (s) differs from the next symbol, whereby a value more suitable for the probability distribution of the information source is selected.

The MPS width is large, and the LPS width Qe (s) is assigned a value smaller than the MPS width. In MPS encoding, 1
The value of the agent (Areg) after encoding the symbol is a value obtained by subtracting the LPS width Qe (s) from the agent (Areg) before encoding (that is, Areg-Qe (s)). Normalization processing is not performed until this value becomes 1/2 of the initial value.

When the MPS is continuous and the context is the same, the prediction condition of each symbol does not change.
-Computation can be performed collectively for a predetermined n symbols such as n × Qe (s). Such a collective encoding method is disclosed in Japanese Patent Publication No. Hei 7-95693 (encoding / decoding device).

[0015]

However, in the above-mentioned conventional method, the speed can be increased only when the condition of batch processing is satisfied for a predetermined number of symbols. An image pattern that may satisfy such a condition has the same context due to the horizontal movement of the pixel arrangement, so that the reference pixel and the MPS are all limited to white, all black, and horizontal stripes. Realistically, the frequency of occurrence of a horizontal stripe pattern or an all-black pattern is low, so that it is considered that the effect is obtained in an all-white portion.

However, the whole white portion in the image is the space between characters, the space between lines, left and right margins, and the like, and the size of the whole white portion greatly changes depending on the resolution and the type of image. In the error diffusion image, when the number of collective processing symbols is increased, the frequency of satisfying the collective processing condition becomes extremely low, and the effect of speeding up is hardly recognized.

The present invention has been made based on such considerations, and has an arithmetic coding apparatus and an arithmetic decoding apparatus capable of performing high-speed processing flexibly in response to various images and local states of the images. The purpose is to provide.

[0018]

According to the present invention, the number of continuously processed symbols is made variable in accordance with the local situation of an image so that the effect of speeding up can be obtained in accordance with the complexity of the image. It is.

For example, the situation is determined by a plurality of detectors,
The number of symbols for collective encoding is determined adaptively according to the situation.

Further, the number of continuously processed symbols is made variable by state transition so as to adapt to the type of image and the local state.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In one embodiment of the present invention, the number of symbols to be collectively coded / decoded is made variable.

According to another aspect of the present invention, pattern determination by a plurality of detectors is performed in parallel, and the number of symbols that can be collectively encoded and decoded is determined adaptively based on the detection results of each detector. I do.

In another aspect of the present invention, the number of symbols for collective encoding / decoding is determined by determining the maximum number of symbols among the conditions for the number of symbols for collective encoding / decoding assigned to each detector. Is performed by selecting. In deciding the number of symbols, it is desirable that the normalization processing in the arithmetic encoder does not occur.

In another aspect of the present invention, the number of symbols for which collective encoding is desired is set, and whether or not collective encoding for the set number of symbols is possible is determined by a determination unit. The number of symbols (set value) in the next encoding / decoding is changed in accordance with the propriety. That is, if the determination result is “OK”, the number of symbols for the next time is equal to or greater than the current symbol, and if “No”, the number of symbols is equal to or less than the current symbol.

According to the present invention, it is possible to perform adaptive batch arithmetic coding / decoding with a relatively simple and realistic configuration, and to perform adaptive arithmetic coding / decoding in accordance with the complexity of the coding object. High-speed processing is always performed. Therefore, the efficiency of the encoding / decoding process is improved. When mounted on a communication device such as a facsimile device, a high-performance communication device capable of performing appropriate batch encoding / decoding processing not only for character images but also for halftone images (dot images) is realized.

(Embodiment 1) FIG. 1 is a block diagram showing the overall configuration of an arithmetic code / decoder according to the present invention.

The basic configuration is the same as that of FIG. 13, but is characterized by having a multiple symbol processing decision unit 1100. As shown, the components are a context generator 1000,
Multi-symbol processing decision unit 1100, context memory 120
0, a probability estimator 1300 and an arithmetic encoder 1400.

The image data is input to the context generator 1000, and an index (s) is output according to the value of the reference pixel in the arrangement determined there. Context generator 1
000 further outputs peripheral pixel data of the encoded symbol to the multiple symbol processing determiner 1100.

The context memory 1200 has 1024 bytes.
Consists of RAM. One byte is allocated to one context, and in each byte, a predicted value MPS (s) of a coded symbol represented by 1 bit and 7 bits of a state number of the probability estimator 1300 are stored.

The probability estimator 1300 is a state transition table constituted by a ROM. The probability estimator 1300 calculates the LPS region width Qe (s)
Is output to the arithmetic encoder 1400. Arithmetic encoder 1400 outputs a coded data sequence using coded symbols, MPS (s), Qe (s), and the number of consecutively processed symbols output from multi-symbol processing determiner 1100.

The multi-symbol processing determiner 1100 uses the peripheral pixel data of the coded symbol and the values of the A register values Areg and Qe (s) of the arithmetic coder within a predetermined range from the symbol. The maximum value of the number of continuously processable symbols is calculated.

In the present embodiment, a plurality of detectors operating in parallel are provided, and whether the context and the MPS are continuous is detected in parallel for 2, 4, 8, and 16 symbols, and the maximum value is detected. select.

For example, "2 symbols" and "4 symbols"
If it is determined that all of the detectors can be processed collectively, "4
"Symbol" is selected as the number of symbols for batch processing. However, in the case where the centralization (half value) of the initial agent (Areg) is cut off when collective encoding of “4 symbols” is performed and a normalization process occurs, in order to avoid complication of the process, "2 symbols" is selected (when normalization processing occurs even with two symbols, the processing is performed sequentially).

That is, when the MPS is continuous with the same context, there is no change in the prediction condition of each symbol. Therefore, a predetermined n symbols, such as Areg−n × Qe (s), are calculated at once. However, as shown in FIG. 2, if the threshold value (point B, “0x8000”) is exceeded, the batch processing is prohibited.

Therefore, as shown in FIG. 3, as to whether or not batch processing is possible, it is determined whether normalization processing occurs (step 10) and a pattern determination whether context and MPS are continuous (step 10). There are two types of determination in step 20). If both conditions are satisfied, batch processing is performed (step 30), and otherwise, sequential processing is performed (step 30).
40).

Hereinafter, the configuration and operation of each block shown in FIG. 1 will be specifically described.

FIG. 4 is a block diagram of the context generator 1000. As shown, the context generator 10
00 denotes three shift registers 1010 to 1030, an index generator 1040, and a timing control circuit 10 for controlling the whole.
With 50.

The shift register is composed of 4 bytes, and is roughly divided into a shift register 1010 for encoding / decoding lines and shift registers 1020 and 1030 for reference lines. At the time of encoding, image data is read from a memory (not shown), and sequentially from the least significant byte of each shift register,
Is entered.

The bit positions of the shift register are identified by symbols c-7 to c23, b-7 to b23, and a-7 to a23 as shown in the figure.

Next, the operation at the time of encoding will be described.

In the initial state, all shift registers are cleared. Then, the image data is read from a memory (not shown) and the shift register 10 for the encoding / decoding line is read.
It is input sequentially from the 10 least significant bytes. After that, the line is shifted to the left until the first pixel of the line to be coded reaches the position of a0, and the lower byte is read from the memory and the 3-byte image data is packed. Similarly, for the reference line, the first pixel of the line is set at b0 and c0.

At the stage when data storage is completed, the coded symbol (indicated by "?" In the figure) is located at the position of a0. Also, a-2, a-1, b-2, b-1, b0, b1, b2,
The 10 pixels at each position of c-1 and c0 are reference pixels. These symbols are surrounded by thick dotted lines in FIG.

The index generator 1040 arranges the reference pixels in the order of a-2, a-1, b-2, b-1, b0, b1, b2, c-1, and c0. This 10-bit data becomes the index (s) for identifying the context.

After the encoding of the encoded symbol "?", In the case of sequential processing, a new context is created by shifting the entire shift register one bit to the left.

At the time of decoding, the decoded symbol is written at the position of a0. In the sequential processing for each symbol, the shift register is shifted one bit to the left each time one symbol is decoded. The decoded data is written to the memory every 8 bits. This data is byte data of a-7 to a-1 of the shift register.

The overall operation timing such as input / output of image data and bit shift is controlled by a timing control circuit 1050. The above is the configuration and operation of the context generator 1000.

Next, the configuration and operation of the multiple symbol processing decision unit 1100 will be described.

When performing batch (consecutive) encoding processing, the context (state of the reference pixel) is a predetermined pattern (for example, all pixels are white). It is necessary to determine both that the dominant symbol value (MPS) for the coded symbol is a predetermined pattern (that is, that it is continuous). The reason for determining the continuity of the MPS is that even if the reference pixel is the same, the MPS changes depending on the value of the pixel to be encoded. In this case,
This is because batch processing cannot be performed. The image data stored in the context generator 1000 described with reference to FIG. 4 is output to the multiple-symbol processing determination unit 1100 to determine whether the same context and MPS are continuous. Here, the output image data is a-2 to a15, b-2 in FIG.
B17, c-1 to c16.

FIG. 5 is a block diagram showing the configuration of the multiple symbol processing decision unit 1100.

As described above, in this embodiment, "2 symbols", "2 symbols"
"4 symbols", "8 symbols" and "16 symbols"
Is set, and the maximum value is selected from executable ones.

That is, information necessary for determining which of the 2, 4, 8, and 16 consecutive symbols is feasible is provided by a plurality of detectors provided corresponding to each continuous symbol. , And inputs the information to the continuous processing symbol number determination circuit 1113.

Each of the plurality of detectors has a configuration for performing the two types of determination shown in FIG. 3, and has the same configuration. Here, a description will be given of a case where detection is performed for “16 symbols”. A detector corresponding to batch processing of 16 symbols includes a 4-bit shifter 1104, a subtractor 1108, a comparator 1112, a comparator 1131, and a context / MPS of 16 bits. And a continuity determination circuit 1117.

4 bit shifter 1104, subtractor 1108, comparator 1
The comparator 112 and the comparator 1131 form a part for acquiring determination information for determining whether or not the normalization processing is required when the collective encoding processing is performed. The comparator 1131 is used at the time of decoding. In addition, context / MPS 1
The six continuation determination circuit 1117 is a part that detects continuation of a predetermined pattern.

The 4-bit shifter 1104 has a region width Qe (s) of the LPS.
Is shifted 4 bits to the left and multiplied by 16. 16 * Qe shifter output
(s). The subtractor 1108 calculates Areg 16 * Qe (s). The comparator 1112 compares the value with 0x8000. 0x8000
Is 1/2 of the initial value of Areg 0x10000 (corresponding to the point B in FIG. 2).

The comparator output 1120 is Areg 16 * Qe (s)> = 0
If it is x8000, set it to "1", otherwise set it to "0". Here, if Areg 16 * Qe (s)> = 0x8000, the normalization processing does not occur, and one of the conditions that allows continuous processing is satisfied.

On the other hand, the context / MPS 16 continuous judgment circuit
A step 1117 refers to the image data 1119 to determine whether the same context and MPS (s) are continuous 16 times. The image data referred to for this purpose are a-2 to a15 and b-2 to b1 in FIG.
7, image data at positions c-1 to c16.

In this embodiment, these pixels are all "white".
Alternatively, all are determined to be “black”. Since it is assumed that MPS is encoded, it is also a criterion that the pixel value matches MPS (s). Output signal 1121 when all the judgment conditions are satisfied
Is "1", otherwise "0". As shown in FIG. 2, the output signal 1120 of the comparator 1112 is “1” and the signal 1121 is “1”.
At 1 ", it can be determined that continuous processing of 16 symbols is possible.

Similarly, for the determination of continuous processing of eight symbols, information for determining whether continuous processing is possible is obtained by the 3-bit shifter 1103, the subtractor 1107, the comparator 1111, and the context / MPS 8 continuous determination circuit 1116. However, context / MPS
The eight-continuation determination circuit 1116 refers to a-2 to a7, b- in FIG.
Pixel data in the range of 2 to b9 and c-1 to c8. The same applies to the case of 4 symbols and 2 symbols. The determination of these different symbol numbers is performed simultaneously (in parallel).

The continuous processing symbol number determination circuit 1113 selects the maximum value of the number of symbols that can be continuously processed from the four determination results. A logic circuit can be easily realized by a combination of input signals. The selected number of consecutively processed symbols is output as signal 1118 to arithmetic encoder and context generator 1000. When continuous processing cannot be performed, zero is output to the signal line 1118.

Next, the arithmetic encoder 1400 will be described.
FIG. 6 is a block diagram of the arithmetic encoder 1400.

The arithmetic coding operation can be executed by a combination of addition, subtraction, and shift operation. Coded symbols and MPS (s)
Is input to the sequence control unit 1480, and the encoded symbol and MP
Compare whether S (s) matches. If they match, the coding of the MPS symbol is performed, otherwise the coding of the LPS symbol is performed.

In the MPS encoding, the value Are of the A register 1440 is
Let g be Areg = Areg Qe (s), and if Areg> = 0x8000, terminate the process. Otherwise, compare Areg with Qe (s), and if Areg <Qe (s), A = Qe (s), Creg = Creg +
Areg.

Then, Areg> = 0x80 by normalization processing
Left shift until 00 is reached. C register (Creg) 1430
Also shift left by the same number of bits. These operations are AL
It can be executed by the U (arithmetic logic operation circuit) 1450 and the shifter 1460.

At this time, the bit data overflowing to the left is output from the C register (Creg) 1430 to the serial / parallel converter 14.
The data converted at step 70 is a code data byte.

The number of consecutive symbols is input to the shifter 1410 through a signal line (1118 in FIG. 3), and becomes the number of shift bits. Similarly, Qe (s) is input to shifter 1410 as data, and the value shifted left by the number of symbols is input to Qe register 1420. The encoding operation replaces Qe (s) with the value of the Qe register in the above description. FIG. 7 is an MPS processing flow in the case of sequential processing. LPS encoding can also be performed by a combination of arithmetic and logical operations similar to MPS. If "No" in step 310, no code is generated, and the code is output only when steps 320, 330, and 340 are executed.

The encoding has been described above. Next, decoding will be described. However, description common to encoding will be omitted.

The batch decoding of 16 symbols will be described with reference to FIG. The context / MPS 16 continuity determination circuit 1117 in FIG.
Determine the continuity of the context except for a15.

FIG. 8 is a symbol decoding flow in the case of sequential processing. The batch decoding condition of the MPS will be described with reference to FIG.

In this flow, MPS (s) is always decoded when Creg <Areg is compared (Yes in step 410) and Areg <0x8000 (step 420) is No. In other cases, in the processing routine (not shown) of Cond_MPS_exchage (Step 430) or Cond_LPS_exchage (Step 450), the decoded symbol D becomes either MPS (s) or 1 MPS (s).

Assuming that the number of symbols to be decoded continuously is 16, the condition for passing the route where D = MPS (s) 16 times is as follows. Creg <Areg 16 * Qe (s) and Areg 16 * Qe (s) <0x8000 ... (1) If the context is the same for 16 symbols and the above condition is satisfied, 16 symbols can be restored as MPS (s) . This can be performed by performing a 16-bit left shift with MPS (s) set at the position of a0 of the shift register in FIG.

In FIG. 6, decoding of a symbol is performed by inputting 1-byte data from an external code memory (not shown) to a C register 1430 and comparing it with the A register value. Although details of the calculation are omitted, the restored symbol is output from the sequence control unit 1480 to the context generator 1000. The operation of determining the number of consecutively processed symbols in FIG. 5 is almost the same as that at the time of encoding, but at the time of decoding, the determination of the first condition of the above equation (1) is added. This judgment is made by comparator 1
This is done by comparing Creg and Areg 16 * Qe (s) by 131.

The determination of 2 symbols, 4 symbols, and 8 symbols is performed at the same time as in the case of 16 symbols, and at the same time at the time of encoding. The maximum number of symbols to be processed is selected by the continuous processing symbol number determination circuit 1113 based on these determination results and output to the arithmetic encoder.

As described above, at the time of encoding and decoding, the maximum value of symbols that can be continuously processed within a predetermined range can be selected. Therefore, high-speed processing can be performed in accordance with changes in the image pattern and the resolution. In addition, since the number of consecutive symbols is assigned to each of the plurality of detectors and detected in parallel, and the maximum value is selected from the respective outputs, a hardware method is adopted, so that high-speed processing is easily realized. There is also a merit.

In the present embodiment, “no normalization processing” is one of the conditions for performing the batch processing, but this is not necessarily a condition. As described above, since the normalization process complicates the calculation, it is desirable to perform the batch process within a range where the normalization process does not occur.

By the way, when batch processing is performed even if normalization processing occurs, the following processing is performed.

As described above, in the batch processing, the value of Areg is changed to Areg−n * Qe (s) for the context (s).
And n symbols are calculated together. Here, when normalization occurs during encoding and decoding of n symbols, the value of Qe (s) is updated by a predetermined state transition of the probability estimator, and becomes Qe ′ (s). In such a case, Areg-
It cannot be simply calculated as n * Qe (s).

Therefore, in this case, the number of symbols until normalization occurs is calculated using Areg, Qe (s), 0x8000, and when it is set to n1, Areg is calculated as follows. Will be. Areg− {n1 * Qe (s) + (n−n1) * Qe ′ (s)} In this case, if n1 and (n−n1) are powers of 2, calculation is easy, but generally, Otherwise, a multiplier is needed instead of the shifter. Therefore, if there is room in the device configuration, the present invention can be applied to perform batch processing (continuous processing) even in such a case. This means
The same applies to the following embodiments.

(Embodiment 2) In the above-described first embodiment, the number of symbols that can be continuously processed is determined simultaneously for a plurality of possibilities. In this case, the maximum value can always be selected according to the local state of the image, but the circuit scale is inevitably increased due to the parallel processing.

Therefore, in the present embodiment, it is possible to determine the number of symbols adapted to the local state of an image while keeping the circuit scale small.

In this embodiment, the configuration of the multiple symbol processing decision unit 1100 of FIG. 1 is different from that of the above-described embodiment (FIG. 5). Others are the same as the above-mentioned embodiment.

FIG. 9 shows a block configuration of the multiple symbol processing decision unit 1100. Unlike the configuration of FIG. 5, the shifter 1150, the subtractor 1151, the comparator 1152, the comparator 1159, the context / MP
It is composed of a circuit including the S continuation determination circuit 1154 as a set and a continuation processing symbol number determination circuit 1155.

The point of judging whether batch processing is possible or not and reflecting the result in actual processing are the same as the above-described embodiment (FIG. 5). The same is true. However, in the case of FIG. 5, the number of symbols that can be batch-processed is always determined. In the present embodiment, whether or not batch processing is possible for a desired number of symbols is determined based on detection information, and the determination result is obtained. Is reflected in the encoding of the next symbol to perform adaptation (that is, adaptation by a kind of learning effect is performed).

The number-of-continuous-processing symbols determination circuit 1155 shown in FIG.
Is a state machine having eight state transitions as shown in FIG. First, the continuous processing symbol number determination circuit 1155 gives the number of continuous symbols to be determined to the determination circuit 1153, the determination circuit 1153 determines whether batch processing is possible, and determines the result as the number of continuous processing symbol numbers. Returning to the circuit 1155, the continuous processing symbol number determination circuit 1155 adaptively changes the continuous processing symbol number by reflecting the determination result in the next batch processing determination.

Hereinafter, a specific description will be given. As shown in FIG. 10, the initial value of the eight states of the continuous processing symbol number determination circuit 1155 is “2” as the number of processing symbols.

First, the initial value “2” is input to the shifter 1150, the judgment circuit 1153, and the context / MPS continuous judgment circuit 1154.

Under these conditions, the same determination as in the first embodiment is performed. If it is determined that continuous processing is possible, the number of symbols 1158 is set to 2
= 2 ^ 1, so "1" is output. The symbol "^" is a power. Otherwise, "0" is output. This determination result is fed back to the continuous processing symbol number determination circuit as a signal Hit /! Hit (hit / miss) signal. Signal Hit /! Hit
Is "Hit" if continuous processing can be performed with two symbols in this example, and "! Hit" otherwise.

The internal state of the continuous processing symbol number determination circuit 1155 transitions according to Hit /! Hit. In the case of Hit, the number of symbols is increased at the time of encoding the next symbol. Conversely, make it smaller for! Hit. If the transition state is at the minimum value or the maximum value and a mishit or hit occurs, the minimum value or the maximum value is maintained next time.

FIG. 11 summarizes the operation when "2" is set as the initial value. That is, once the number of symbols is set (step 100), it is determined whether batch processing is possible (step 110).
Batch processing for two symbols is executed (step 130), and the set value in the next batch processing determination is changed to “4” (step 140). On the other hand, if it is determined in step 110 that batch processing is not possible, the processing is switched to sequential processing and executed, and the set value in the next batch processing determination is maintained at “2” (step 120).

Due to such a state transition, a small value (a small number of consecutive symbols) is selected for a halftone in which an all white area is unlikely to appear, and a large value (a large number of consecutive symbols) is selected for a character image in which an all white area is likely to appear. Is done. As a result, the number of continuously processed symbols adapted to the image pattern and local state is obtained, and high-speed processing is realized.
In this embodiment, a detector operating in parallel is not required, which is advantageous in terms of circuit size and current consumption.

FIG. 12 shows the above two embodiments.
FIG. 3 is a block diagram illustrating a hardware configuration of a facsimile apparatus equipped with a QM encoding / decoding circuit.

As shown, the facsimile apparatus includes a host processor 102, an MH / MR / MMR encoding / decoding circuit 103, an image processing circuit 104 for performing processing such as resolution conversion and enlargement / reduction, and a QM Encoding / decoding circuit 105
, An image line memory 106, a code memory 107, and a communication interface such as a modem (functioning as an interface for wired transmission using the telephone line 113 or the like) 108
, An image input device 111 such as a scanner, and an image recording / display device 112 such as a printer. Each block can exchange information with each other via internal buses 109 and 110.

By applying the present invention, high-speed arithmetic encoding / decoding can be realized by flexibly adapting to the type of image, and in this respect, the function of the facsimile apparatus (communication apparatus) can be enhanced.

[0093]

As described above, according to the present invention,
It is possible to flexibly select the number of symbols that can be continuously processed within a preset range according to various images and local states of the images. Therefore, high-speed encoding / decoding processing flexibly corresponding to the complexity of an image can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an arithmetic coding device (arithmetic decoding device) according to a first embodiment of the present invention;

FIG. 2 is a diagram for explaining an agent division process when a batch encoding process is performed;

FIG. 3 is a flowchart of a process for determining whether batch encoding is possible or not.

FIG. 4 is a block diagram showing a configuration of a context generator according to the first embodiment.

FIG. 5 is a block diagram showing a configuration of a multi-symbol processing determination unit according to Embodiment 1.

FIG. 6 is a block diagram illustrating a configuration of an arithmetic encoder according to the first embodiment;

FIG. 7 is a flowchart showing a procedure of MPS processing (symbol sequential processing) of the QM-coder.

FIG. 8 is a flowchart showing a procedure of symbol decoding processing (symbol sequential processing) of the QM-coder.

FIG. 9 is a block diagram showing a configuration of a multi-symbol processing determiner according to Embodiment 2.

FIG. 10 is a diagram showing a state transition of a multi-symbol processing determination unit according to Embodiment 2.

FIG. 11 is a flowchart showing a procedure of a collective encoding process according to the second embodiment;

FIG. 12 is a block diagram showing a hardware configuration example of a facsimile apparatus to which the present invention is applied.

FIG. 13 is a diagram showing a main configuration of a general arithmetic encoder.

FIG. 14 is a diagram for explaining the principle of arithmetic coding;

[Explanation of symbols]

 1000 Context generator 1100 Multi-symbol processing decision unit 1200 Context memory 1300 Probability estimator 1400 Arithmetic encoder

Claims (20)

[Claims] 1. An arithmetic coding apparatus for predicting a coded symbol based on a value of a reference pixel around the coded symbol and coding the prediction result, wherein the number of symbols to be collectively coded is made variable. Arithmetic coding device. 2. An arithmetic decoding apparatus for decoding symbols according to values of reference pixels around decoded symbols, wherein the number of symbols to be collectively decoded is variable. 3. An arithmetic coding apparatus for predicting a coded symbol based on a value of a reference pixel around the coded symbol and coding a result of the prediction, comprising the steps of: A plurality of detectors for detecting that a value of a reference pixel used when encoding an encoded symbol matches a predetermined pattern, and collective encoding can be performed based on detection results of these detectors Arithmetic coding, comprising: symbol number determination means for determining the number of symbols; and arithmetic coding means for collectively coding continuous symbols for the number of symbols determined by the symbol number determination means. apparatus. 4. The arithmetic coding apparatus according to claim 3, wherein each of the plurality of detectors performs detection in different conditions of the number of symbols to be collectively coded in parallel. 5. The number-of-symbols determination means checks whether any of the plurality of detectors operating in parallel outputs a signal indicating that the signal matches the predetermined pattern. 5. The arithmetic method according to claim 4, wherein when a plurality of detectors are applicable, the maximum number of symbols among the conditions for the number of symbols to be collectively encoded assigned to the detectors is selected. Encoding device. 6. The symbol number determining means determines the number of symbols that can be collectively encoded, provided that no normalization processing is performed in the arithmetic encoding means even when the collective encoding is performed. The arithmetic coding device according to any one of claims 3 to 5, wherein 7. A decoding apparatus for decoding a symbol by a value of a reference pixel around the decoded symbol, wherein a reference pixel corresponding to a plurality of predetermined consecutive decoded symbols matches a specific pattern. A plurality of detectors to be detected, symbol number determining means for determining the maximum number of symbols that can be collectively decoded based on the detection results of these detectors, and a continuous number of symbols determined by the symbol number determining means. Arithmetic decoding means for collectively decoding the decoded symbols. 8. The arithmetic decoding apparatus according to claim 7, wherein each of the plurality of detectors performs detection in different conditions of the number of symbols to be collectively decoded in parallel. 9. The symbol number determination means checks whether any of the plurality of detectors operating in parallel has output a signal indicating that it matches the predetermined pattern. 9. The arithmetic method according to claim 8, wherein, when a plurality of detectors are applicable, the maximum number of symbols among the conditions for the number of symbols to be collectively decoded assigned to the detectors is selected. Decryption device. 10. The symbol number determination means determines the number of symbols that can be decoded collectively, on condition that no normalization processing is performed in the arithmetic decoding means even if the collective decoding is performed. Claim 7 to Claim 9
The arithmetic decoding device according to any one of the above. 11. A coding apparatus for predicting a coded symbol based on a value of a reference pixel around the coded symbol and coding a result of the prediction, comprising the steps of: A detector that detects that the value of a reference pixel used in encoding matches a specific pattern, and whether it is possible to collectively encode a desired number of symbols based on the detection result of the detector An arithmetic coding device comprising: a determination unit for determining whether or not the number of symbols is to be determined; and a batch-coded symbol number changing circuit that changes the number of symbols to be batch-coded based on a determination result of the determination unit. 12. When the determination means determines that the desired collective encoding is not possible, the collective encoded symbol number changing circuit determines the number of symbols desired to be collectively encoded at the next encoding. Is changed to a number equal to or less than the number of symbols, and if it is determined by the determination unit that desired collective encoding is possible, the number of symbols for which collective encoding is 12. The arithmetic coding device according to claim 11, wherein the arithmetic coding device is changed to a number. 13. A decoding apparatus for decoding a symbol by using a value of a reference pixel around a decoded symbol, comprising: detecting whether a reference pixel corresponding to a predetermined continuous decoded symbol matches a specific pattern; Detector for determining whether or not a desired number of symbols can be collectively decoded based on the detection result of the detector; and a symbol to be collectively decoded based on the determination result of the determination means. An arithmetic decoding device, comprising: a batch decoding symbol number changing circuit for changing the number. 14. If the determining means determines that the desired collective decoding is not possible, the collective decoding symbol number changing circuit sets the number of symbols desired to perform the collective decoding at the next decoding. Is changed to a number equal to or less than the number of symbols, and if it is determined that the desired batch decoding is possible by the determination unit, the number of symbols desired to be batch decoded is equal to or greater than the current symbol number in the next decoding. 14. The arithmetic decoding device according to claim 13, wherein the number is changed to a number. 15. A communication apparatus comprising the arithmetic coding device according to claim 1, claim 3, claim 4, claim 4, claim 5, claim 6, claim 11, or claim 12. 16. A communication device having the arithmetic decoding device according to claim 2, claim 7, claim 8, claim 9, claim 9, claim 13, or claim 14. 17. The context and dominant symbol (M
PS) and the value of the area remaining after the area widths of the inferior symbols (LPS) for the number of consecutive superior symbols have been collectively subtracted from the current agent become less than a predetermined value. It is always detected whether the second condition is satisfied, and if those conditions are satisfied, batch encoding for the maximum number of symbols that satisfies the condition is adaptively executed. Arithmetic encoding method. 18. The context and dominant symbol (M
PS) and the value of the area remaining after the area widths of the inferior symbols (LPS) for the number of consecutive superior symbols have been collectively subtracted from the current agent become less than a predetermined value. It is characterized by always detecting whether or not the second condition is satisfied, and if these conditions are satisfied, collectively decoding up to the maximum number of symbols satisfying the condition is adaptively executed. Arithmetic decoding method. 19. A method for setting the number of symbols for which collective encoding is desired, and for the set number of symbols, the first that a context and a dominant symbol (MPS) are continuous.
And the second condition that the value of the area remaining after the area widths of the inferior symbols (LPS) for the number of consecutive superior symbols are collectively subtracted from the current agent does not become less than a predetermined value. It is detected whether both are satisfied, and when those conditions are satisfied, the collective encoding for the set number of symbols is executed, and the number of symbols for which the collective encoding in the next encoding is desired is set as the current symbol number. An arithmetic coding method comprising setting a number of symbols equal to or greater than a desired number of symbols. 20. A method of setting the number of symbols for which collective decoding is desired, and for the set number of symbols, the first that a context and a dominant symbol (MPS) are continuous.
And the second condition that the value of the area remaining after the area widths of the inferior symbols (LPS) for the number of consecutive superior symbols are collectively subtracted from the current agent does not become less than a predetermined value. It is detected whether both are satisfied, and if those conditions are satisfied, batch decoding is performed for the set number of symbols, and the number of symbols for which batch decoding is to be performed in the next decoding is determined as the current symbol number. An arithmetic decoding method comprising setting a number of symbols equal to or greater than a desired number of symbols.