JP2821177B2 - Image coding method and apparatus - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding system in a facsimile apparatus or an image filing apparatus which is an image communication apparatus.

[Conventional technology]

As a conventional image coding method, a run-length coding method represented by G3, G4 facsimile recommended by CCITT (International Telegraph and Telephone Consultative Committee) is generally used. This encoding method is a method of counting the length (run length) of a pixel in which white or black continues, and determining a code corresponding to the count value from a code table prepared in advance. The code table valued here is characterized in that relatively short codes are assigned to long white runs, which are common in document images. For this reason, when the statistical properties of the run length are different from those of the reference image when creating the code table, for example, when encoding a pseudo halftone image in which white and black are frequently spotted, the code amount is reduced. There is a problem of exceeding the data.

Therefore, as one encoding method that can efficiently perform encoding even on an image that causes inconvenience when encoding based on such a run lens, encoding using a Markov model code through arithmetic code is proposed. Have been.

A conventionally known arithmetic code is a method in which a code is formed by an arithmetic operation so that an input signal sequence becomes a code represented by a decimal binary number. This method is described in the document “Compression of Blach / White” by Langdon and Rissanen et al.
Images with Arithmetic Coding ", IEEE Tran Com.COM
−29,6 (1981.6). According to this document, an already coded input signal sequence is represented by S,
Q is the probability of S), A (S) is the arithmetic register Augend,
When the code register is set to C (S), the following arithmetic operation is performed for each input signal.

A (S1) = A (S) × q ≒ A (S) × 2− ^Q (1) A (S0) = <A (S) −A (S1)> _l (2) << ₁ is valid C (S0) = C (S)... (3) C (S1) = C (S) + A (S0)... (4) where code data is a dominant symbol (MSP: the above example) In the case of 0), A (S0) and C (S0) are used for encoding the next data. Further, in the case of a less-probable symbol (LPS: 1 in the above example), A (S1) and C (S1) are used for encoding the next data.

The new value of A is multiplied by 2 ^S (S is an integer greater than or equal to 0), and 0.5
A is within the range of 1.0. This processing corresponds to shifting the operation register A S times in hardware. The same number of left shifts are performed on the code register C, and the shifted-out signal becomes a code. The above processing is repeated to form a code.

Also, as shown by the color of (1), by approximating the appearance probability q of LPS by a power of 2 (2- ^Q : Q is a positive integer),
Multiplication calculation is replaced by shift operation. In order to further improve this approximation, q is set to, for example, 2 as in the equation (5).
It has been proposed to approximate with a power of polynomial. This approximation improves the worst efficiency.

q ≒ 2− ^Q1 + 2− ^Q2 (5) [Problem to be Solved by the Invention] However, in the above-described arithmetic coding, the appearance probabilities approximated by the power of 2 are fixed, and the appearance probabilities are different. May not be efficiently coded.

Therefore, it has been proposed that the appearance probability q of the LPS is changed in accordance with the characteristics of the image to be encoded, and efficient encoding suitable for the image is performed. As the probability estimating method, there are considered a static method in which the probability is uniquely determined based on the state of the encoded pixels, and a dynamic method in which the probability is estimated while encoding.

By the way, when the appearance probability q of the LPS is approximated by a power-of-two polynomial, the value of the appearance probability q is a discontinuous value, and the change from one occurrence probability to another occurrence probability is performed. Are important factors for achieving optimal encoding.

[Means for solving the problem]

The present invention has been made in view of the above points, and an object of the present invention is to provide an image encoding method and apparatus for efficiently predictively encoding an image. A reference step of referring to the pixel of the, and a holding step of holding an index indicating the appearance efficiency of the superior symbol and the inferior symbol of the pixel of interest of the encoding target image corresponding to the state of the plurality of pixels referred to, An encoding step of encoding a target pixel of the encoding target image based on the held value of the superior symbol and the index, wherein the encoding target pixel of the encoded target image has a superior symbol And an updating step of updating the value of the held superior symbol and the index in accordance with whether the symbol is the inferior symbol or the inferior symbol. A setting step of setting a plurality of tables including a plurality of indexes and having different update widths of the plurality of indexes included in each of the plurality of indexes, and selecting one of the plurality of tables based on the update history of the indexes And updating the held index based on the plurality of indexes included in the selected table in the updating step. A reference unit that refers to a plurality of predetermined pixels of the encoding target image; and a dominant symbol of a pixel of interest of the encoding target image corresponding to a state of the plurality of pixels referenced by the reference unit. Holding means for holding a value and an index representing the probability of occurrence of the inferior symbol; Encoding means for encoding a pixel of interest of the image to be encoded based on the value of the dominant symbol and the index, and a pixel of interest of the image to be encoded which has been encoded by the encoding means. Or updating means for updating the index and the value of the superior symbol held in the holding means depending on whether the symbol is the inferior symbol, the updating means, each including a plurality of indexes, And a plurality of tables each having a different update width of the plurality of indexes included therein, selecting one of the plurality of tables based on an update history of the index, and selecting the plurality of indexes included in the selected table. Updating the index held in the holding unit based on the image encoding apparatus. is there.

〔Example〕

FIG. 1 shows an embodiment of an encoding apparatus to which the present invention is applied. The image signal 100 that has become binary information (0 or 1, white or black) is input to the line memory 10, and data for several rows is held. The output signal 103 from here is sent to the state determination circuit 1
By inputting to 1, the state to which the pixel of interest in the image signal 100 belongs is determined. The total number of states is determined by how many pixels around the target pixel are to be referred to. If the number of reference pixels is n, the total number of states has a relationship of 2 ⁿ . State signal indicating the determined state
St104 is input to the counter memory 13 and the encoding condition memory 14.

The encoding condition memory 14 stores, for each state represented by the state signal St104, a dominant symbol that is a symbol that is likely to appear.
An MSP 108 and an index 1107 indicating an encoding condition of an arithmetic code to be described later are stored. The MPS 108 is input to the predictive conversion circuit 17, where the image signal 100 is
And outputs a YN signal 101 which becomes 1 when it matches. YN signal 1
01 is input to the update circuit 15, and when the YN signal is 1, the update circuit 15 increments the count of the corresponding state among the count values stored in the counter memory 13 for each state by one. Then, when the count value C106 stored in the counter memory 13 matches the set value MC105 from the count table ROM 12, the index I107 is updated in a direction to increase (a direction in which the appearance probability q of LPS decreases). (The inversion of the MPS is not performed.) The count table ROM 12 supplies the update circuit 15 with the MC 105 of the number of MPSs shown in Table 1 determined in correspondence with the index I indicating the appearance probability q of the LPS. I do.

Further, in the updating circuit 15, when the MPS 108 and the pixel signal 100 do not match, that is, when the YN signal from the predictive conversion circuit 17 is 0, the index I107 decreases (the LPS appearance probability q increases). Update. When a YN signal with a value of 0 comes when the index is 1, the MPS is inverted (0 →
1 or 1 → 0). Output I'109, MPS '
110 is the value of the updated index, which is stored in the encoding condition memory 14 again.

In the coding parameter determination circuit 16, the index I107
The arithmetic coding parameter Q111 of the arithmetic code is set in the arithmetic encoder 18 based on the value of. The arithmetic encoder 18 arithmetically encodes the YN signal 101 from the prediction conversion circuit 17 using the parameter Q111 to obtain a code 102.

FIG. 2 is a block diagram of the predictive conversion circuit 17. The image signal 100 and the MPS 108 are input to the EX-NOR circuit 20, and a YN signal 101 that is 1 when the image signal 100 and the MPS 108 match and 0 when they do not match is output according to the logical formula in Table 2.

FIG. 3 is a block diagram of the updating circuit 15. YN signal 10
When 1 is 1, the count value C106 from the counter memory 13 is incremented by +1 in the adder 21 to become a signal C'112. This value is calculated by the comparator 23 as M from the count table ROM12.
Compared with C105, if the value of C 'coincides with the value of MC, the update signal UPA113 is set. In addition, the YN signal 101 is
, The update signal UPB114, and UPA and UPB enter the index change circuit 25. UPA and UPB are logically ORed by OR circuit 27.
And the output signal 115 of the OR circuit 27 becomes a switching signal of the selector 22. When the signal 115 is 1, the selector 22 selects the 0 signal 119 to reset the counter value, and otherwise selects the output signal C'112 of the adder 21 and outputs it as the counter update signal C'116. Counter memory 13
To memorize.

The index change circuit 25 includes a signal d117 (typically d = 1) for controlling the index update interval and the UPA11.
3. The current index I107 is input from the UPB 114 and the encoding condition memory 14.

Table 3 is a table showing an index update method in the index change map 25 (Table 3 shows a case where the update interval is d = 1 and d = 2). , UPA, and UPB to determine the updated index I '. When I = 1 and UPB1, the EX signal 118 is set. When the EX signal is 1, the inverter 26 inverts the symbol of the current MPS 108 (0 → 1 or 1 → 0) to obtain an updated MPS′110. When EX = 0, MPS 'is not changed. Updated I'109 and MP
S'110 is stored in the encoding condition memory 14, and is used as an index I and MPS for the next processing. The updating method shown in Table 3 can be constituted by a table using a ROM or the like, or can be constituted by logic using an adder / subtractor.

As described above, when as many MPSs as the number of MPSs determined according to the value of the index I representing the appearance probability q of the LPS approximated by the power-of-two polynomial are generated, the index I
Is added, and the appearance probability q of the LPS used for the arithmetic code is reduced. On the other hand, when the LPS occurs, the index I is subtracted by d to increase the appearance probability q of the UPS used for the arithmetic code. Further, when the LPS is generated while the index I indicating that the appearance probability q of the LPS is 0.5 is 1, the MPS is inverted.

In this way, the index and MPS
Is updated, arithmetic coding with good coding efficiency can be achieved.

FIG. 4 is a block diagram of the state determination circuit 11. The reference pixels for determining the state are the four pixels A, B, C, and D shown in FIG. * Indicates a target pixel position to be encoded. In FIG. 4, reference numerals 42, 43, 44, and 45 denote latches, an A latch 42 holds data one pixel before the image signal 100 of the volume of interest *, and a B latch 43, a C latch 44, D As shown in FIG. 5, each of the latches 45 holds data of a position corresponding to one pixel before the current target pixel position, a target pixel position, and a position corresponding to one pixel after the target pixel position, as shown in FIG. The latch data is input to the decoder 41. The output from the decoder 41 becomes a state signal St104 (0 to 15) indicating 16 states.
Note that the number of reference pixels is not limited to four pixels.

FIG. 6 is an encoding efficiency curve of the arithmetic code used in this embodiment. Hereinafter, the value of the index I is indicated by a small letter i.
This curve shows the appearance probability of LPS as q and the approximate probability q at the time of encoding.
_When expressed as _ei , it is expressed by equation (6). Then, the indexes I are sequentially assigned as 1, 2, 3,... From the larger value of the appearance probability q of the LPS to the smaller value.

Here, the numerator is etropy, and q _ei is a value represented by Expression (7).

q _ei = q ₁ + q ₂ (7) The values of q ₁ and q ₂ are power-of-two polynomial approximations and are given in Table 4. For example, they are shown in (8) to (10).

q _e1 = 2 ^-2 +2 ^-2 ... (8) q _e2 = 2 ^-1 +2 ^-4 ... (9) q _e3 = 2 ^-2 +2 ^-3 ... (10), and the efficiency η becomes 1.0 at this probability. The peak point q _ei is hereinafter referred to as the effective probability. In addition, it is clear that the efficiency is improved when the intersection of the efficiency curves is called a boundary probability q _bi and coding is performed using the adjacent effective probability with this probability as a boundary.

In the present embodiment, the effective probabilities q _ei shown in Table 4 are selected from the probabilities that can be approximated by two terms as shown in Expression (5). Further, Q ₁ , Q ₂ , Q _{3 in} Table 4 are parameters Q _c 111 to be sent to the arithmetic encoder 18. That is, Q ₁ and Q ₂ are shift amounts given to the shift register, and a power of 2 is calculated by this shift operation. Q ₃ represents the coefficient of the second term,
Switches between + and-.

 The MC values in Table 1 are determined as follows.

That is, when the number of LPS N _L, the number of MPS was N _M, the probability of LPS is given by equation (11).

Solving this equation with N _M gives equation (12).

N _M = N _L (1 / q−1) (12) where x represents the fractional part rounded up. Expression (1
By giving the boundary probability q _bi shown in FIG. 6 to q in 2), the number N _Mi of dominant symbols (MPS) there is calculated. Therefore, MC is calculated from equation (13).

MCi = N _{Mi + 1} −N _Mi (13) The value of MC in Table 1 is obtained from equations (11), (12), and (13) as N _L = 2
It is calculated as

Thus, to the number of calculated N _Mi, the difference of each Indetsukusu I dominant symbols N _M between adjacent Indetsukusu the symbol MPS corresponding to each Indetsukusu I on the basis of each boundary probability q _bi as sixth illustrated MC.

Then, the MC value is compared with the number of dominant symbols to be generated as described above. If the MC value matches the number of dominant symbols, the state is determined to be suitable for encoding using the adjacent index I. And the index I is changed. As a result, the index I is changed at a good timing based on the number of occurrences of the superior symbols, and the encoding using the optimal index I can be adaptively achieved.

 FIG. 7 is a block diagram of the arithmetic encoder 18.

Q ₁ of the control signal Q _c 111 (Table 4) determined by the code parameter determination circuit 16 is assigned to the shift register A 70,
Q ₂ is input to the shift register B, and Q ₃ is input to the selector 72.
Q ₁ and Q ₂ instruct shift registers A and B how many bits to shift As123, which is the Augend signal, to the right. The shifted results are output signals 130 and 131.

The signal 131 is complemented by the inverter 76 and
2 selects the output signal of the signal 131 or the inverter 76 by the control signal Q _3, to obtain an output signal 132. The adder 73 outputs a signal 130 from the shift register A70 and a signal from the selector 72.
The addition of 132 is performed, and an _AS1 signal 124 is output. Subtractor 7
In 4 subtracts the A _S1 signal 124 from the A _S signal 123, A _S0 signal 125
Get. One of the selectors 75 in the A _S0 signal 125 and A _S1 signal 124 selected by the YN signal 101. That is A _S0 signal when the YN signal is 1, also the A _S1 signal when the YN signal is 0 is A 'signal 126. In the shift circuit 80, a process of shifting to the left until the MSB of the A 'signal becomes 1 is performed.
An A _S 'signal 127 is obtained. The shift signal 132 corresponding to the number of shifts enters the code register 79, and the number of bits corresponding to the number of shifts is output from the code register 79 in order from the KSB to become the code data 130.

Code data 130 is stored in bit 1 by a bit processing method (not shown).
Are processed so as to be within a finite number, and sent to a receiver (not shown).

The contents CR128 code register 79 by the adder 77 A _S0
The signal is added to the signal 125 and the result is input to the selector 78. Also, the A _S0 signal
The 125 non-added signal CR128 also enters the selector 78,
CR '= CR when YN signal 101 is 1, CR' = CR when YN = 0
It is output as a CR 'signal 129 which becomes + A _S0 . The shift processing described above for the code register 79 is performed on the CR 'signal.

Incidentally, the signal of d117 in the update circuit shown in FIG. 3 may be fixed, for example, d = 1, but the following can be further accelerated as shown below.

 FIG. 8 is a block diagram of the decision circuit of d.

EXO indicates that either UPA or UPB signal is set to 1
Detection is performed by the R circuit 80, and a detection signal 140 is output. This output
Drives latches 83-87 when 140 is set, UP
The history of the past several times of the A and UPB signals is retained. As shown in Table 5, the signal 146 is UPA when it is 1 and U when it is 0.
This indicates that PB has been set to 1. Ratch 83 ~
The output signals 141 to 145 from 87 are determined by the determination circuit 88, for example,
A determination signal 14 indicating whether all 1's, all 0's, other than that, etc.
7 is output to the d setting circuit 89. The d setting circuit 89 outputs the d signal 117 so that d = 2 when all 1 or all 0, and d = 1 otherwise. This makes it possible to switch between the tables shown in Table 3.

As described above, when the index update processing is continuous, the index update width is increased, so that the index I can be quickly followed in accordance with the image.

In the present embodiment, the value of d is a positive integer, but d = 1 /
It is also possible to change the circuit to take values such as 2 or 1/4.

In addition, the appearance probability of the inferior symbol LPS is set to the
Although approximation was made by addition and subtraction of terms, it goes without saying that the number of terms is not limited to this.

[Effects of the Invention] As described above, according to the book, with reference to a plurality of predetermined pixels of the encoding target image, the dominant symbol of the target pixel of the encoding target image corresponding to the state of the plurality of pixels. And an index indicating the probability of occurrence of the inferior symbol, and encoding the pixel of interest of the image to be encoded based on the value of the inferior symbol and the index. Since the value and index of the superior symbol are updated according to whether the pixel is the superior symbol or the inferior symbol, encoding using the superior symbol value and the index suitable for the content (property) of the encoding target image is performed. Dynamically and adaptively, it is possible to improve the coding efficiency,
Further, each further includes a plurality of indexes, and
Providing a plurality of tables each having a different update width of a plurality of indexes included therein, selecting one of the plurality of tables based on the update history of the index, and updating the index based on the plurality of indexes included in the selected table Therefore, for example, if the index update processing occurs infrequently, select a table with a small index update width, while if the index update processing is continuous, select a table with a large index update width. Accordingly, the index used for dynamic and adaptive coding can be made appropriate for the occurrence state of the superior symbol and the inferior symbol, and the encoding efficiency can be further improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of an encoder to which the present invention is applied, FIG. 2 is a block diagram of a prediction conversion circuit, FIG. 3 is a block diagram of an update circuit, FIG. 4 is a block diagram of a state determination circuit, FIG. 6 is a diagram showing a reference pixel, FIG. 6 is a diagram showing an encoding efficiency curve, FIG. 7 is a block diagram of an arithmetic encoder, FIG. 8 is a block diagram of a circuit for determining d based on an update history, and 11 is a state. A decision circuit, 12 is a count table ROM, 13 is a counter memory, 14 is an encoding condition memory, 15 is an update circuit,
16 is an encoding parameter decision circuit, 17 is a predictive conversion circuit, 18
Is an arithmetic encoder.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 7/24-7/68 H04N 1/41-1/419

Claims (2)

(57) [Claims] A reference step of referring to a plurality of predetermined pixels of an encoding target image; and a dominant symbol and a dominant symbol of a pixel of interest of the encoding target image corresponding to a state of the referenced plurality of pixels. A holding step of holding an index indicating a symbol appearance probability; an encoding step of encoding a target pixel of the encoding target image based on the held dominant symbol and the index; and Updating the value of the retained superior symbol and the index according to whether the pixel of interest in the encoding target image is a superior symbol or an inferior symbol, further comprising: A setting step of setting a plurality of tables including a plurality of indexes and having different update widths of the plurality of indexes included in each of the plurality of indexes; And a selecting step of selecting one of the plurality of tables based on an update history of the index. In the updating step, the selected table is stored based on the plurality of indexes included in the selected table. And updating the index. 2. A reference unit for referring to a plurality of predetermined pixels of an image to be encoded, and a dominant pixel of interest of the image to be encoded corresponding to a state of the plurality of pixels referenced by the reference unit. Holding means for holding a symbol value and an index indicating the probability of occurrence of the inferior symbol; and encoding a target pixel of the encoding target image based on the value of the superior symbol and the index held by the holding means. Encoding means, and the value of the priority symbol held in the holding means depending on whether the pixel of interest of the encoding target image encoded by the encoding means is a superior symbol or an inferior symbol. And updating means for updating the index, wherein the updating means includes a plurality of indexes, and the plurality of indexes included in each of the plurality of indexes. A plurality of tables having different update widths of the indexes, selecting one of the plurality of tables based on the update history of the index, and holding the selected table based on the plurality of indexes included in the selected table. An image encoding device for updating the index.