JPH02285776A - Picture coding system - Google Patents

Abstract

PURPOSE:To improve the tracking performance of a change in establishment of coincidence of prediction after predictive conversion of a picture by revising an index deciding a parameter of arithmetic coding at an optimum revision period depending on the state of occurrence of a majority symbol and a minority symbol so as to change the revision range with the revision history. CONSTITUTION:A data by several lines of a picture signal 100 of binary information is stored in a line memory 10 and a state of a noted picture element belonging to the signal 100 is decided from an output signal 103 with a status decision circuit 11. A status signal St 104 representing the decided state is inputted to a counter and coding condition memories 13, 14 and an index I 107 representing the majority symbol MPS 108 and a coding condition of an arithmetic code is stored in the memory 14 for each status and outputs a YN signal 101 being logical 1 when the MPS 108 is coincident with the signal 100 at a prediction conversion circuit 17 and a revision circuit 15 advances a count stored for each state in the memory 13 when the level of the signal 101 is logical 1 and when the count stored in the memory 13 is coincident with a setting value MC 105 from a count table ROM 12, the index I 107 is revised.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image encoding method in a facsimile device or an image filing device, which are image communication devices.

[Conventional technology]

The conventional image encoding method is G3. recommended by CCITT (International Telegraph and Telephone Consultative Committee). A run-length encoding method, typified by G4 facsimile, is generally used. This encoding method counts the number of run lengths in which pixels are white or black, and determines a code corresponding to the counted value from a code table prepared in advance. The code table used here is characterized in that relatively short codes are assigned to long white runs, which are common in document images. Therefore, if the statistical properties of the run length are different from those of the image used as a reference when creating the codebook, for example, when encoding a pseudo-halftone image in which white and black are frequently reversed, the amount of code becomes A problem arises in that the data exceeds the original data.

Therefore, as an encoding method that can perform efficient encoding even for images that would cause problems when encoded based on such run lengths, encoding using Markov model codes such as arithmetic codes is proposed. Proposed.

Conventionally known arithmetic codes convert input signal sequences into 2 decimal numbers.
This is a method in which the code is formed by arithmetic operations so that the code is expressed in base numbers. This method is based on Langdon
and the document “Compreh” by Ri, 5sanen et al.
session of Black/White Image
with Arithmetic Coding
, IEEE TranC,om,C0M-29,6
, (1981, 6), etc. According to this document, the input signal sequence that has already been encoded is denoted by S, the inferior symbol (
LPS) is expressed as 91. When the arithmetic register Augend is A (S) and the sign register is C (S), the following arithmetic operation is performed for each input signal.

A(Sl)=A(S)Xq '9A(S)X2-Q ・
...(1)A(SO)=<A(S)-A(Sl))z
...(2) <>1 indicates truncation with 11 significant digits c(so) = C(S) ・
...(3) C(St)=C(S)+A(SO)
...(4) Here, if the encoded data is a dominant symbol (MPS: O in the above example), A (SO),
C(SO) is used to encode the next data. In addition, in the case of a less powerful symbol (LPS: l in the above example), A (S
l), C(St) is used to encode the next data.

The new value of A is multiplied by 2s (S is an integer greater than or equal to 0), and 0.
It falls within the range of 5<A<1.0. This processing corresponds to shifting the calculation register A eight times in hardware. The code register C is also shifted to the left the same number of times, and the shifted out signal becomes the code. The above process is repeated to form a code.

Further, as shown in equation (1), the occurrence probability q of LPS is approximated by a power of 2 (2-': Q is a positive integer), thereby replacing the multiplication calculation with a shift calculation. In order to further improve this approximation, it has been proposed to approximate q with a polynomial of a power of 2, such as equation (5). This approximation improves the worst point of efficiency.

q # 2-” +2-Q!
...(5) [Problem to be solved by the invention] However, in the arithmetic coding described above, the appearance probability approximated by a power of 2 is fixed, and the efficiency is low for images with different appearance probabilities. Good encoding may not be possible.

Therefore, it has been proposed to change the LPS appearance probability q according to the characteristics of the image to be encoded to perform efficient encoding suitable for the image. Note that this probability estimation method includes a static method in which the probability is uniquely determined based on the state of pixels in the encoding stream, and a dynamic method in which the probability is estimated while encoding.

By the way, when the appearance probability q of LPS is approximated by a polynomial of a power of 2, the value of the appearance probability q is a discontinuous value and changes from one appearance probability to another. The conditions, timing, etc. are important factors in achieving optimal encoding.

[Means to solve the problem]

The present invention has been made in view of the above points.
An image encoding method that assigns an index to each probability of appearance of a less-favorable symbol approximated by a power of provides an image encoding method that updates an index so that the probability of appearance becomes small, and updates the index so that the probability of appearance becomes large when an inferior symbol occurs, and also updates the index so that the probability of appearance becomes large. The present invention provides an image encoding method that changes the update width of the index according to the history of the update state of the index.

〔Example〕 FIG. 1 shows an embodiment of an encoding device to which the present invention is applied.

The image signal 100, which has become binary information (0 or 11 white or black), is input to the line memory 10, where several lines of data are held. By inputting the output signal 103 from here to the state determining circuit 11, the state to which the pixel of interest in the image signal 100 belongs is determined.

The total number of states is determined by how many pixels around the pixel of interest are referenced, and if the number of reference pixels is n, then the total number of states is 2n. A status signal 5t104 representing the determined status is sent to the counter memory 13. The data is input to the encoding condition memory 14.

For each state represented by the state signal 5t104, the encoding condition memory 14 stores a dominant symbol MPS108, which is a symbol that is likely to appear, and an index l107 indicating the encoding condition of an arithmetic code, which will be described later. MPS10
8 is input to the predictive conversion circuit 17, and the predictive conversion circuit 17 outputs a YN signal 101 which becomes 1 when the image signal 100 matches the MPS 108. The YN signal 101 is input to the update circuit 15, and in the update circuit 15, the YN signal is 1.
At this time, the count of the corresponding state among the count values stored for each state in the counter memory 13 is incremented by one. Then, the count value C106 stored in the counter memory I3 or the count table ROM1
If it matches the set value MC105 from 2, the index 1107 is updated in the direction of increasing (in the direction of decreasing the LPS appearance probability q). (The MPS is not inverted.) The count table ROM 12 supplies the update circuit 15 with the number MC105 of MPS shown in Table 1, which is determined corresponding to the index ■ representing the probability of appearance q of the LPS. .

Further, in the update circuit 15, the MPS 108 and the pixel signal 10
If 0 does not match, that is, YN from the prediction conversion circuit 17
When the signal is O, the index 1107 is updated in the direction of decreasing (in the direction of increasing the LPS appearance probability q).

Further, when a YN signal with a value of 0 comes when the index is 1, processing is performed to invert the MPS (0→l or 1→0). Output 1' 109 and MPS' 110 are the updated index values and are stored again in the encoding condition memory 14.

In the encoding parameter determination circuit 16, the index 11
Coding parameter Q11 of arithmetic code based on the value of 07
1 is set in the arithmetic encoder 18. This arithmetic encoder 18
Now, the YN signal 101 from the predictive conversion circuit 17 is arithmetic encoded using the parameter Qllll to obtain a code 102.

FIG. 2 is a block diagram of the predictive conversion circuit [7].

The image signal 100 and the MPS 108 are inputted to the EX-NOR circuit 2°, and a YN signal 101 which becomes 0 when the image signal 100 and the MPS 108 match and 11 when they do not match is output according to the logical formula in Table 2.

FIG. 3 is a block diagram of the update circuit 15. When the YN signal 101 is 1, the count value C106 from the counter memory 13 is incremented by +1 by the adder 21 and becomes the signal C' 112. This value is compared with MC105 from count table ROM 12 in comparator 23, and if the value of C' matches the value of MC, update signal UPA113 is set. Further, the YN signal lot passes through the inverter 24 and becomes the update signal UPB114, and UPA and UPB enter the index change circuit 25. Also, UPA and UPB are OR
A logical OR is performed in the circuit 27, and the output signal 115 of the OR circuit 27 becomes a switching signal for the selector 22. When the signal 115 is 1, the selector 22 selects the O signal 119 to reset the counter value, otherwise selects the output signals C' and 112 of the adder 21, and outputs the counter update signal C'.
116 and stored in the counter memory 13.

The index change circuit 25 has a signal dl17 (standardly, d=ritoU) that controls the index update increments.
PA113. UPB 114 and encoding condition memory 14
The current index 1107 is input from .

Table 3 is a table showing the index update method in the index change circuit 25. (Table 3 shows cases where the update increments are d=1 and d=2.) Input this table ■1 Condition d, The updated index 1' is determined by referring to UPA and UPB. Also, I
=l and when UPB=1, EX signal 118 is set.

When the EX signal is 1, the inverter 26 outputs the current MPS 108.
Invert the symbol of (0-1 or 1→O) and update M
Get PS' 110. Also, when EXO is MPS'
does not change. Updated 1' 109 and MP
S' 110 is stored in the encoding condition memory 14 and used as index I and MPS for the next processing.

Note that the updating method shown in Table 3 can be configured as a table using a ROM or the like, or can be configured as a logic using an adder/subtractor.

As described above (, when MPSs as many as the number of MPSs determined according to the value of the index ■ representing the appearance probability q of an LPS approximated by a polynomial of a power of 2 are generated, d is added to the index I, and the arithmetic code is The appearance probability q of LPS used for is made small, and on the other hand, when LPS occurs,
The index I is subtracted by d to increase the appearance probability q of the LPS used for the arithmetic code. Furthermore, if an LPS occurs in a state where the index I representing the LPS appearance probability q is 0.5 is 1, the MPS is inverted.

In this way, the index and MPS are adaptively applied to the input image.
By updating , arithmetic coding with high coding efficiency can be achieved.

FIG. 4 is a block diagram of the state determination circuit 11.

The reference pixels for determining the state are A and B shown in FIG.

There are four pixels, C and D. * indicates the position of the pixel of interest to be encoded. Numerals 42, 43 and 44, 45 in FIG.
．． C latch 44. The D latch 45 is connected to the 5th one line before each
As shown in the figure, data for positions corresponding to one pixel before the current pixel position, the pixel position of interest, and one pixel after the pixel position of interest are held, and the latch data of these latches is input to the decoder 41. .The output from the decoder 41 is 16
The state signal 5t104 (0 to 15) indicates the state of the state. Note that the number of reference pixels is not limited to four pixels.

FIG. 6 is a coding efficiency curve of the arithmetic code used in this embodiment. Hereinafter, the value of the index ■ will be indicated by a lowercase letter i. This curve is expressed by equation (6) when the LPS appearance probability is the approximate probability qei at the time of 91 encoding.

Then, the index I is sequentially set to 1. 2. 3. ...and given.

Here, the numerator is entropy, and qei is the value shown by equation (7).

qei"q 1 + q 2...
- (7) The value of qIl 92 is a polynomial approximation value of a power of 2 and is given in Table 4. For example, it is shown by (8) to (10).

q el = 2-” + 2-”
...(8) qd = 2-'-2-'
...(9)q e3 '''
2-” + 2-” °= (
10), and the peak point qel at which the efficiency η becomes 1.0 in this probability is hereinafter referred to as the effective probability. Furthermore, it is clear that efficiency is improved by calling the intersection of the efficiency curves the boundary probability qb+, and encoding using the effective probabilities adjacent to this probability.

In this embodiment, the effective probability qei shown in Table 4 is selected from the probabilities that can be approximated by two terms as shown in equation (5). Also, Qll 02. in Table 4. Q3 is a parameter Q, 111 sent to the arithmetic encoder 18. That is, Ql,
Q2 is the shift amount given to the shift register, and a power of 2 calculation is performed by this shift operation. Also Q,
indicates the coefficient of the second term, and switches between - and -.

The values of MC in Table 1 are determined as follows.

That is, when the number of LPS is NL and the number of MPS is NM,
The probability of LPS occurrence is given by equation (11).

Solving this equation using NM gives equation (12).

NM= LNL (1/q 1)J...
(12) However, "X" indicates rounding up to the nearest whole number.

In equation (12), the boundary probability qbi shown in FIG.
By giving the dominant symbol (MPS)
The number N M+ is calculated. Therefore, MC is expressed as (1
3).

M Ci = N M1 straight −N M+
...
(l 3 ) The value of MC in Table 1 is given by formula (11),
It is calculated from (12) and (13) with N L = 2.

In this way, the number NMI of dominant symbols MPS corresponding to each index I is determined based on each boundary probability qbi of shall be.

The value of this MC and the number of generated dominant symbols are compared as described above, and if the value of MC and the number of dominant symbols match, the state is suitable for encoding using the neighboring index I. It is determined that index I is changed. As a result, the index l can be changed at a good timing based on the number of dominant symbols generated, and encoding using the optimal index {circle around (2)} can be adaptively achieved.

FIG. 7 is a block diagram of the arithmetic encoder 18.

Of the control signals 0.111 (Table 4) determined by the code parameter determination circuit 16, shift register A7
Ql to 0, Q 2 to shift register B, selector 7
Q3 is input to 2. Ql and Q2 are the Augend signals As1 for shift registers A and B, respectively.
Instructs how many bits to shift 23 to the right.

The shifted results become output signals 130 and 131.

The signal 131 is complemented by the inverter 76, and the selector 72 selects the signal 131 or the output signal of the inverter 76 using the control signal Q3 to obtain the output signal 132.

Adder 73 receives signal 130 from shift register A70.
and the signal 132 from the selector 72 are added, and As
+ signal 124 is output. The subtracter 74 subtracts the AS+ signal 124 from the AS signal 123 to obtain As.

A signal 125 is obtained. The selector 75 receives the Aso signal 125.
and the As+ signal 124 are selected by the YN signal 101. That is, when the YN signal is 1, the Aso signal becomes the A' signal 126, and when the YN signal is 0, the AS+ signal becomes the A' signal 126. In the shift circuit 80, processing is performed to shift the A' signal to the left until the MSB becomes 1, and this shift causes As
' signal 127 is obtained. A shift signal 132 corresponding to the number of shifts is input to the code register 79, and a number of bits corresponding to the number of shifts are sent from the food register 79.
are output in order from KSB to become code data 130.

The code data 130 is processed using a bit processing method (not shown).
The bitl sequence is processed to within a finite number and sent to a receiver (not shown).

Further, the content CR128 of the code register 79 is stored in the adder 7
7, it is added to the Aso signal 125 and enters the selector 78. Also, the signal CR to which the Aso signal 125 is not added is
l28 also enters the selector 78, when the YN signal 101 is 1, CR' = CR, and when YN = 0, CR' = CR+
As.

It is output as a CR' signal 129. The shift processing described above regarding code register 79 is performed on the CR' signal.

Note that the signal dl17 in the update circuit shown in FIG. 3 may be fixed at d=1, for example, but it is also possible to make the tracking even faster as shown below.

FIG. 8 is a block diagram of the decision circuit for d.

The EXOR circuit 80 detects that either the UPA or UPB signal is set to 1, and a detection signal 140 is output. When this output 140 is set, latch 8
3 to 87 to hold the history of the past several UPA and UPB signals. The signal 146 is as shown in Table 5.
A value of 1 indicates that UPA is set to 1, and a value of 0 indicates that UPB is set to 1.

The output signals 141 to 145 from the latches 83 to 87 are sent to a determination circuit 88 and output to a d setting circuit 89 as a determination signal 147 indicating, for example, whether they are all 1, all 0, or something else. The d setting circuit 89 sets the d signal 211 so that when all 1 or all 0, d=2) otherwise, d21.
Outputs 7. This makes it possible to switch the tables shown in Table 3.

In this way, if the index update process is continuous,
Since the update width of the index is increased, it is possible to quickly follow the index I according to the image.

Further, in this embodiment, the value of d is a positive integer, but it is also possible to change the circuit so that it can take a value such as d=% or s.

In addition, the appearance probability of the inferior symbol LPS is set to 2 to the power of 2.
Although the approximation was made by adding and subtracting terms, it goes without saying that the number of terms is not limited to this.

Table (-) indicates don't care Table (-) indicates don't care. [Effects of the Invention] As explained above, according to the present invention, the index that determines the parameters of arithmetic coding is determined based on the occurrence status of dominant symbols and inferior symbols. This allows updates to be made at the optimal update timing, allowing for good adaptive encoding of input images.Furthermore, by changing the update width based on the update history, it is possible to follow changes in the predicted match probability after predictive conversion of images. A good image encoding method can be realized.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an encoder to which the present invention is applied, Fig. 2 is a block diagram of a predictive conversion circuit, Fig. 3 is a block diagram of an update circuit, Fig. 4 is a block diagram of a state determination circuit, and Fig. 5 is a diagram showing a reference pixel, FIG. 6 is a diagram showing a coding efficiency curve, FIG. 7 is a block diagram of an arithmetic encoder, FIG. 8 is a block diagram of a circuit for determining d based on update history, and 11 is a state Determination circuit, 12 is a count table ROM. 13 is a counter memory, 14 is an encoding condition memory, 15
1 is an update circuit, 16 is an encoding parameter determination circuit, 17 is a predictive conversion circuit, and 18 is an arithmetic encoder. Port 4 - Figure palm figure 4 Noke 1 or 2 people

Claims (2)

[Claims] (1) An image coding method in which an index is assigned to each of the probabilities of appearance of inferior symbols approximated by a finite number of powers of 2, and an image signal is arithmetic encoded according to a parameter corresponding to the index, in which the dominant symbol An image code characterized in that when a predetermined number of symbols occur, the index is updated so that the probability of appearance becomes small, and when an inferior symbol occurs, the index is updated so that the probability of appearance becomes large. method. (2) The image encoding method according to claim (1), characterized in that the update width of the index is changed according to the history of the update state of the index.