JPH0670176A - Encoding method and encoding device - Google Patents

Abstract

PURPOSE:To evade the complication of hardware by setting a first flag for every n-lines and a second flag of a picture element unit in accordance with the features of first and second picture data, and predictive-encoding the first picture data in accordance with the first and the second flags. CONSTITUTION:The flag FLG='0' is set, and all reduced picture elements A to I are of the same color, and pattern prediction processing TP='1' is set to objective picture elements (a) to (d) to be encoded, and afterwards, it is judged whether a processed picture element is of the right edge of a second line or not, and if it is of the right edge of the second line, the FLG is settled when the processed picture element reaches, for instance, the right edge of the second line of a block line, and encoding processing is executed. Besides, in the case that the objective picture elements (a) to (d) to be encoded contain a different color, after TP='0' is set to the objective picture elements (a) to (d) to be encoded after FLG='1' is set, FLG is settled, and the encoding processing is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding method and a coding apparatus, for example, a coding method and a coding apparatus in an image data service.

[0002]

2. Description of the Related Art In a facsimile device, which is a typical example of a still image communication device, a binary image is coded using MH, MR codes or the like. In encoding methods such as facsimile machines, all of the image data needs to be transmitted in order to grasp the overall image of the image. For this reason, it is difficult to use the encoding method used in facsimile devices in image data services such as image database services and video texts that require quick image determination.

Therefore, in transmitting one image,
A sequential reproduction method has been proposed in which rough image information is transmitted first, and then additional information is transmitted to form gradually detailed images, and the encoding for realizing this is a hierarchical code. It is a system. In the sequential playback system,
As rough information, there are many cases in which an original image is reduced, and the reduction process is repeated several times to form a hierarchy. For example, when the image is repeatedly reduced by ½ in the vertical and horizontal directions, an image having a size of 1/4 and 1/16 is formed. In the sequential playback method, the size is first small 1
/ 16 image data is encoded and transmitted, then 1 /
Additional information for forming a 1/4 image from 16 images is encoded and transmitted, and subsequently, additional information for forming an original image from the 1/4 image is transmitted.

Further, in order to record 1/4 and 1/16 images in the same size as the original image, the recording density is reduced to 1/2 and 1/4 for output. Making this additional information as small as possible is very effective in reducing the transmission time. For this reason, there are many pre-coding processes for removing an image from a small size image that can be predicted from a small size image.

A typical pattern prediction process (hereinafter "TP")
Is also an effective means of precoding processing. TP
Is a block line, for example, if 2 × 2 4 pixels to be coded, a reduced pixel corresponding to this, and a total of 9 pixels around it are the same color, the pixel to be coded as a TP-enabled pixel Therefore, this 2 × 2 pixel is removed. That is, the TP flag added to the beginning of the block line is set to "0" when the pixel to be encoded from the reduced pixel can be TP, and is set to "1" when the exception exists and TP cannot be performed.
And For the block line having the TP flag of “0”, the TP-capable pixel is excluded from the encoding target on the receiving side, and the other pixels are subjected to normal predictive encoding. In the block line having the TP flag of "1", normal encoding is performed on all pixels.

[0006]

However, the above-mentioned conventional example has the following problems. That is, in the encoding using the TP of the above-mentioned conventional example, in order to determine whether or not the TP is possible, the pixel to be encoded, the corresponding reduced pixel and its periphery are provided for each block line by the pre-scan. It is necessary to check the pixel and add a TP flag to the beginning of each block line. Therefore, the T of the above conventional example is
In the encoding using P, it is necessary to refer to the reduced pixel and its surrounding pixels many times, and there is a drawback that the hardware becomes complicated.

[0007]

SUMMARY OF THE INVENTION The present invention is intended to solve the above problems, and has the following structure as one means for solving the above problems.

That is, second image data having a lower resolution converted from the first image data is generated, and every n lines depending on the characteristics of the first image data and the characteristics of the second image data. The first flag of the
A second flag in pixel units according to the characteristics of the image data and the characteristics of the second image data, and the first image data according to the first flag and the second flag. Is a predictive coding method.

Alternatively, a first detecting means for detecting a characteristic of the first image data and a second detecting means for detecting a characteristic of the second image data having a lower resolution converted from the first image data. And a coding means for predictively coding the first image data according to the characteristics detected by the first detection means and the characteristics detected by the second detection means. The encoding device.

[0010]

With the above arrangement, a coding method and code for predictively coding the first image data according to the characteristics of the first image data and the characteristics of the second image data having a lower resolution. A device can be provided. For example, with the above configuration, it is not necessary to refer to the reduced pixel and its surrounding pixels many times, and it is possible to provide an encoding method and an encoding device that implements hierarchical encoding with small-scale hardware.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a general hierarchical encoder. In FIG. 1, reference numeral 101 denotes a reduction processing unit a, which converts the input original image data I1 into 1 / horizontal directions.
The size of the image is reduced to 2 and the reduced image data I2 having a quarter area is output.

Reference numeral 102 denotes a reduction processing unit b, which further reduces the vertical and horizontal directions of the input reduced image data I2 to 1/2 size and outputs reduced image data I3 having an area of 1/16. Reference numeral 103 is an encoder a for inputting the reduced image data I
3 is encoded and compressed. The code data C3 output from the encoder a103 is the reduced image data I3 having a data amount of 1/16 of the original image data I1, which is further encoded and compressed, and is much smaller than the original image data I1. It becomes the amount. That is, the transmitting side first transmits the code data C3 output from the encoder a103,
On the receiving side, it is possible to decode the coded data C3 and to know the outline of the transmitted image although the image size is small.

Reference numeral 104 denotes an encoder b, which refers to the reduced image data I3 and outputs encoded data C2 obtained by encoding and compressing the reduced image data I2. Reference numeral 105 denotes an encoder c, which refers to the reduced image data I2 and outputs encoded data C1 obtained by encoding and compressing the original image data I1. FIG. 2 is a block diagram showing a configuration example of a general hierarchical decoder.

In FIG. 2, reference numeral 201 denotes a decoder a, which decodes the input code data C3. A frame memory a 204 is the decoded image data I output by the decoder a 201.
Remember 3 '. An interpolator 207 interpolates the decoded image data I3 'stored in the frame memory 204a into a required size (for example, four times the vertical and horizontal directions). Also, 202
Is a decoder b, which adds the decoded image data I3 'to the prediction reference to decode the input code data C2. A frame memory b 205 stores the decoded image data I2 'output from the decoder b202. Reference numeral 208 denotes an interpolator b, which is the decoded image data I2 'stored in the frame memory b205.
Is interpolated to a required size (for example, double the length and width).

Reference numeral 203 denotes a decoder c, which adds the decoded image data I2 'to the prediction reference to input the input code data C1.
To decrypt. A frame memory c 206 includes a decoder c2
The decoded image data I1 ′ output by 03 is stored. 20
Reference numeral 9 denotes a selector, which inputs image data I31 input from the interpolator a to the input terminal A and input from the interpolator b to the input terminal B according to a switching signal input to the selection input terminal S from a controller (not shown). Image data I21 and input terminal C
Image data I input from the frame memory c206
Select one of 11 and output.

Reference numeral 210 denotes a video memory, which is a selector 209.
The image data output from is stored. A monitor 211 displays an image or the like based on the image data stored in the video memory 210. Reference numeral 212 denotes a printer, which makes a hard copy of an image or the like based on the image data I11 output from the frame memory c206.

FIG. 3 is a block diagram showing a configuration example of the encoder b104. The encoder c105 and the encoder a103
Also has substantially the same configuration. In FIG. 3, reference numeral 304 denotes a memory n which stores the coded pixel of interest of the reduced image data I2 and its surrounding pixels. A memory m 305 stores data of several lines of the reduced image data I3. Memory 304,
The image data stored in 305 is output to a prediction unit, which will be described later, and used as a prediction reference pixel.

Reference numeral 301 denotes a typical predictor, which excludes pixels that can be predicted on the decoding side from the object of encoding, and therefore several pixels of the reduced image data I2 input from the memory n304 and the memory m.
When several pixels of the reduced image data I3 input from 305 have the same color, the pixels of the reduced image data I2 to be encoded are excluded from the encoding target. Reference numeral 302 denotes a unique predictor, which includes pixels surrounding the coded pixel of interest input from the memory n304,
When the coded pixel of interest input from the typical prediction unit 301 can be uniquely determined according to the reduction method used by referring to the reduced pixel data I3 input from the memory m305, Pixels are excluded from encoding.

Reference numeral 303 denotes a predictive coding unit, which is a unique predicting unit 30.
The image data input from 2 is encoded. FIG. 4 is a flow chart showing an example of the encoding process of the encoder b104, and shows the process of encoding an arbitrary pixel of interest for encoding. Note that the encoders c105 and a103 also perform encoding processing in a similar flow.

In FIG. 4, the encoder is step S1.
Then, it is determined whether or not the typical prediction of the coded pixel of interest is impossible. If the prediction is impossible, the process proceeds to step S2, and if the prediction is possible, the process ends. Subsequently, the encoder determines in step S2 whether or not the univocal prediction of the coded pixel of interest is impossible, and if unpredictable, the encoder proceeds to step S3.
If it is predictable, the process ends.

Subsequently, the encoder executes the encoding of the pixel of interest to be encoded in step S3, and then ends the processing. FIG. 5 is a diagram showing an example of the relationship between the pixel to be coded and the reduced pixel in the encoder b104, in which the symbol ◯ represents the reduced pixel and the symbol □ represents the pixel to be encoded. The relationship between the encoding target pixel and the reduced pixel in the encoders c105 and a103 is substantially the same.

As shown in an example in FIG. 5, one reduced pixel A corresponds to four encoding target pixels a, b, c and d,
The same applies to other reduced pixels. Also, in FIG.
A flag LG indicates a flag, which is attached to, for example, the left end of each line composed of reduced pixels. In addition, the line including the encoding target pixels a and b and the encoding target pixels c and d
Two lines including a line including a line are called block lines.

The encoder refers to, for example, the pixels to be encoded a to d shown in FIG. 5 and the reduced pixels A to I shown in FIG. In general typical prediction, if the reduced pixels A to I have the same color, the rule that the encoding target pixels a to d also have the same color is assumed, and it is determined whether or not this rule holds, A flag FLG corresponding to the result is set for each block line. That is, FLG = '0' means that all the rules are satisfied at the block line.
LG = '1' indicates that there is a case where the rule is not satisfied in the block line.

FIG. 6 is a flow chart showing an example of setting the flag FLG in a general typical prediction.
In FIG. 6, the encoder is FLG = in step S11.
"0" is set, and in steps S12, the reduced pixels A to I are set.
Are all the same color, and if they are all the same color, the process proceeds to step S13, and if pixels of different colors are included, the process jumps to step S14.

When all the reduced pixels A to I have the same color,
In step S13, the encoder determines whether all the pixels to be coded a to d have the same color and proceeds to step S14 if they are all the same color, or proceeds to step S15 if they include pixels of different colors. Go to Step S15, FL
After setting G = '1', the process is terminated. Further, the encoder determines the position of the processing pixel in step S14, and if the pixel is not the right end of the block line, returns to step S12, and if the pixel is the right end of the line block, the process is performed. finish.

That is, the encoder detects the pixel for which the above-mentioned rule is not satisfied or until the processed pixel reaches the right end of the block line, the steps S12 to S1.
When the processing of step 4 is repeated and the processing is terminated through step S14, FLG = '0'. FIG. 7 is a flow chart showing an example of determining the TP value for each pixel in a general typical prediction. The figure shows the processing of one block line.

In FIG. 7, the encoder is step S21.
Read FLG with, and then read FLG with step S22.
Is determined, and if FLG = '0', step S2
3 and if FLG = '1', proceed to step S24. If FLG = '0', the encoder determines in step S23.
Then, it is determined whether or not all the reduced pixels A to I have the same color. If all the reduced pixels have the same color, the process proceeds to step S25 without encoding, and if different colors are included, the process proceeds to step S24.

If FLG = '1' and reduced pixel A
If ~ I contains different colors, the encoder determines
After encoding the pixel of interest at 24, the process proceeds to step S25. Subsequently, the encoder determines in step S25 whether or not the pixel of interest is, for example, the right end of the line. If it is not the right end of the line, the process returns to step S22, and if it is the right end of the line, the process proceeds to step S26. That is, the encoder repeats steps S22 to S25 until the pixel of interest reaches the line density.

When the target pixel reaches the right end of the line, the encoder determines in step S26 whether or not the target pixel is the right end of the block line, for example, the second end, and if not, the step Returning to S22, if it is the right end of the second line, the process ends. The encoder repeats the processing shown in FIG. 7 for each block line to process the entire image data.

As shown in FIGS. 6 and 7, in the general typical prediction, for example, it is necessary to refer to the reduced pixels A to I twice. Hereinafter, the predictive coding according to the embodiment of the present invention will be described in detail. FIG. 8 is a flow chart showing an example of a typical prediction of an embodiment according to the present invention.

In FIG. 8, this embodiment is based on step S3.
In step 1, FLG = '0' is set, and in step S32, it is determined whether or not all the reduced pixels A to I have the same color. If they are all the same color, the process proceeds to step S33, and if different colors are included, the process proceeds to step S36. If all the reduced pixels A to I have the same color, in this embodiment, in step S33, the encoding target pixel a
~ D are all the same color, and if they are all the same color, go to step S34, and if different colors are included, step S34
Proceed to 35.

If all the pixels to be coded a to d have the same color, in this embodiment, at step S34, the pixel to be coded a is encoded.
After setting TP = '1' in .about.d, the process proceeds to step S37. If the pixels a to d to be encoded include different colors, this embodiment sets FLG = '1' in step S35 and then proceeds to step S36. Reduced pixels A to I
Are all the same color, and if the encoding target pixels a to d include different colors, in this embodiment, in step S36, after setting TP = "0" to the encoding target pixels a to d, step S37. Go to.

Next, in this embodiment, in step S37,
Whether the processed pixel is the right end of the second line of the block line is determined, and if it is the right end of the second line, step S
Proceed to step 38, and if not the right end of the second line, step S3
Return to 2. That is, in this embodiment, steps S32 to S37 are repeatedly executed until the processed pixel reaches, for example, the right end of the second line of the block line.

When the processed pixel reaches, for example, the right end of the second line of the block line, this embodiment determines FLG in step S38, and executes the encoding process described later in step S39. In this embodiment, since the FLG is determined and then the encoding can be executed, the pixel data to be encoded and the TP value thereof are stored, for example, by a 2-line buffer or the like until the encoding is executed. You need to do it.

FIG. 9 is a flow chart showing an example of the encoding process of this embodiment, which corresponds to step S39 shown in FIG. In FIG. 9, in the present embodiment, in step S41, FLG and TP of the pixel of interest to be encoded are determined, and if FLG = '0' and TP = '1', jump to step S43. In addition, in this embodiment, the step S
If the pixel of interest to be coded does not satisfy the above condition at 41, the process proceeds to step S42, the predictive coding of the pixel is executed at step S42, and then the process proceeds to step S43.

That is, in the present embodiment, in steps S41 and S42, the typical prediction rule is established for the block line including the pixel to be encoded (that is, FLG).
= '0'), and if the pixel is determined to be TP (that is, TP = '1'), the predictive coding in step S42 is passed. Subsequently, in the present embodiment, step S43
Then, it is determined whether the processing pixel is the right end of the second line of the block line, for example, and if it is not the right end of the second line, the process returns to step S41, and if it is the right end of the second line, the process ends. That is, in this embodiment, steps S41 to S43 are repeatedly executed until the processed pixel reaches the right end of the second line of the block line, for example.

FIG. 10 is a block diagram showing an example of the structure of the predictive coding unit of this embodiment. In FIG. 10, reference numeral 121 denotes a predictor, which determines a prediction state from surrounding pixel data input from an external line buffer (not shown) and outputs a signal N described later.
Depending on s, the resulting prediction state and the encoded symbol Xn
Is output. Reference numeral 122 denotes an LUTa, which is composed of, for example, a RAM, and stores an index INDEX and a dominant symbol M which are stored according to the prediction state input from the predictor 121.
Output PS. The LUTa 122 has its stored data initialized (eg, INDEX = '0', MPS = '0') by the initialization circuit 120, and the stored data is stored by the updater 125 described later. Will be updated.

Reference numeral 123 denotes an LUTb, which is composed of, for example, a ROM, and outputs a stored inferior symbol P indicating a probability of misprediction according to INDEX input from the LUTa 122. An arithmetic encoder 124 receives the encoded symbols Xn from the predictor 121, the superior symbol MPS from the LUTa 122, and the inferior symbol P from the LUTb 123 to dynamically arithmetically encode the arithmetic encoded data. Cn and signal Ns requesting the next coded symbol
And a signal YN indicating the coincidence state between the coded symbol Xn and the dominant symbol MPS. The arithmetic encoder 1
The signal Ls input to 24 is a signal indicating the final bit of encoded data sent from an external controller (not shown).

Reference numeral 125 denotes an updater, which inputs the signals Ns and YN from the arithmetic encoder 124, the index INDEX and the dominant symbol MPS from the LUTa 122, and outputs L
The index INDEX of the UTa 122 and the dominant symbol MPS are updated. FIG. 11 is a block diagram showing a configuration example of the arithmetic encoder 124. In FIG. 11, reference numeral 130 is a multiplier a, and 131 is a subtracter, which multiplies and subtracts the above-mentioned inferior symbol P and the output of a latch a 136 described later, respectively. An adder 133 adds the output of the subtractor 131 and the output of the output device 141 described later.

133 and 134 are selectors, respectively. The selector a133 selects the data input from the multiplier a130 and the data input from the subtractor 131 according to the output of the exclusive OR circuit EXOR135. The selector b134 outputs the exclusive OR circuit E
According to the output of the XOR 135, the data input from the adder 132 and the data input from the output unit 141 are selected and output. The EXOR 135 inputs the above-described coded symbol Xn and the dominant symbol MPS,
Outputs the exclusive OR of both. In addition, EXOR135
Is the above-mentioned signal YN.

Reference numeral 136 denotes a latch a which latches the output of the selector a133 and the output of the multiplier b139. In addition,
The latch a136 is initialized by the above-mentioned signal Ls. 1
Reference numeral 38 is a comparator which outputs the above-mentioned signal Ns from the data input from the latch a136. 139 is a multiplier b
Then, multiply the data input from the latch a136,
It is sent to the latch a136 again.

137 latches the output of the latch b and the selector b134 and the output of the multiplier c140. The latch b137 is initialized by the above-mentioned signal Ls. 14
Reference numeral 0 denotes a multiplier c, which multiplies the data input from the latch b137 and sends it to the latch b137 again. An output unit 141 outputs the above-described arithmetic code data Cn from the data input from the latch b137.

Although FIG. 10 and FIG. 11 show an example in which the predictive coding unit of this embodiment is configured by hardware, an example in which the predictive coding unit of this embodiment is configured by software will be described. FIG. 12 is a flow chart showing an example of the encoding main routine. In FIG. 12, the present embodiment is
In step S51, the "initialization" subroutine described later for initializing the encoder is executed, in step S52 the encoded symbol Xn is read, in step S53 the "encoding" subroutine described later is executed, and in step S54 the processed pixel is processed. Is the last pixel, and if it is not the last pixel, the process returns to step S52, and if it is the last pixel, the process proceeds to step S55, where the "final code output" subroutine described later is executed, and then the main routine To finish.

FIG. 13 is a flow chart showing an example of the "initialization" subroutine. 13, in the present embodiment, in step S61, for example, the register C = 0, the buffer B = 0, and the counter SC = 0 are initialized, and, for example, the register A = 'FFFF' and the flag STFLG ≠.
After initializing to "0" and the counter CT = 11, the "initializing" subroutine is terminated and the process returns to the main routine.

FIG. 14 is a flow chart showing an example of the "encoding" subroutine. 14, in the present embodiment, in step S71, the LUTa 122 shown in FIG.
From the above-mentioned superior symbol MPS and index IND
EX is read, and the above-mentioned inferior symbol P is determined from the read INDEX. Subsequently, in this embodiment, step S7 is performed.
At 2, the register A1 is updated (A1 ← A × P) and the register A0 is updated (A0 ← A-A1).

Subsequently, in this embodiment, in step S73,
Xn is compared with MPS, and if Xn = MPS (that is, if the predictions match), the process proceeds to step S74, where Xn ≠
In case of MPS (that is, when prediction is wrong), step S
Proceed to 81. If the predictions match (Xn = MPS), the present embodiment updates the register A in step S74 (A ← A).
0) Then, in step S75, the highest bit of register A (hereinafter referred to as "MSB") is determined, and MSB = "0".
If it is, the process proceeds to step S76. If MSB is '1', the "encoding" subroutine is terminated and the process returns to the main routine.

If MSB = '0', the present embodiment updates INDEX according to the NMPS table in step S76, and then proceeds to step S85. If the prediction is wrong (Xn ≠ MPS), in this embodiment, the update of the register C (C ← C + A0) and the update of the register A (A ← A1) are executed in step S81, and step S82 is executed.
Then, the switch SWITCH corresponding to INDEX is determined, and if SWITCH = '0', jump to step S84. If SWITCH = '1', proceed to step S83 to invert MPS at step S83 ( After performing MPS ← 1-MPS), the process proceeds to step S84.

Subsequently, in this embodiment, in step S84, I
After updating NDEX according to the NLPS table, the process proceeds to step S85. Subsequently, in the present embodiment, step S8
After executing the "RENORME" subroutine in step 5,
The "encoding" subroutine is ended and the process returns to the main routine. FIG. 15 is a flow chart showing an example of the "RENORME" subroutine.

In FIG. 15, the present embodiment is based on step S.
At 91, the MSB of the register A is determined and MSB =
If "0", the process proceeds to step S92, and MSB =
In the case of "1", the "RENORME" subroutine is terminated and the process returns to the "encoding" subroutine. MSB =
In the case of "0", in this embodiment, in step S92, the registers A and C are left-shifted and updated, and the counter CT is decremented and updated.

Then, in this embodiment, in step S93,
The value of the counter CT is judged. If CT = 0, the process proceeds to step S94, and if CT ≠ 0, the process returns to step S91. If CT = 0, the present embodiment uses step S9.
After executing the "byte output" subroutine in step 4, the process returns to step S91. That is, in this embodiment, "RENOR
In the "ME" subroutine, the registers A and C are left-shifted and the counter CT is decremented until the MSB of the register A becomes "1".

FIG. 16 is a flow chart showing an example of the "byte output" subroutine. 16, in the present embodiment, in step S401, for example, the value obtained by logically shifting the value of the register C by 19 bits to the right and "1FF" is stored in the register temp. That is,
The register temp is, for example, the bit 19 of the register C.
9 bits from to 27 are stored.

Subsequently, in this embodiment, step S402 is executed.
Then, the value of the register temp is determined and, for example, tem
If p>'FF', the process proceeds to step S403 and tem
If p ≦ 'FF', the process proceeds to step S410. For example, the bit 27 carrier was set (temp>
In the case of “FF”), in this embodiment, in step S403, the value obtained by adding 1 to the value of the register BUFFER is used as an argument.
Executes the "output" subroutine.

Next, in this embodiment, step S404 is executed.
Then, the value of the counter SC is determined, and if SC> 0, the process proceeds to step S405, and if SC = 0, the process proceeds to step S4.
Proceed to 21. If SC> 0, the present embodiment uses step S
The counter SC is decremented at 405, and step S4 is executed.
In step 06, the "output" subroutine is executed using, for example, "00" as an argument, and then the process returns to step S404. That is, in the present embodiment, steps S404 to S406 are repeated until the counter SC reaches 0.

In addition, for example, when the carrier of the bit 27 is not set (temp≤'FF '), the present embodiment determines the register temp again in step S410, and determines, for example, temp <' FF '. In the case of step S412, or in the case of temp = 'FF', the counter SC is incremented in step S411, and then the process proceeds to step S422.

If temp <'FF', this embodiment
In step S412, the "output" subroutine is executed using the value of the register BUFFER as an argument. Subsequently, in the present embodiment, the value of the counter SC is determined in step S413, and if SC> 0, the process proceeds to step S414 and S
If C = 0, the process proceeds to step S421.

If SC> 0, the present embodiment uses step S
The counter SC is decremented at 414, and step S4 is executed.
In step 15, the "output" subroutine is executed using, for example, "FF" as an argument, and then the process returns to step S413. That is, in this embodiment, steps S413 to S415 are repeated until the counter SC reaches 0. continue,
In this embodiment, in step S421, for example, the register t
The result of the logical product of the value of emp and'FF 'is stored in register B
Store in UFFER. That is, the register BUFFE
R stores the lower 8 bits of the register temp, for example.

Next, in this embodiment, step S422 is executed.
Then, for example, after the bit of the output register C is cleared by storing the result of the logical product of the value of the register C and '7FFFF' in the register C, and after setting the counter CT = 8, for example, The "byte output" subroutine is terminated and the process returns to the main routine. FIG. 17 is a flow chart showing an example of the "output" subroutine.

Referring to FIG. 17, this embodiment is based on step S.
At 431, the flag STFLG is determined and STFLG =
In the case of "0", after outputting the data given as an argument in step S433, the "output" subroutine is terminated and the process returns to the "byte output" subroutine. Also, ST
If FLG ≠ '0', the present embodiment uses step S432.
After setting STFLG to '0', the "output" subroutine is terminated and the process returns to the "byte output" subroutine. This is to invalidate the initial value of the register C included in the first "output" process, and the data given as the argument is output from the second time and thereafter.

FIG. 18 is a flow chart showing an example of the "final code output" subroutine, and the "final code output" subroutine is a routine for finally outputting the code remaining in the register C. 18, in the present embodiment, in step S501, for example, the calculation result (C + A-1) and'FF
The result of the logical product of FF0000 'and the register temp
Store to. That is, the register temp is, for example,
The upper 16 bits of the operation result (C + A-1) are stored.

Next, in this embodiment, step S502 is executed.
Then, the value of the register temp is compared with the value of the register C, and if temp <C, the register C is updated (C ← temp + '8000') in step S507, and
If temp ≧ C, register C in step S504
Is updated (C ← temp). Next, in this embodiment, the register C is left-shifted by the value of the counter CT in step S505, the value of the counter C is determined in step S506, and if C>'7FFFFFF', step S507.
If C ≦ '7FFFFFF', go to step S5.
Proceed to 11.

If C>'7FFFFFF', this embodiment executes the "output" subroutine shown in FIG. 17 with the value obtained by adding 1 to the value of the register BUFFER as an argument in step S507. Then, in this embodiment, in step S508, the value of the counter SC is determined, and if SC> 0, the process proceeds to step S509, and if SC = 0, the process proceeds to step S515.

If SC> 0, the present embodiment uses step S
The counter SC is decremented by 509, and step S5 is executed.
In step 10, the "output" subroutine is executed using, for example, "00" as an argument, and then the process returns to step S508. That is, in this embodiment, steps S508 to S510 are repeated until the counter SC reaches 0. Also, C
If ≦ '7FFFFFF', the present embodiment uses step S
At 511, using the value of the register BUFFER as an argument,
Executes the "output" subroutine.

Subsequently, in this embodiment, step S512 is executed.
Then, the value of the counter SC is judged, and if SC> 0, the process proceeds to step S513, and if SC = 0, the process proceeds to step S5.
Proceed to 15. If SC> 0, the present embodiment uses step S
The counter SC is decremented at 513, and step S5 is executed.
At 14, the "output" subroutine is executed using, for example, 'FF' as an argument, and then the process returns to step S512. That is, in the present embodiment, steps S512 to S514 are repeated until the counter SC reaches 0.

Then, in this embodiment, step S515 is executed.
Then, for example, the "output" subroutine is executed with 8 bits from bit 19 to bit 26 of register C as an argument, and in step S516, for example, 8 bits from bit 11 to bit 18 of register C is used as an argument.
Executes the "output" subroutine. As described above, according to the present embodiment, by referring to the encoding target pixel and the reduced pixel only once, for example, by the TP flag detection, the TP determination, and the two-line delay, it is possible to use the TP flag and the TP. Since it can be determined that the hierarchical encoding can be realized by a small-scale hardware.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0066]

As described above, according to the present invention, the coding for predictively coding the first image data according to the characteristics of the first image data and the characteristics of the second image data having a lower resolution. A method and a coding device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a general hierarchical encoder.

FIG. 2 is a block diagram showing a configuration example of a general hierarchical decoder.

FIG. 3 is a block diagram showing a configuration example of a general encoder.

FIG. 4 is a flowchart showing an example of encoding processing of a general encoder.

FIG. 5 is a diagram showing an example of a relationship between an encoding target pixel and a reduced pixel in a general encoder.

FIG. 6 is a flow chart showing an example of setting a flag FLG in a general typical prediction.

FIG. 7 is a flowchart showing an example of determining a TP value for each pixel in a general typical prediction.

FIG. 8 is a flow chart showing an example of a typical prediction according to the embodiment of the present invention.

FIG. 9 is a flow chart showing an example of the encoding process of the present embodiment.

FIG. 10 is a block diagram showing a configuration example of a predictive coding unit according to the present embodiment.

FIG. 11 is a block diagram showing a configuration example of an arithmetic encoder of this embodiment.

FIG. 12 is a flow chart showing an example of an encoding main routine of the present embodiment.

13 is a flow chart showing an example of an "initialization" subroutine of FIG.

14 is a flow chart showing an example of the "encoding" subroutine of FIG.

15 is a flow chart showing an example of a "RENORME" subroutine of FIG.

16 is a flow chart showing an example of a "byte output" subroutine of FIG.

FIG. 17 is a flowchart showing an example of the “output” subroutine of FIG. 16.

18 is a flow chart showing an example of a "final code output" subroutine of FIG.

[Explanation of symbols]

 120 Initialization Circuit 121 Predictor 122 LUTa 123 LUTb 124 Arithmetic Encoder 125 Updater

Claims (3)

[Claims] 1. A second image data having a lower resolution converted from the first image data is generated, and every n lines depending on the characteristics of the first image data and the characteristics of the second image data. A first flag of the first image data is set, and a second flag of a pixel unit is set according to the characteristics of the first image data and the characteristics of the second image data. An encoding method, wherein the first image data is predictively encoded according to the flag. 2. The encoding method according to claim 1, wherein the first flag is set every two lines. 3. A first detecting feature of the first image data
Detecting means, second detecting means for detecting the characteristics of the second image data having a lower resolution converted from the first image data, the characteristics detected by the first detecting means, and Second
The first according to the characteristics detected by the detection means of
And a coding means for predictively coding the image data of 1.