JP3246910B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a bipolar transistor (hereinafter referred to as a BIP device) formed on a green substrate, for example, in an SOI (Silicon-On-Insulator) film.

[0002]

2. Description of the Related Art A BIP device formed on an SOI film has a low stray capacitance, so that a BIP device formed on a bulk silicon substrate can be used.
High-speed operation is expected as compared with the IP device. For example, IEE
E, EDL-8, NO. 3, p. 104, 1987, byJ. C. Sturm
et al. 9 is shown in FIG. In this, a base region B is formed by laminating a p-type layer 63 and ap + -type layer 632 on a silicon substrate 1 with an SiO 2 film 2 interposed therebetween. On both sides of this region, n + type layers 68, 67
, An emitter region E and a collector region C are formed. The lead wiring 60 is connected to these regions. 61 is an interlayer insulating film. However, SOI lateral BIP devices, despite being considered inherently superior, did not exhibit the expected rough performance due to the disadvantages described below. That is, since the impurity distribution of the base region 631 is formed at a uniform concentration from the emitter 68 to the collector 67, the carrier transit time is large,
That is, the high frequency characteristics such as the cutoff frequency are lowered. These are due to the fact that it is structurally difficult to change the impurity distribution in the direction parallel to the surface of the substrate 1.

[0003]

The conventional semiconductor device has a problem that the traveling time of the carrier in the base region is long, and therefore, the high-speed operation is inferior. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device which has a short carrier base traveling time and is extremely excellent in high-speed operation. Another object is to provide a method for manufacturing a semiconductor device in which such a semiconductor device can be easily formed.

[0004]

To achieve the above object, the present invention provides a semiconductor substrate, an insulating substrate formed on the semiconductor substrate, and a first conductive layer formed on the surface of the insulating substrate. An emitter region of a first conductivity type, a collector region of a first conductivity type formed on the surface of the insulating substrate so as to be separated from the emitter region, and a surface of the insulating substrate between the emitter region and the collector region. A first base region of a second conductivity type which is adjacent to and protrudes in a direction perpendicular to the substrate direction of the insulating substrate; and the first base formed on the first base region The second conductivity type second having an impurity concentration higher than the impurity concentration of the region.
A bipolar transistor having a base region, a first conductivity type drain region formed on the surface of the insulating substrate, and a first conductivity type source formed on the surface of the insulating substrate so as to be separated from the drain region. A region, a channel formation scheduled region formed adjacent to the insulating substrate surface between the drain region and the source region, and a gate insulating film formed on the channel formation scheduled region; A MOS transistor having a gate electrode formed on a gate insulating film, the impurity concentration distribution of the first base region being lower on the collector region side than the emitter region, and A low-concentration portion having a low impurity concentration of the first conductivity type is formed on a side in contact with the first base region;
The thickness t0 of the channel forming region, the collector region, and the emitter region in a direction perpendicular to the planar direction of the insulating substrate is substantially the same, and this t0 is 100 ° ≦
It is intended to provide a semiconductor device characterized in that t0 ≦ 3000 °.

(Operation) The impurity concentration in the base region of the BIP element is made lower on the collector side than on the emitter side.
Since it is not increased more than necessary, the traveling time of carriers in the base region can be shortened, and high-frequency characteristics such as cutoff frequency can be improved. Further, since ion implantation is performed obliquely into the base region in order to obtain such an impurity concentration distribution, the BIP element can be formed very easily. Further, since the emitter / collector region of the BIP element and the source / drain region of the FET are formed from the same semiconductor layer, the manufacturing process is simple.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described by way of examples. FIG. 1 shows a plan view of a semiconductor device according to a first embodiment of the present invention. In addition, respective cross sections AA 'and BB'
2 (a), FIG. 2 (b), and FIG.
(C). In this semiconductor device, a MOSFET is formed on an SOI film formed on a silicon substrate 1 via an SiO 2 film 2.
So-called BiCMO incorporating NPNBIP element
It is S. The NPNBIP element has a P-type Si layer (internal base region) 39 and a P + -type Si layer (external base region).
35, and n + formed on both sides of the base region.
It has a collector region 72 and an emitter region 82 of a type Si layer. This BiCMOS has three features. First
In addition, the p-type Si layer 39, which is a part of the base region, has a lower impurity concentration on the collector region 72 side than the emitter region 82. Here, this was achieved by forming the p-type ion implantation layer 6 on the p-type Si layer 39. As a result, the carrier traveling time can be shortened, and high-frequency characteristics such as a cutoff frequency can be improved. Second, near the base region of each of the collector region 72 and the emitter region 82, a region 7 having a lower impurity concentration than these regions is provided.
3,83 are formed. As a result, in the BIP element having the conventional structure as shown in FIG. 9, since the impurity concentration on the collector side of the base-collector junction is high, a high electric field is easily generated at this junction and avalanche breakdown should occur. Although the open-circuit emitter-collector breakdown voltage (VECO) has a problem of being extremely low, such a problem hardly occurs in the BIP element of the present embodiment due to the above-described structure.

Third, the power consumption of the BIP element alone increases remarkably with the integration, causing a serious problem. In particular, the power dissipation problem is more serious on the SOI film due to poor heat dissipation. In order to reduce the power consumption, it is conceivable to use the same with the CMOS structure. Therefore, in this embodiment, the BIP
Since all elements are mixed with CMOSFET, all BI
The overall power consumption can be greatly reduced as compared with the case where the P element is used. By the way, the channel region 38 of the MOSFET and the emitter / collector region 8 of the BIP element
The film thicknesses (t0) of the layers 2 and 72 are preferably the same, but it is particularly preferable to set the film thickness to the empirical formula (A) shown below.

[0008]

(Equation 2) Here, φ: Fermi level of the semiconductor, q: electron charge,
NA: impurity concentration of the semiconductor, ε: dielectric constant of semiconductivity It is preferable that the following formula (B) be established between the thickness T of the internal base region 39 and t0. T ≧ 2 · t0 (B) However, when 100 ° ≦ t0 ≦ 3000 ° When t0 becomes thinner by 100 mm, hFE decreases and LS
Only an unsuitable switching element for I can be obtained. On the other hand, when t0 exceeds 3000 °, the characteristics become close to those of a transistor formed on a bulk Si substrate,
This is because high-speed operation utilizing the advantage of the SOI thin film cannot be performed. Further, the width W of the base region is more preferably t0 or less. Next, a method for manufacturing the semiconductor device according to the present embodiment will be specifically described with reference to FIGS. First, oxygen ions are implanted into a P-type single crystal silicon substrate 1 at an acceleration voltage of 180 kV and a dose of 2 × 10 18 cm −2, and then an SiO 2 layer 2 having a thickness of 4000 ° and a thickness of 2500 ° are annealed at 1300 ° C. for 20 hours. SOI
A film 31 is formed. This formation method is not limited to ion implantation. A CVD-Si02 film is formed on a Si substrate, and poly-Si is further deposited thereon.
Alternatively, the SOI film may be formed by single crystallization in a solid phase.
(FIG. 3A) Next, boron ions are accelerated at 50 kV and the dose is 2 × 1.
Ion implantation is performed at 011 cm−2, annealing is performed at 1000 ° C. for 2 hours, and the concentration of the SOI film is about 1017 cm 2.
-3 P-type region 32. Next, after implanting boron ions at an acceleration voltage of 30 kV and a dose of 3 × 10 15 cm −2, annealing is performed at 900 ° C. for 30 minutes to form a high-concentration P-type region 33 on the surface of the SOI film 31.

[0009] Next, after depositing a CVD oxide layer at 4000 ° C, a resist pattern 51 is formed in a portion to be a base region of the BIP element by using a well-known patterning technique, and further, by using a reactive ion etching technique. A CVD oxide film 41 is formed. (FIG. 3B) The exposed SOI films 32 and 33 are further etched to
A mold layer 34 is formed. At this time, the remaining thickness of the SOI film 32 was 1000 Å, and the P-type high-concentration region 33 was removed from portions other than the base region of the BIP element. (FIG. 3C) Next, after the resist 51 is removed, the BIP element and the MOS are removed.
A region to be an element is covered with resist patterns 52 and 53,
The SOI film is removed by etching, and island-shaped element regions 36 and 3 are formed.
7 was shaped. (FIG. 4 (a)). Further, the MOS element portion and the collector region of the BIP element are covered with resists 54 and 55, and boron ions are obliquely inclined from the direction perpendicular to the substrate, for example, at an angle of 45 degrees, at an acceleration voltage of 50 kV and a dose of 1 × 10 13 cm −2. Implantation was performed to form an ion implantation layer 6. At this time, the silicon substrate 1 may be rotated at the time of ion implantation, and the ion implantation may be performed on the base regions of the BIP elements facing various directions. (FIG. 4B) Next, oxide films 111 and 112 are formed to have a thickness of 200 ° and a boron-doped polysilicon film is deposited.
By patterning, the gate electrode 42 of the MOS element and BI
A base electrode 41 of the P element was formed. Next, phosphorus ions are implanted into the substrate 1 from a substantially vertical direction at an acceleration voltage of 50 kV and a dose of 1 × 10 13 cm −2, so that an N-type MOS device becomes a so-called LDD (Lightly-Doped Drain) region.
Type low concentration diffusion regions 91 and 101 and BIP
Low-concentration N-type regions 71 and 8 for increasing the breakdown voltage of the device
1 was formed. (FIG. 5 (a)) Next, after forming a CVDSi02 film with a thickness of 2000.degree., SiO2 114 is formed on the gate side wall of the MOS device by the reactive ion etching technique, and the SOI film step in the base region of the BIP device is formed. SiO2 113 was formed in each part. Further, arsenic ions are implanted at an accelerating voltage of 60 kV and a dose of 3 × 10 16 cm −2, annealed at 900 ° C. for 1 hour, and the source / drain 92 and 102 of the MOS device, the emitter and the collector of the BIP device, and the collector. Parts 82 and 72 were formed simultaneously. (FIG. 5B) Next, the CVD SiO2 film 511 as an interlayer insulating film or B
After laminating the PSG film, an aluminum wiring 60 was formed by a known method, and finally, a PSG film 512 for passivation was deposited to complete the device. (FIG. 2 (a)) FIG. 6 (a) shows an investigation of the impurity concentration distribution of the cross section (as viewed from the direction shown in FIG. 2 (a)) of the BIP element thus obtained. FIG. 6B is a view similar to that of the conventional BIP element shown in FIG. 9 for comparison. As is clear from this figure, in the device of this embodiment, the impurity concentration in the base region is lower on the collector region side, and is gradually reduced from the emitter region toward the collector region. It can also be seen that a low impurity concentration layer having a lower impurity concentration than the collector region can be formed between the base region and the collector region. FIG. 7 shows the impurity concentration distribution of the MOSFET formed simultaneously with the BIP element of this embodiment. It can be seen that a low concentration impurity layer has been formed between each of the source / drain region and the channel formation region. Thereby, the MOSFE having the LDD structure is formed.
T can be constructed.

According to the manufacturing method of this embodiment, a high-performance CMOS
The FET and the high-performance BIP element can be formed simultaneously, and an unprecedented high-performance BiCMOS structure can be realized. Furthermore, in order to make use of the features of the lateral BIP transistor, the MOSI is formed by using an SOI film and minimizing the number of processes.
Simultaneous fabrication with the structure is possible. Further, by forming a low-concentration impurity region in the collector region simultaneously with the LDD structure of the MOS structure, the withstand voltage of the BIP element can be improved, and
The reliability of the OS element is also realized without complicating the element manufacturing process. Here, the impurity concentration in the base region is changed by oblique ion implantation, but this angle is not limited to 45 °, and an angle such that channeling does not occur, for example, an angle of 20 ° to 80 ° with the substrate surface. °
Is more preferable. Next, a second embodiment of the present invention will be described with reference to FIG. The device according to the present embodiment realizes a complementary BiCMOS structure. A detailed description of the same parts as in the previous embodiment will be omitted below. PchMO
The SFET is indicated by the 50's of the number assigned to the same part as the NchMOSFET. Also, PNPBIP is similarly NP
The 50th generation number of NBIP was added. This BiC
A major feature of the MOS structure different from the previous embodiment is that, in addition to the base region of the BIP element being left thicker than the emitter / collector region, the source / drain region of the MOSFET is left thicker than the channel forming region. This was obtained by shaving and forming semiconductor layers having the same thickness in the same etching step.

In this embodiment, in addition to the effects obtained in the previous embodiment, the present invention can be applied not only to the N-type MOSFET and the NPN-type BIP element but also to the P-type MOSFET and the PNP-type BIP element. You can build everything on top. The present invention is not limited to the above-described embodiment, and may be as follows. Here, the insulating substrate is made of SiO2 on the surface of a Si substrate.
Although a substrate having a film is used, any substrate having an insulating surface may be used. For example, an insulating single crystal substrate such as sapphire or spinel may be used. The semiconductor material used for element formation is not limited to Si, but may be another group IV semiconductor such as Ge, C, or a compound semiconductor such as SiGe, GaAs, InP, or the like. The element formed at the same time as the BIP element is not limited to the MOSFET, but may be another FET such as a MIS type FET, a Schottky junction type FET or an SIS type FET.

[0012]

According to the present invention, a semiconductor device excellent in high speed can be obtained.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing the first embodiment of the present invention.

FIG. 3 is a sectional view of a first embodiment of the present invention in the order of steps.

FIG. 4 is a sectional view of a first embodiment of the present invention in the order of steps.

FIG. 5 is a sectional view of a first embodiment of the present invention in the order of steps.

FIG. 6 is a diagram illustrating a first embodiment of the present invention.

FIG. 7 is a diagram illustrating a first embodiment of the present invention.

FIG. 8 is a sectional view showing a second embodiment of the present invention.

FIG. 9 is a sectional view showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Si substrate 2 ... SiO2 film 35, 39 ... Base region 38 ... Channel formation region 42 ... Gate electrode 51 ... Interlayer insulating film 6 ... Ion implantation layer 72 ... Emitter region 82 ... Collector region 92 ... Source region 102 ... Drain region 60 … Electrode wiring

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 27/08 331 H01L 29/80 B 29/73 29/786 29/812 (56) References JP-A-2-49464 (JP JP-A-60-57643 (JP, A) JP-A-1-298767 (JP, A) JP-A-1-192171 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H01L 21/8222 H01L 21/331 H01L 21/338 H01L 21/8249 H01L 27/06 H01L 27/08 331 H01L 29/73 H01L 29/786 H01L 29/812

Claims (4)

(57) [Claims] A semiconductor substrate; an insulating substrate formed on the semiconductor substrate; an emitter region of a first conductivity type formed on the surface of the insulating substrate; and an emitter region on the surface of the insulating substrate. A first conductivity type collector region formed at a distance, and a direction adjacent to the insulating substrate surface between the emitter region and the collector region and orthogonal to the substrate direction of the insulating substrate. A first base region of a second conductivity type protruding from the first base region; and a second conductivity type formed on the first base region and having an impurity concentration higher than that of the first base region. A bipolar transistor having a second base region, a first conductivity type drain region formed on the surface of the insulating substrate, and a first region formed on the surface of the insulating substrate so as to be separated from the drain region. A conductive type source region; a channel formation region formed on the surface of the insulating substrate between the drain region and the source region so as to be adjacent thereto; and a gate insulation formed on the channel formation region. A semiconductor device having a film and a MOS transistor having a gate electrode formed on the gate insulating film, wherein an impurity concentration distribution of the first base region is lower on the collector region side than on the emitter region; A low-concentration portion having a low impurity concentration of a first conductivity type is formed on a side of the emitter region in contact with the first base region, and the insulated substrate of the channel formation planned region, the collector region, and the emitter region Are substantially the same in a direction perpendicular to the plane direction of the above, and this t0 is 100 ° ≦
A semiconductor device, wherein t0 ≦ 3000 °. 2. The semiconductor device according to claim 1, wherein a thickness T of said first base region in a direction perpendicular to a plane direction of said insulating substrate satisfies T ≧ 2t0. 3. The width W of the first base region in a direction in which the collector region and the emitter region are opposed to each other is W ≧ t0.
3. The semiconductor device according to claim 1, wherein: 4. When the Fermi level of a semiconductor is φF, the impurity concentration of the semiconductor is NA, the dielectric constant of the semiconductor is ε, and the charge of electrons is q, these and t0 have the following relationship. The semiconductor device according to claim 1. (Equation 1)