JP3240837B2 - Display semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display semiconductor device used for a drive substrate of an active matrix type liquid crystal display device. More specifically, the present invention relates to an input terminal structure of an external signal provided in a display semiconductor device.

[0002]

2. Description of the Related Art The structure of a conventional display semiconductor device will be briefly described with reference to FIG. As shown, the display semiconductor device has a row-shaped gate line X and a column-shaped signal line Y.
And a matrix of pixel arrays arranged at the intersections of the two. Each pixel is, for example, a fine pixel electrode PX.
L and a thin film transistor Tr for driving the same.
A single vertical drive circuit 101 is connected to one end of each gate line X, and outputs a gate pulse V _N , V _{N + 1} ,
V N _{+ 2,} and sequentially applies the ... to the gate line X to selectively drive the pixels in each row. The vertical drive circuit 101 outputs the above-described gate pulse by sequentially transferring the vertical start signal VST in synchronization with clock signals VCK and VCKX externally input. Note that VCK and VCKX are clock signals of opposite polarities. On the other hand, the video line 10 is connected to the end of each signal line Y via a horizontal switch HSW.
2 is connected, and a video signal VS input from the outside
Receive IG supply. The horizontal switch HSW is controlled to be opened and closed by a horizontal scanning circuit 103, and sequentially scans each signal line Y and sequentially selects a pixel of one row and a video signal VS in a column sequence.
Write IG. The horizontal scanning circuit 103 outputs a sampling pulse for controlling opening and closing of the horizontal switch HSW by sequentially transferring the horizontal start signal HST in synchronization with predetermined clock signals HCK and HCKX. The horizontal scanning circuit 103 and the horizontal switch HSW form a horizontal driving circuit.

[0003]

FIG. 6 is an operation timing chart of the conventional display semiconductor device shown in FIG. As shown in the figure, the horizontal start signal HST is input to the horizontal scanning circuit 103 every horizontal period, and starts writing a video signal to pixels of one row. On the other hand, the vertical drive circuit 101 outputs a gate pulse every horizontal period by sequentially transferring the vertical start signal VST. Although the gate pulse basically has a rectangular waveform, the waveform is actually rounded because the resistance component r is included in the gate line X. This rounding becomes more remarkable as the distance from the input side of the vertical drive circuit 101 increases. The timing chart of FIG. 6 shows gate pulses observed in the first row near the vertical drive circuit 101 side, the middle middle row, and the last row near the other end. In the first row, each gate pulse V _N ,
_{VN + 1} , _{VN + 2} ,... Maintain a substantially rectangular shape and are temporally separated from each other. However, in the middle row, the gate pulse waveform becomes blunt due to the resistance component included in the gate line X. In particular, the last stage row becomes the worst condition for the resistance component r is added to the series, starting gate pulse waveform rounding is remarkable V _N and late gate pulse V _{N + 1} will overlap. Similarly, V _{N + 1} and V _{N + 2} also overlap. In such a state, there is a problem that shading occurs in a displayed image or a mixture of video signals occurs between rows of pixels, thereby significantly deteriorating the image quality.

In particular, when a bidirectional type is adopted as the horizontal scanning circuit 103 shown in FIG. 5, signal mixing becomes remarkable. In the bidirectional type, each signal line Y is arranged along a forward direction (right direction in the drawing) from one end to the other end of the gate line X or a reverse direction (left direction in the drawing) from the other end to the one end. Scanning is performed sequentially to enable left-right inverted display of the image. This left-right inversion function is required when, for example, an active matrix type liquid crystal display device is applied to a light valve of a projector. As described above, the worst condition occurs because the resistance component r is added in series in the last stage, and the waveform rounding is conspicuous, and the first gate pulse and the second gate pulse overlap. In such a state, a problem arises when reverse point sequential scanning is performed on a pixel row. As shown in the timing chart of FIG. 6, when for example, the gate pulse V _N Advance does not fall up completely, the gate pulse V _{N + 1} of the next onset are starting up. At this time, the horizontal start signal HST
Is input, and writing of the video signal to the pixels on the (N + 1) th row starts. However, when the HST is inputted, the gate pulse V _N Advance has not fallen yet, the video signal will be also written to the pixels of the N rows. As a result, another video signal assigned to the (N + 1) th row is written to the pixels in the Nth row, and signal mixing occurs.

FIG. 7 schematically shows the mixing of the video signal described above. As described above, in the case of the forward scanning, the horizontal start signal HST is input in a state where there is no rounding of the gate pulse, so that there is no fear of mixing of video signals.
However, in the case of reverse scanning, writing starts from the last row where the gate pulse becomes remarkable, so that an overlap occurs between the input point of the horizontal start signal HST and the falling point of the gate pulse of the previous row. Would. As a result, the video signal assigned to the row is written in the previous row pixel, and as shown in the figure, the image is disturbed due to the mixing of the video signals on the right end of the screen.

In order to prevent such rounding of the gate pulse, a structure in which vertical driving circuits are provided on both sides of the gate line has been considered, and FIG. 8 shows an example thereof. The display semiconductor device includes a pixel array unit that forms a screen 201, a peripheral circuit unit that drives the pixel array unit, and a plurality of input terminals 202 that supply external signals to the pixel array unit. The pixel array section has pixels arranged in a matrix. The peripheral circuit section has vertical driving means for selectively driving each row of pixels in accordance with the supplied signal, and horizontal driving means for writing and driving the selected pixels in column order. The vertical driving means is the screen 201
Of vertical drive circuits 203 and 204 arranged on both sides of the
, And each row of pixels is simultaneously selected and driven from both sides.
On the other hand, the horizontal drive means comprises a single horizontal drive circuit 205.

In the above-described display semiconductor device, an input terminal is independently provided for each of the pair of vertical drive circuits 203 and 204. In the example of FIG. 8, input terminals a, b, and c are provided for one vertical drive circuit 203,
A vertical start signal and a vertical clock signal were input.
For the other vertical drive circuit 204, input terminals d,
e and f are provided, and a vertical start signal and a vertical clock signal are similarly input.

However, in the above-described configuration, shading and mixing of image signals can be prevented by providing two vertical driving circuits, but the number of input terminals is increased as compared with the configuration having a single vertical driving circuit. Other drawbacks have arisen. First, the area occupied by the input terminals with respect to the substrate constituting the display semiconductor device is increased, so that the substrate is more susceptible to electrostatic damage. Second, as the number of input terminals increases, the number of inspection steps increases accordingly, which is disadvantageous in the manufacturing process. Third, the number of internal wirings connecting the input terminals to the drive circuit unit increases, and defects are likely to occur in the assembly and mounting process.

[0009]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, the present invention enables a pair of vertical drive circuits to be formed on a display semiconductor device without increasing the number of input terminals. With the goal. The following measures were taken to achieve this purpose. That is, the display semiconductor device according to the present invention is assembled into a panel using a seal material.
In addition, as a basic configuration, the image processing apparatus includes a pixel array unit that forms a screen, a peripheral circuit unit that drives the pixel array unit, and a plurality of input terminals that supply external signals to the peripheral circuit unit. The pixel array section has pixels arranged in a matrix.
The peripheral circuit section includes a vertical driving unit for selectively driving each row of pixels in accordance with a supplied signal, and a horizontal driving unit for writing and driving the selected pixels in column order. The vertical driving means includes a pair of vertical driving circuits disposed on both sides of the screen, and selectively drives each row of pixels from both sides simultaneously. As a feature of the present invention, the plurality of input terminals are commonly assigned to both vertical drive circuits, and
And a common input terminal disposed at a position outside the sealing material . Further, an internal wiring is provided across the seal material to connect the common input terminal to each vertical drive circuit. The display semiconductor device having such a configuration is used, for example, as a drive substrate of an active matrix liquid crystal display device.

In the embodied invention, the internal wiring directly connects the shared input terminal to one of the vertical driving circuits, and the internal wiring indirectly connects to the other vertical driving circuit via the one vertical driving circuit. And indirect internal wiring. In another embodiment, the internal wiring has a branch internal wiring that branches the common input terminal to both vertical drive circuits. In addition to the branch internal wiring, there is an auxiliary internal wiring for auxiliary connecting the two vertical drive circuits to each other.

[0011]

In the present invention, a pair of vertical drive circuits are arranged on both sides of the screen, and each row of pixels is selectively driven from both sides simultaneously. As a result, shading of an image and mixing of a video signal can be suppressed, and image quality can be greatly improved, as compared with a method in which a single vertical driving circuit drives from one side of the screen. In addition, a common input terminal that is commonly assigned to both the vertical drive circuits is provided, and an internal wiring that connects the common input terminal to each vertical drive circuit is provided. As a result, the number of input terminals can be reduced as compared with the conventional example in which independent input terminals are separately provided, which is advantageous in terms of a manufacturing process, quality, and reliability. In this case, it is important to reduce the resistance of the internal wiring, and a start signal and a clock signal can be supplied to both vertical drive circuits at the same timing. As a result, both the vertical driving circuits can operate in synchronization with each other, and can perform selective driving of each pixel row that is timing-matched. In particular, since the vertical drive circuit uses a clock signal having a lower frequency than the horizontal drive circuit, there is no problem such as signal delay due to routing of internal wiring.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic plan view showing a first embodiment of a display semiconductor device according to the present invention. As shown in the drawing, the display semiconductor device 1 is configured using an insulating substrate 2 such as quartz or glass, and includes a pixel array section 4 included in a screen 3, a peripheral circuit section for driving the same, and an external circuit section. And a plurality of input terminals 5 for supplying signals from the integrated circuit.

The pixel array section 4 has pixels arranged in rows and columns. Each pixel includes a pixel electrode PXL and a switching thin film transistor Tr. Further, it has gate lines X arranged in rows and signal lines Y arranged in columns. The gate electrode of each thin film transistor Tr is connected to the corresponding gate line X, the source electrode is connected to the corresponding signal line Y, and the drain electrode is connected to the corresponding pixel electrode PXL.

The peripheral circuit section has vertical driving means for selectively driving each row of pixels in accordance with a signal supplied from the input terminal 5, and horizontal driving means for writing and driving the selected pixels in column order. I have. In the present invention, the vertical driving means comprises a pair of vertical driving circuits 6 and 7 arranged on both left and right sides of the screen 3, and selectively drives each row of pixels from both sides simultaneously. Specifically, the first vertical drive circuit 6 is connected to the left end of the gate line X, while the second vertical drive circuit 7 is connected to the right end of the gate line X. The vertical drive circuits 6 and 7 sequentially output gate pulses at the same timing, and open / close the thin film transistor Tr for each row to perform the above-described pixel selective drive. Since gate pulses are input from both sides of each gate line X at the same time, overlapping due to rounding of the waveform, which has conventionally been a problem, is suppressed. On the other hand, the horizontal driving means comprises a single horizontal driving circuit 8 and is connected to one end of the signal line Y. The horizontal drive circuit 8 samples and distributes a video signal supplied from the outside via the input terminal 5 to each signal line Y, and writes and drives selected pixels in column order.

As a feature of the present invention, the plurality of input terminals 5 include common input terminals 5a, 5b, 5c commonly assigned to both the vertical drive circuits 6, 7. These shared input terminals 5a, 5b and 5c supply a vertical start signal and vertical clock signals of opposite polarities to the vertical drive circuits 6 and 7, respectively. Although not shown,
A common input terminal for supplying a power supply voltage or the like to the vertical drive circuit is also provided. In addition, input terminals 5d, 5e, and 5 for supplying a predetermined signal and a power supply voltage to the horizontal drive circuit 8 are provided.
f,... are also provided. The common input terminals 5a, 5b,
5c is connected to each of the vertical drive circuits 6, 7 using internal wiring. In this embodiment, the shared input terminals 5a, 5b, 5
a direct internal wiring 9 for directly connecting c to the first vertical drive circuit 6
R and the second vertical drive circuit 7 via the first vertical drive circuit 6
And an indirect internal wiring 9S that is indirectly connected to the power supply. That is, signals applied to the shared input terminals 5a, 5b, 5c from an external timing generator (not shown) or the like are first supplied directly to the first vertical drive circuit 6 via the internal wiring 9R to control the operation. I do. Next, a signal is transferred to the second vertical drive circuit 7 via the first vertical drive circuit 6 and then via the indirect internal wiring 9S. Since the length of the indirect internal wiring 9S is longer than that of the direct internal wiring 9R, the resistance may be increased. However, since the lower side of the normal screen 3 is often a dead space, a wide wiring using, for example, aluminum or an aluminum alloy is possible, and the resistance value can be sufficiently reduced. Therefore, when a clock signal having a low frequency is used as in the vertical driving circuit, the delay in signal transfer does not substantially matter, and the first vertical driving circuit 6 and the second vertical driving circuit 7 are sufficiently synchronized in timing. are doing.

In the present invention, the shared input terminals 5a, 5b, 5c are assigned to both the vertical drive circuits 6, 7, and the independent input terminals shown in FIG. 8 are assigned to the respective vertical drive circuits. It has the following advantages. First, since the number of input terminals connected to the vertical drive circuit is reduced, the area of the input terminals occupying the insulating substrate 2 is reduced, and the input terminals are more resistant to electrostatic damage. In addition, since the number of input terminals is reduced, the inspection process can be shortened. Further, the driving can be performed using the same timing generator as the timing generator connected to the display semiconductor device incorporating the single vertical drive circuit shown in FIG. In addition, since the common input terminal is used, the first vertical drive circuit 6
And no relative delay appears in the operation timing of the second vertical drive circuit 7. As can be understood from the above description, by using a pair of vertical drive circuit configurations, it is possible to realize an image quality superior to that of a single vertical drive circuit configuration without the problem that has conventionally occurred.

FIG. 2 is a schematic plan view showing a second embodiment of the display semiconductor device according to the present invention. The basic configuration is the same as that of the first embodiment shown in FIG. 1, and corresponding parts are denoted by corresponding reference numerals to facilitate understanding.
The difference is that the shared input terminals 5a, 5b, 5c are branched and connected to both the vertical drive circuits 6, 7 using the branch internal wiring 9T. In this way, the first vertical drive circuit 6 and the second vertical drive circuit 7 are connected to the shared input terminals 5a, 5b,
5c can be connected under substantially equal conditions, and the operation timings of both can be completely synchronized.

FIG. 3 is a schematic plan view showing a third embodiment of the display semiconductor device according to the present invention. Basically, it is the same as the second embodiment shown in FIG. 2, and corresponding parts are denoted by corresponding reference numerals to facilitate understanding. The difference is that, apart from the branch internal wiring 9T, an auxiliary internal wiring 9P for mutually connecting the two vertical drive circuits 6, 7 is provided. By utilizing the dead spaces left above and below the screen 3, the pair of vertical driving circuits 6, 7 are
The resistance is further reduced by interconnecting the internal wirings 9T and 9P in a double manner.

Finally, FIG. 4 is a schematic sectional view showing an example of an active matrix type liquid crystal display device assembled using the display semiconductor device according to the present invention. As shown, the liquid crystal display device has a panel structure including a driving substrate, a counter substrate 21, and a liquid crystal 22 held between them. As the driving substrate, for example, the display semiconductor device 1 shown in FIG. 1 is used. That is, a pair of vertical drive circuits 6 and 7 and a pixel array section forming a screen are integratedly formed on the inner surface of the drive substrate. The pixel array section includes pixel electrodes PXL arranged in a matrix and corresponding switching thin film transistors Tr. On the other hand, a counter electrode 23 is formed entirely on the inner surface of the counter substrate 21. Counter substrate 2
1 and the driving substrate are bonded to each other by a sealant 24. Although not shown, the input terminals are arranged outside the seal member 24. Therefore, a part of the wiring connecting the outer input terminal and the inner drive circuit section crosses the seal member 24. In the present invention, by sharing a part of the input terminals, the number of wirings crossing the sealing material can be reduced,
Problems such as liquid crystal leakage and breakage of seals that occur during panel assembly are also reduced.

[0020]

As described above, according to the present invention, a pair of vertical drive circuits are arranged on both sides of the screen, and each row of pixels is simultaneously selected and driven from both sides. In this case, a common input terminal is commonly assigned to both the vertical drive circuits, and an internal wiring connecting the common input terminal to each vertical drive circuit is provided. With such a configuration, there is an effect that the display image quality can be improved as compared with a single vertical drive circuit configuration. Also, it is advantageous in terms of measures against static electricity as compared with a structure in which input terminals are provided independently for a pair of vertical drive circuits. Further, the inspection process can be shortened. Further, defects generated when assembling and mounting as a liquid crystal panel can be reduced. In addition, the degree of freedom in designing peripheral circuits such as a timing generator increases. Finally, the degree of freedom in designing the layout of the display semiconductor device itself is increased.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of a display semiconductor device according to the present invention.

FIG. 2 is a schematic plan view showing a second embodiment of the display semiconductor device according to the present invention.

FIG. 3 is a schematic plan view showing a third embodiment of the display semiconductor device according to the present invention.

FIG. 4 is a schematic cross-sectional view showing an example of an active matrix liquid crystal display device assembled using the display semiconductor device according to the present invention.

FIG. 5 is a circuit diagram illustrating an example of a conventional display semiconductor device.

FIG. 6 is a timing chart for explaining the operation of the conventional example shown in FIG. 5;

FIG. 7 is a schematic diagram for explaining a problem of the conventional example shown in FIG. 5;

FIG. 8 is a schematic plan view showing another example of the conventional display semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Display semiconductor device 2 Insulating substrate 3 Screen 4 Pixel array part 5 Input terminal 5a Shared input terminal 5b Shared input terminal 5c Shared input terminal 6 First vertical drive circuit 7 Second vertical drive circuit 8 Horizontal drive circuit 9R Direct internal wiring 9S Indirect internal wiring 9T Branch internal wiring 9P Auxiliary internal wiring 21 Counter substrate 22 Liquid crystal

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-271569 (JP, A) JP-A-3-289698 (JP, A) JP-A-4-159520 (JP, A) 110486 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) G02F 1/133 550 G02F 1/1345 G02F 1/1368 G09G 3/20 G09G 3/36

Claims (5)

(57) [Claims] 1. A pixel array, comprising: a pixel array unit forming a screen; a peripheral circuit unit for driving the pixel array unit; and a plurality of input terminals for supplying a signal to the peripheral circuit unit from outside. The peripheral circuit section has vertical driving means for selectively driving each row of pixels in accordance with a supplied signal, and horizontal driving means for writing and driving the selected pixels in column order. the has, shea - a semiconductor device for display is assembled in the panel with the sealing material, the vertical drive unit from both sides of each row of pixels comprises a pair of vertical drive circuit arranged on both sides of the screen At the same time, the plurality of input terminals are commonly assigned to both the vertical drive circuits and are located outside the sealing material.
Display semiconductor device, characterized in that provided internal wiring arranged a includes a shared input terminals, that across the sealing material connecting the co input terminal to the vertical drive circuit. 2. The internal wiring includes a direct internal wiring for directly connecting the shared input terminal to one vertical drive circuit, and an indirect internal wiring for indirectly connecting to the other vertical drive circuit via the one vertical drive circuit. 2. The display semiconductor device according to claim 1, comprising: 3. The display semiconductor device according to claim 1, wherein said internal wiring has a branch internal wiring for branch-connecting said common input terminal to both vertical drive circuits. 4. The display semiconductor device according to claim 3, wherein said internal wiring has an auxiliary internal wiring for mutually connecting said two vertical drive circuits to each other separately from said branch internal wiring. 5. A driving substrate, an opposing substrate, and a sealing material.
The driving substrate has a panel structure including a liquid crystal held between the two, and the driving substrate includes a pixel array unit that forms a screen, a peripheral circuit unit that drives the pixel array unit, and the peripheral circuit. A plurality of input terminals for supplying a signal from the outside to the unit, wherein the pixel array unit has pixels arranged in a matrix, and the peripheral circuit unit responds to the supplied signal. Vertical drive means for selectively driving each row of pixels and horizontal drive means for writing and driving the selected pixels in column order, wherein the vertical drive means comprises a pair of vertical drive circuits arranged on both sides of the screen And simultaneously driving each row of pixels from both sides simultaneously, and wherein the plurality of input terminals are commonly assigned to both vertical drive circuits and located outside the seal material.
A liquid crystal display device, comprising: a common input terminal disposed in the liquid crystal display device; and an internal wiring for connecting the common input terminal to each vertical drive circuit across the sealing material .