JP3234528B2 - Method for manufacturing split gate transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a split gate.
And a method for manufacturing a type transistor .

[0002]

2. Description of the Related Art In recent years, ferroelectric memories (Ferro-electric memories) have been developed.
Random Access Memory), EPROM (Erasable and
Programmable Read Only Memory), EEPROM (El
ectrically Erasable and Programmable Read Only Mem
ory) is attracting attention.
In EPROMs and EEPROMs, data is stored by storing charge in a floating gate electrode and detecting a change in threshold voltage due to the presence or absence of a charge with a control gate electrode. The EEPROM includes a flash EEPROM which erases data in the entire memory cell array or divides the memory cell array into arbitrary blocks and erases data in each block unit.

[0003] Memory cells (memory cell transistors) constituting a flash EEPROM are roughly classified into a stacked gate type and a split gate type. Flash EEPROM using stacked gate type memory cells
Does not have the ability for individual memory cells to select themselves. Therefore, when extracting charges from the floating gate electrode during data erasing, if the charges are excessively extracted, a predetermined voltage (for example, 0 V) for bringing the memory cell into a non-conductive state is used.
Is applied to the control gate electrode, the channel region becomes conductive. As a result, the memory cell is always in a conductive state, a cell current always flows between the source region and the drain region, and a problem that reading of stored data becomes impossible, that is, a problem of so-called excessive erasure occurs. In order to prevent over-erasing, it is necessary to devise an erasing procedure, and it is necessary to control the erasing procedure by a peripheral circuit of the memory device or to control the erasing procedure by an external circuit of the memory device.

A split gate type memory cell has been developed in order to avoid the problem of excessive erasure in such a stacked gate type memory cell. Flash EEPROM using split gate memory cells
Are disclosed in WO 92/18980 (G11C 13/00).

FIG. 12 is a cross-sectional view of a conventional split gate memory cell 1. As shown in FIG. The split-gate memory cell (split-gate transistor) 1 includes a source region 3, a drain region 4, a channel region 5, a floating gate electrode 7, and a control gate electrode 9.

An N type source region 3 and a drain region 4 are formed on a P type single crystal silicon substrate 2. On the channel region 5 sandwiched between the source region 3 and the drain region 4, a floating gate electrode 7 is formed via a gate insulating film 6. On the floating gate electrode 7, LOCOS (Local Ox
insulating film 19 formed by the idation on Silicon method
In addition, a control gate electrode 9 is formed via a tunnel insulating film 8. Due to the insulating film 19, a protrusion 7b is formed in a peripheral portion above the floating gate electrode 7.

Here, a part of the control gate electrode 9 is disposed on the channel region 5 via the respective insulating films 6 and 8 to form a select gate 10. The select transistor 11 is constituted by the select gate 10 and the source region 3 and the drain region 4. That is, the split gate memory cell 1 has a configuration in which a transistor including the gate electrodes 7 and 9 and the regions 3 and 4 and the selection transistor 11 are connected in series.

FIG. 13A is a partial sectional view of a memory cell array 152 of a flash EEPROM 151 using the split gate type memory cell 1. The memory cell array 152 includes a plurality of memory cells 1 formed on a P-type single-crystal silicon substrate 2.

In order to reduce the occupied area on the substrate 2, two memory cells 1 (hereinafter referred to as "1a" and "1b" to distinguish the two) share a source region 3, The floating gate electrode 7 and the control gate electrode 9 are arranged in an inverted manner with respect to the common source region 3.

FIG. 13B shows a memory cell array 152.
FIG. FIG. 13 (a) is the same as FIG.
It is an AA line sectional view in (b). A field insulating film 13 is formed on the substrate 2, and the field insulating film 13 performs element isolation between the memory cells 1. Each memory cell 1 arranged in the vertical direction in FIG.
Are common. FIG.
The control gate electrode 9 of each memory cell 1 arranged in the vertical direction in (b) is common, and the control gate electrode 9 forms a word line. FIG. 13 (b)
Are connected to a bit line (not shown) via a bit line contact 14.

FIG. 14 shows an overall configuration of a flash EEPROM 151 using the split gate type memory cell 1. The memory cell array 152 includes a plurality of memory cells 1
Are arranged in a matrix. The control gate electrodes 9 of the memory cells 1 arranged in the row direction form common word lines WLa to WLz. The drain regions 4 of the memory cells 1 arranged in the column direction are connected to common bit lines BLa to BLz.

The odd-numbered word lines (WLa... WLm... WL
y) and each of the memory cells 1a connected to the even-numbered word lines (WLb... WLn... WLz) share a source region 3. Lines RSLa to RSLm are formed. For example, each memory cell 1b connected to the word line WLa and each memory cell 1a connected to the word line WLb have a common source region 3, and the common source region 3 forms a source line RSLa. . Each of the source lines RSLa to RSLm is connected to a common source line SL.

Each word line WLa-WLz is connected to a row decoder 153, and each bit line BLa-BLz is connected to a column decoder 154. The row address and column address specified from outside are
55 is input. The row address and the column address are sent from the address pin 155 to the address buffer 15.
6 to the address latch 157. Among the addresses latched by the address latch 157, the row address is transferred to the row decoder 153, and the column address is transferred to the column decoder 154.

The row decoder 153 includes an address latch 1
One word line WLa to WLz (for example, WLm) corresponding to the row address latched at 57 is selected, and the potential of the selected word line WLm is controlled in accordance with each operation mode shown in FIG. .

The column decoder 154 selects bit lines BLa to BLz (for example, BLm) corresponding to the column address latched by the address latch 157, and sets the potential of the selected bit line BLm to each operation shown in FIG. Control according to the mode.

The common source line SL is connected to a source line bias circuit 162. Source line bias circuit 162
Are connected to the source lines RSLa to RLa via a common source line SL.
The potential of SLm is controlled according to each operation mode shown in FIG.

Data specified externally is input to data pin 158. The data is stored on data pin 158.
Through the input buffer 159 and the column decoder 154
Transferred to The column decoder 154 controls the potentials of the bit lines BLa to BLz selected as described above in accordance with the data as described later.

Data read from an arbitrary memory cell 1 is transmitted from bit lines BLa to BLz to column decoder 15.
4 to the sense amplifier group 160. The sense amplifier group 160 includes several sense amplifiers (not shown). The column decoder 154 connects the selected bit line BLm to each sense amplifier. As described later, the data determined by the sense amplifier group 160 is:
The data is output from the output buffer 161 to the outside via the data pin 158.

The operation of each of the circuits (153 to 162) is controlled by the control core circuit 163. next,
Each operation mode (erase mode, write mode, read mode, standby mode) of the flash EEPROM 151 will be described with reference to FIG.

(A) Erasing Mode In the erasing mode, all the source lines RSLa to RSL
The potentials of m and all the bit lines BLa to BLz are held at the ground level (= 0 V). 14 to 15 V is supplied to the selected word line WLm, and the other word lines (non-selected word lines) WLa to WL1, WLn to WL
The potential of z is set to the ground level. Therefore, the control gate electrode 9 of each memory cell 1 connected to the selected word line WLm is raised to 14 to 15V.

By the way, the capacitance between the source region 3 and the substrate 2 and the floating gate electrode 7 and the control gate electrode 9
Comparing the capacitance between the floating gate electrode 7 and the floating gate electrode 7, the former is overwhelmingly larger. Therefore, when the control gate electrode 9 has a voltage of 14 to 15 V and the source and the drain have a voltage of 0 V, a high electric field is generated between the control gate electrode 9 and the floating gate electrode 7. As a result, a Fowler-Nordheim Tunnel Current (hereinafter, referred to as FN tunnel current) flows, and electrons in the floating gate electrode 7 are drawn toward the control gate electrode 9 as shown by an arrow B in FIG. Then, the data stored in the memory cell 1 is erased. At this time, the floating gate electrode 7 has a protrusion 7b
Are formed, the electrons in the floating gate electrode 7 jump out of the projection 7b and move to the control gate electrode 9 side.
Therefore, the movement of the electrons is facilitated, and the electrons in the floating gate electrode 7 can be efficiently extracted.

This erase operation is performed by selecting the selected word line WL.
This is performed for all the memory cells 1 connected to m. Note that by simultaneously selecting a plurality of word lines WLa to WLz, an erasing operation can be performed on all the memory cells 1 connected to each word line. The erasing operation of dividing the memory cell array 152 into arbitrary blocks for each of the plural sets of word lines WLa to WLz and erasing data in each block is called block erasing.

(B) Write Mode In the write mode, the potential of the bit line BLm connected to the drain region 4 of the selected memory cell 1 is set to the ground level, and the other bit lines (unselected bit lines) 4 V is supplied to BLa to BLl and BLn to BLz. 2 V is supplied to the word line WLm connected to the control gate electrode 9 of the selected memory cell 1, and the other word lines (non-selected word lines) WLa to WLm are supplied.
The potentials of WL1, WLn to WLz are set to the ground level. 12 V is supplied to all the source lines RSLa to RSLm.

In the memory cell 1, the threshold voltage Vth of the selection transistor 11 is 0.5V. Therefore, in the selected memory cell 1, the electrons in the drain region 4 move into the channel region 5 in an inverted state. Therefore, a cell current flows from the source region 3 to the drain region 4. On the other hand, since 12 V is applied to the source region 3, the potential of the floating gate electrode 7 is raised by the coupling between the source region 3 and the floating gate electrode 7 via the capacitance. Therefore, a high electric field is generated between the channel region 5 and the floating gate electrode 7. Accordingly, the electrons in the channel region 5 are accelerated to become hot electrons, and are injected into the floating gate electrode 7 as shown by an arrow C in FIG. As a result, charges are accumulated in the floating gate electrode 7 of the selected memory cell 1, and 1-bit data is written and stored.

This writing operation is different from the erasing operation.
This can be performed for each selected memory cell 1. (C) Read Mode In the read mode, four words are connected to the word line WLm connected to the control gate electrode 9 of the selected memory cell 1.
V is supplied, and the potentials of the other word lines (non-selected word lines) WLa to WLl and WLn to WLz are set to the ground level. 2 V is supplied to the bit line BLm connected to the drain region 4 of the selected memory cell 1, and the other bit lines (unselected bit lines) BLa to BLm are supplied.
The potentials of BL1, BLn to BLz are set to the ground level.

As described above, electrons are extracted from the floating gate electrode 7 of the memory cell 1 in the erased state. Electrons are injected into the floating gate electrode 7 of the memory cell 1 in the written state. Therefore, the channel region 5 immediately below the floating gate electrode 7 of the memory cell 1 in the erased state is on, and the channel region 5 immediately below the floating gate electrode 7 of the memory cell 1 in the written state is off. Therefore, when 4 V is applied to the control gate electrode 9, the cell current flowing from the drain region 4 toward the source region 3 is larger in the erased memory cell 1 than in the written memory cell 1.

By determining the magnitude of the cell current between the memory cells 1 by each of the sense amplifiers in the sense amplifier group 160, the value of the data stored in the memory cell 1 can be read. For example, reading is performed with the data value of the memory cell 1 in the erased state being “1” and the data value of the memory cell 1 in the written state being “0”. That is, each memory cell 1 can store two values of the data value “1” in the erased state and the data value “0” in the written state.

(D) Standby Mode In the standby mode, the common source line SL, all word lines WLa to WLz, and all bit lines BLa to BL
The potential of z is kept at the ground level. In this standby mode, no operation (erase operation, write operation, read operation) is performed on all the memory cells 1.

A flash EEPROM 151 using the split gate memory cell 1 constructed as described above.
Has the function of selecting itself in each memory cell 1 because the selection transistor 11 is provided. That is, the channel region 5 can be made non-conductive by the selection gate 10 even if the charge is excessively extracted when extracting the charge from the floating gate electrode 7 at the time of data erasing. Therefore, even if excessive erasure occurs, conduction / non-conduction of the memory cell 1 can be controlled by the selection transistor 11, and excessive erasure does not pose a problem. That is, the conduction / non-conduction of the memory cell itself can be selected by the selection transistor 11 provided inside the memory cell 1.

In the split gate type memory cell 1 shown in FIGS. 12 and 13, a flash EEPROM in which the source region 3 is a drain region and the drain region 4 is a source region is disclosed in US Pat. No. 5,029,130.
(G11C 11/40).

FIG. 16A shows a flash EEPROM using the split gate type memory cell 21 in that case.
FIG. 171 is a partial cross-sectional view of the memory cell array 152 of FIG.
FIG. 16B is a partial plan view of the memory cell array 152 in that case. FIG. 16A is a diagram corresponding to FIG.
3 is a sectional view taken along line AA in FIG.

FIG. 17 shows the overall configuration of a flash EEPROM 171 using the split gate type memory cell 21. FIG. 18 shows the potential of each part of the flash EEPROM 171 in each operation mode.

The split gate type memory cell 21 differs from the split gate type memory cell 1 in that the names of the source region 3 and the drain region 4 are reversed. That is, the source region 3 of the memory cell 21
Is called the drain region 4 in the memory cell 1, and the drain region 4 of the memory cell 21 is called the source region 3 in the memory cell 11.

In the flash EEPROM 171,
The only difference from the flash EEPROM 151 is that the common source line SL is grounded. Therefore, in any operation mode, the potentials of the source lines RSLa to RSLm are held at the ground level via the common source line SL.

In the write mode, 12 V is supplied to the bit line BLm connected to the drain region 4 of the selected memory cell 21, and the other bit lines (non-selected bit lines) BLa to BL1,. BLn-BL
The potential of z is set to the ground level.

Incidentally, also in the memory cell 21, the threshold voltage Vth of the selection transistor 11 is 0.5V. Therefore, in the selected memory cell 21, the electrons in the source region 3 move into the channel region 5 in the inverted state. Therefore, a cell current flows from the drain region 4 to the source region 3. On the other hand, 12 V
Is applied, the drain region 4 and the floating gate electrode 7
, The potential of the floating gate electrode 7 is raised. Therefore, a high electric field is generated between the channel region 5 and the floating gate electrode 7. Therefore, the electrons in the channel region 5 are accelerated to become hot electrons and are injected into the floating gate electrode 7. As a result, charges are accumulated in the floating gate electrode 7 of the selected memory cell 21, and 1-bit data is written and stored.

Next, the memory cell array 15 shown in FIG.
2 will be described step by step with reference to FIGS. 19 and 20. Step 1 (see FIG. 19A): A field insulating film 13 (not shown) is formed on the substrate 2 by using the LOCOS method.
Next, a gate insulating film 6 made of a silicon oxide film is formed using a thermal oxidation method in a portion (element region) where the field insulating film 13 is not formed on the substrate 2. Subsequently, a doped polysilicon film 31 serving as the floating gate electrode 7 is formed on the gate insulating film 6. And LPCVD
A silicon nitride film 32 is formed on the entire surface of the doped polysilicon film 31 by using a (Low Pressure Chemical Vaper Deposition) method. Next, after a resist is applied to the entire surface of the silicon nitride film 32, an etching mask 33 for forming the floating gate 7 is formed by using ordinary photolithography technology.

Step 2 (see FIG. 19B): The silicon nitride film 32 is etched by anisotropic etching using the etching mask 33. Then, the etching mask 33 is peeled off . Next, the insulating film 19 is formed by oxidizing the doped polysilicon film 31 using the etched silicon nitride film 32 as an oxidation mask using the LOCOS method. At this time, the end of the insulating film 19 penetrates into the end of the silicon nitride film 31, and a bird's beak 19a is formed.

Step 3 (see FIG. 19C): The silicon nitride film 32 is removed. Next, the doped polysilicon film 31 is etched by anisotropic etching using the insulating film 19 as an etching mask to form the floating gate electrode 7.
To form At this time, since the bird's beak 19a is formed at the end of the insulating film 19, the upper edge of the floating gate electrode 7 becomes sharp along the shape of the bird's beak 19a, and the projection 7b is formed.

Step 4 (see FIG. 19D): A tunnel insulating film 8 made of a silicon oxide film is formed on the entire surface of the device formed in the above steps by using the thermal oxidation method or the LPCVD method or a combination thereof. . Then, the laminated insulating films 6 and 8 are integrated.

Step 5 (see FIG. 20A): A doped polysilicon film 34 serving as the control gate electrode 9 is formed on the entire surface of the device formed in the above step. The following are the methods for forming the doped polysilicon films 31 and 34.

Method 1: When forming a polysilicon film using the LPCVD method, a gas containing impurities is mixed. Method 2: After forming a non-doped polysilicon film by using the LPCVD method, POCl ₃ is formed on the polysilicon film.
An impurity diffusion source layer is formed using, for example, and an impurity is diffused from the impurity diffusion source layer into the polysilicon film.

Method 3: After forming a non-doped polysilicon film using the LPCVD method, impurity ions are implanted. Step 6 (see FIG. 20B): After applying a resist to the entire surface of the device formed in the above step, an etching mask 35 for forming the control gate electrode 9 by using a normal photolithography technique. To form

Step 7 (see FIG. 20C): The doped polysilicon film 34 is etched by anisotropic etching using the etching mask 35 to form the control gate electrode 9. Thereafter, the etching mask 35 is peeled off.

[0045]

As shown in FIG. 21,
In the initial stage of the formation of the tunnel insulating film 8 in Step 4, an incomplete silicon oxide film 8a due to a natural oxide film, a structural transition layer, and the like is formed. This imperfect silicon oxide film 8
a includes dangling bonds that do not take the form of O-Si-O, as well as O-Si-O bonds that are complete silicon oxides.

That is, during the transition from step 3 to step 4, the side wall of the floating gate electrode 7 is exposed to the outside air containing oxygen, so that a natural oxide film is formed on the surface of the side wall of the floating gate electrode 7. You. The natural oxide film contains dangling bonds that do not take the form of O-Si-O.

A structural transition layer exists at the boundary between the floating gate electrode 7 made of a polysilicon film and the tunnel insulating film 8 made of a silicon oxide film. Dangling bonds that do not take the form of O-Si-O are likely to exist in the structural transition layer.

FIG. 22 is a sectional view of the memory cell 1 in which the incomplete silicon oxide film 8a has been formed. As described above, in the erase mode, as shown by the arrow B in FIG. 22, electrons in the floating gate electrode 7 are pulled out to the control gate electrode 9 side, and the data stored in the memory cell 1 is erased. . At this time, since the electrons accelerated by the high electric field pass through the tunnel insulating film 8 including the incomplete silicon oxide film 8a, a large stress is applied to each of the films 8, 8a.

Therefore, when the writing operation and the erasing operation are repeated, an electron trap is formed and accumulated in the incomplete silicon oxide film 8a due to the stress applied to each of the films 8, 8a during the erasing operation. The electron trap inhibits the transfer of electrons from the floating gate electrode 7 to the control gate electrode 9. Accordingly, as the number of times of writing and the number of times of erasing (that is, the number of times of rewriting of data) increase, the number of incomplete electron traps in the silicon oxide film 8a also increases, and the electrons in the floating gate electrode 7 cannot be sufficiently extracted.

Therefore, as shown in FIG. 23, the cell current in the read mode does not change as the number of data rewrites increases, whereas the cell current of the memory cell 1 in the read state changes. The cell current decreases. As a result, the difference between the cell current of the memory cell 1 in the write state and the cell current of the memory cell 1 in the read state decreases, and it becomes impossible to determine the magnitude of the cell current between the memory cells 1 described above. That is, it becomes impossible to read the value of the data stored in the memory cell 1, and the function as the memory cell is not performed.

As described above, when the incomplete silicon oxide film 8a is formed in the step 4, it is difficult to increase the number of times of rewriting data in the memory cell 1, and the operating life of the memory cell 1 is shortened. There is. When the operating life of the memory cell 1 is shortened, the operating life of the flash EEPROM 151 is also shortened. This problem is caused by the memory cell 21 and the flash EEPROM.
The same occurs in 171.

As shown in FIG. 24, when the tunnel insulating film 8 is formed by the thermal oxidation method in the step 4, the end of the tunnel insulating film 8 penetrates into the lower edge of the floating gate electrode 7. , Bird's Beak (Gate Bird's Beak) 8b
May be formed. When the bird's beak 8b is formed, the surface of the tunnel insulating film 8 on the opposite side of the bird's beak 8b is thinned to form a gap 8c.

Then, when the doped polysilicon film 34 is formed in the step 5, the doped polysilicon film 34 is also formed in the gap 8c.
Is sharpened along the shape of the gap 8c, and the protrusion 9
a is formed.

FIG. 25 is a sectional view of the memory cell 1 in which the projection 9a is formed at the lower end of the control gate electrode 9. When the projection 9a is formed at the lower end of the control gate electrode 9, in the write mode, a phenomenon occurs in which electrons are emitted from the projection 9a and the electrons are erroneously injected into the floating gate 7. This phenomenon is generally called a reverse tunneling phenomenon. When the reverse tunneling phenomenon occurs, in the write mode of the flash EEPROM 151, data is erroneously written to the unselected memory cell 1. That is, it becomes impossible to write separate data to each memory cell 1, and the function as an EEPROM is not performed.

As described above, when the bird's beak 8b is formed in the step 4, there is a problem that a reverse tunneling phenomenon occurs and the flash EEPROM 151 does not function. This problem also occurs in the memory cell 21 and the flash EEPROM 171.

The present invention has been made to solve the above problems, and has the following objects. (1) A method for producing a long-life split gate transistor.

(2) A method of manufacturing a split gate transistor capable of preventing a reverse tunneling phenomenon is provided.

[0058]

[0059]

[Means for Solving the Problems]

The split gate transistor according to the first aspect of the present invention includes a tunnel insulating film provided between the floating gate electrode and the control gate electrode, and controls the electrons in the floating gate electrode through the tunnel insulating film. Data is erased by pulling out to the gate electrode,
Forming a conductive film selected from the group consisting of a polysilicon film, an amorphous silicon film, and a single crystal silicon film on a semiconductor substrate, and forming the floating gate electrode by patterning the conductive film; A step of nitriding the entire side wall of the floating gate electrode to form a layer containing nitrogen atoms, and using at least one of a thermal oxidation method, a thermal nitridation method, a thermal oxynitridation method, and a CVD method, Forming a tunnel insulating film containing at least one of silicon oxide, silicon oxynitride, and silicon nitride as a main component on the device formed in the process; and forming the tunnel insulating film on the floating gate electrode through the tunnel insulating film. And forming the control gate electrode so as to face each other.

According to a second aspect of the present invention, there is provided a method of manufacturing a split gate type transistor according to the first aspect of the present invention, further comprising the steps of:
The gist of the present invention is to use any one method selected from the group consisting of a method of exposing to nitrogen plasma and a method of performing heat treatment in a nitriding atmosphere.

According to a third aspect of the present invention, there is provided a method of manufacturing a split gate transistor according to the first aspect of the present invention, wherein when the floating gate electrode is nitrided, a rotational oblique ion implantation method of nitrogen ions is used. I do.

[0063]

[0064]

[0065]

According to a fourth aspect of the present invention, there is provided a method of manufacturing a split gate transistor, comprising a tunnel insulating film provided between a floating gate electrode and a control gate electrode, and allowing electrons in the floating gate electrode to pass through the tunnel insulating film. Erasing data by extracting the floating gate electrode on the semiconductor substrate and forming the tunnel insulating film on the device formed in the above step. And nitriding the tunnel insulating film so that the distribution of nitrogen in the tunnel insulating film has a maximum peak near at least one of the control gate electrode and the floating gate electrode; and Forming the control gate electrode so as to face the floating gate electrode with the interposition of the control gate electrode.

According to a fifth aspect of the present invention, in the method for manufacturing a split gate transistor according to the fourth aspect of the present invention, the method further comprises the steps of:
The gist of the present invention is to use any one method selected from the group consisting of a method of exposing to nitrogen plasma and a method of performing heat treatment in a nitriding atmosphere.

[0068]

[0069]

[0070]

[0071]

[0072]

[0073]

[0074]

[0075]

[0076]

[0077]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. In this embodiment,
12, 13, 19, and 20, the same components as those of the conventional embodiment shown in FIGS.

FIG. 1 is a partial sectional view of a split gate type memory cell 41 of this embodiment. FIG. 2A shows a flash E using a split gate type memory cell 41.
FIG. 3 is a partial cross-sectional view of a memory cell array 152 of the EPROM 151. FIG. 2B is a partial plan view of the memory cell array 152. FIG. 2A is a sectional view taken along line AA in FIG. 2B.

FIGS. 1 and 2 differ from FIGS. 12 and 13 only in the following points. (1) A plurality of split gate type memory cells (split gate type transistors) 41 are arranged on a substrate 2. Each memory cell 41 includes a source region 3, a drain region 4, a channel region 5, a floating gate electrode 7, and a control gate electrode 9.

For the purpose of keeping the occupied area on the substrate 2 small, two memory cells 41 (hereinafter, referred to as “41a” and “41b” for distinguishing the two) share the source region 3 and The floating gate electrode 7 and the control gate electrode 9 are arranged in an inverted manner with respect to the common source region 3.

(2) On the side wall of the floating gate electrode 7, a layer 7a of a doped polysilicon film containing nitrogen atoms at a concentration of about 1 to 10% (hereinafter referred to as a nitrogen atom-containing layer) 7a
Is provided. The shape of the floating gate electrode 7 is a rectangular parallelepiped, and a nitrogen atom-containing layer 7a is provided on all four side walls.

The overall configuration of a flash EEPROM 51 using the split gate type memory cell 41 of the present embodiment is the same as the conventional configuration shown in FIG. Further, the potential of each part in each operation mode of the flash EEPROM 51 of the present embodiment is the same as that of the conventional mode shown in FIG.

Next, the manufacturing method of this embodiment will be described with reference to FIGS.
Will be described step by step. Step 1 (see FIG. 3A), Step 2 (see FIG. 3B); the same as Steps 1 and 2 of the conventional embodiment.

Step 3 (see FIG. 3C): The silicon nitride film 32 is removed. Next, the floating gate electrode 7 is formed by etching the doped polysilicon film 31 by anisotropic etching using the insulating film 19 as an etching mask. At this time, since the bird's beak 19a is formed at the end of the insulating film 19, the upper edge of the floating gate electrode 7 becomes sharp along the shape of the bird's beak 19a,
The projection 7b is formed. The above steps are the same as step 3 of the conventional embodiment.

Subsequently, nitrogen ions are implanted into the side wall of the floating gate electrode 7 to form a nitrogen atom-containing layer 7a. At this time, in order to uniformly implant nitrogen ions into the four side walls of the floating gate electrode 7 having a rectangular parallelepiped shape, the substrate 2
It is desirable to implant nitrogen ions at an angle of about 60 ° from a normal standing on the surface of the substrate 2 while rotating the entire silicon wafer (not shown) on which is formed. A method of performing ion implantation at a predetermined angle on a silicon wafer while rotating the entire silicon wafer in this manner is generally called a rotational oblique ion implantation method. Here, the conditions for implanting nitrogen ions are as follows: implantation energy: about 10 keV, and dose: about 1 × 10 ^{15 to} 5 × 10 ¹⁶ atoms / cm ² .
The injection range (RP; Projection Range) of nitrogen ions in the polysilicon film at an implantation energy of 10 keV is as follows.
Since the implanted nitrogen ions are introduced only near the very surface of the side wall of the floating gate electrode 7, the thickness of the nitrogen atom-containing layer 7a becomes very small.

Step 4 (see FIG. 3D): A tunnel insulating film 8 made of a silicon oxide film is formed on the entire surface of the device formed in the above steps by using the thermal oxidation method, the LPCVD method, or a combination thereof. . Then, the laminated insulating films 6 and 8 are integrated.

At this time, since the nitrogen-containing layer 7 a is provided on the side wall of the floating gate electrode 7, in the initial stage of the formation of the tunnel insulating film 8, incomplete silicon due to a natural oxide film, a structural transition layer, No oxide film is formed.

That is, since the nitrogen atom-containing layer 7a is provided, even if the side wall of the floating gate electrode 7 is exposed to the outside air containing oxygen during the transition from the step 3 to the step 4,
The formation of a natural oxide film containing a dangling bond that does not take the form of O-Si-O is suppressed on the surface of the side wall of the floating gate electrode 7.

As described above, the structural transition layer exists at the boundary between the floating gate electrode 7 made of a polysilicon film and the tunnel insulating film 8 made of a silicon oxide film. Dangling bonds that do not take the form of O-Si-O are likely to occur in the structural transition layer. However, dangling bonds are not terminated by trivalent nitrogen atoms contained in the nitrogen atom-containing layer 7a. As a result, generation of dangling bonds in the structural transition layer can be suppressed.

In addition, since the nitrogen atom-containing layer 7a is provided, even when the tunnel insulating film 8 is formed by using the thermal oxidation method, the end of the tunnel insulating film 8 is formed on the lower edge of the floating gate electrode 7. And bird's beak (gate bird's beak) is suppressed.

Step 5 (see FIG. 4A) to Step 7 (see FIG.
(See (c)); the same as steps 5 to 7 in the conventional embodiment. Step 8 (see FIG. 5A): After applying a resist to the entire surface of the device formed in the above-described step, an ion implantation mask 42 for forming the source region 3 using ordinary photolithography technology. To form Next, the source region 3 is formed by implanting phosphorus ions (P ⁺ ) using a normal ion implantation method. Then, the ion implantation mask 4
2 is peeled off.

At this time, the ion implantation mask 42 is formed so as to cover at least a portion to be the drain region 4 on the substrate 2 and not to protrude above the floating gate electrode 7. As a result, the position of the source region 3 is
It is defined by the end of the floating gate electrode 7.

Step 9 (see FIG. 5B): After a resist is applied to the entire surface of the device formed in the above step, ion implantation for forming the drain region 4 is performed by using ordinary photolithography technology. A mask 43 is formed. Next, arsenic ions (A
s ⁺ ) is implanted to form the drain region 4.

At this time, the ion implantation mask 43 is formed so as to cover at least the source region 3. Step 10 (see FIG. 5C); mask 43 for ion implantation
Is removed, the split gate memory cell 41 (41a, 41b) of the present embodiment is completed.

As described above, according to the present embodiment, the following operations and effects can be obtained. [1] A nitrogen atom-containing layer 7a is formed on the side wall of the floating gate electrode 7.
Is provided. Therefore, even in the initial stage of the formation of the tunnel insulating film 8 in the step 4, an incomplete silicon oxide film as shown in FIG. 21 of the conventional embodiment is not formed.

[2] From the above [1], even if the write operation and the erase operation are repeated for the memory cell 41,
An electron trap is not formed in the tunnel insulating film 8 due to the stress applied to the tunnel insulating film 8 during the erase operation. Therefore, even if the number of times of data rewriting increases, electrons in the floating gate electrode 7 can be sufficiently extracted in the erase mode.

Therefore, even if the number of times of data rewriting increases, the cell current of the memory cell 41 in the read state does not decrease in the read mode. Therefore, the difference between the cell current of the memory cell 41 in the write state and the cell current of the memory cell 41 in the read state does not decrease, and the magnitude of the cell current between the memory cells 41 can be easily determined. Can be.

[3] From the above [2], the number of times of rewriting data in the memory cell 41 can be increased, and the operating life of the memory cell 41 can be extended. As a result, the operating life of the flash EEPROM 51 can be extended.

[4] Since the nitrogen-containing layer 7 a is provided, the tunnel insulating film 8 is formed on the lower edge of the floating gate electrode 7.
Bird's beak (gate bird's beak)
Is not formed. Therefore, at the time of forming the tunnel insulating film 8 in the step 4, the conventional mode shown in FIG.
The gap 8c of the tunnel insulating film 8 as shown in FIG. 4 does not occur. Then, when the doped polysilicon film 34 is formed in the step 5, the projection 9a at the lower end of the control gate electrode 9 as shown in FIG. 25 of the conventional embodiment is not formed.

[5] From the above [4], in the write mode, the phenomenon that electrons are emitted from the control gate electrode 9 and the electrons are erroneously injected into the floating gate 7 (reverse tunneling phenomenon) does not occur. . Therefore,
In the write mode of the flash EEPROM 51, data is not erroneously written to the non-selected memory cells 41, and individual data can be written to each memory cell 41.

[6] The nitrogen atom-containing layer 7a is formed by oblique rotation ion implantation. Therefore, the nitrogen atom-containing layer 7a can be easily formed with high controllability. [7] In step 3, as for the conditions for implanting nitrogen ions when forming the nitrogen atom-containing layer 7a, the dose range is suitably about 1 × 10 ^{15 to} 5 × 10 ¹⁶ atoms / cm ² ,
If the amount exceeds this range, silicon nitride tends to be formed and the formation of the tunnel insulating film 8 tends to be hindered. If the amount is below this range, the effect tends to decrease.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. In this embodiment, the same components as those in the conventional embodiment shown in FIGS. 12, 13, 19, and 20 are denoted by the same reference numerals, and detailed description thereof is omitted.

FIG. 6A shows a flash EEPROM using the split gate type memory cell 61 of this embodiment.
71 is a partial cross-sectional view of a memory cell array 152 of FIG. FIG. 6B is a partial plan view of the memory cell array 152. FIG. 6A is a sectional view taken along line AA in FIG. 6B.

FIG. 6 differs from FIGS. 12 and 13 only in the following points. (1) A plurality of split gate type memory cells (split gate type transistors) 61 are arranged on a substrate 2. Each memory cell 41 includes a source region 3, a drain region 4, a channel region 5, a floating gate electrode 7, and a control gate electrode 9.

For the purpose of reducing the occupied area on the substrate 2, two memory cells 61 (hereinafter, referred to as "61a" and "61b" for distinguishing the two) share the source region 3, The floating gate electrode 7 and the control gate electrode 9 are arranged in an inverted manner with respect to the common source region 3.

(2) The tunnel insulating film 8 contains nitrogen atoms. 7 to 9 show the distribution and concentration of nitrogen atoms contained in the tunnel insulating film 8. FIG. FIG. 7 shows a case where a portion of the tunnel insulating film 8 near the floating gate electrode 7 has a nitrogen concentration peak.

FIG. 8 shows a case where the tunnel insulating film 8 has a nitrogen concentration peak near the control gate electrode 9. FIG. 9 shows a case where the nitrogen concentration peaks both in the portion near the floating gate electrode 7 and in the portion near the control gate electrode 9 in the tunnel insulating film 8.

In FIGS. 7 and 8, (a) to (c)
When the peak level of nitrogen concentration is large,
In (i), when the peak level of the nitrogen concentration is small,
(D) to (f) show the peak levels of the nitrogen concentration in (a) to (f).
The case between (c) and (g) to (i) is shown. Also,
(A) (d) (g) when the nitrogen distribution is narrow,
(C) (f) (i) when the nitrogen distribution is broad,
(B) In (e) and (h), the nitrogen distribution is (a) (d) (g)
And (c), (f), and (i).

As described above, the structural transition layer exists at the boundary between the floating gate electrode 7 and the tunnel insulating film 8, and the structural transition layer has a dangling bond that does not take the form of O—Si—O. Likely to happen. However, by including nitrogen atoms in the tunnel insulating film 8 corresponding to the structural transition layer, dangling bonds can be terminated with trivalent nitrogen atoms, thereby eliminating dangling bonds. be able to.

Therefore, as shown in FIG. 7 or FIG. 9, if there is a peak of the nitrogen concentration near the floating gate electrode 7 in the tunnel insulating film 8, dangling bonds in the structural transition layer can be eliminated.

However, in this case, there is an optimum value for the nitrogen concentration. If the concentration is higher than that, a problem occurs that the stress in the tunnel insulating film 8 increases. If the concentration is lower than the optimum value, the dangling bond This causes a problem that the unbonded hands cannot be completely terminated.

By the way, as shown in FIG. 8 or FIG.
If there is a peak of the nitrogen distribution near the control gate electrode 9 in the tunnel insulating film 8, it is possible to suppress electron traps generated during the erase operation. Also. When the nitrogen distribution is broad, it is possible to suppress electron traps generated other than near the interface.

Therefore, it is desirable that the distribution state of nitrogen atoms in tunnel insulating film 8 is broad or that nitrogen atoms are contained in a portion of tunnel insulating film 8 close to control gate electrode 9.

The overall configuration of a flash EEPROM 71 using the split gate type memory cell 61 of the present embodiment is the same as the conventional configuration shown in FIG. Further, the potential of each part in each operation mode of the flash EEPROM 71 of the present embodiment is the same as that of the conventional form shown in FIG.

Next, the manufacturing method of this embodiment will be described.
In the manufacturing method according to this embodiment, the conventional method and the first method are used.
Only the following points are different from the embodiment. That is,
After the conventional step 4 is completed, a nitriding atmosphere (NH
₃ ), the tunnel insulating film 8 contains nitrogen atoms. At this time, by adjusting the thickness of the tunnel insulating film 8 and the heat treatment conditions, the thickness of FIG.
9, the distribution and concentration of nitrogen atoms contained in tunnel insulating film 8 can be adjusted.

Thereafter, steps 5 to 10 of the first embodiment
Through the split gate type memory cell 6 of the present embodiment.
1 is completed. As described above, according to the present embodiment, since the tunnel insulating film 8 contains nitrogen atoms, the same operations and effects as [1] to [3] of the first embodiment can be obtained. In addition, since the heat treatment in a nitriding atmosphere is used as a method for causing the tunnel insulating film 8 to contain nitrogen atoms, the distribution and concentration of the nitrogen atoms contained in the tunnel insulating film 8 can be easily set to a desired state. .

The above embodiments may be modified as follows, and even in such a case, the same operation and effect can be obtained. (1) In the first embodiment, the nitrogen atom-containing layer 7a is provided only on a portion where electrons jump out in the erase mode, instead of providing the nitrogen atom-containing layer 7a on all four side walls of the floating gate electrode 7. In this case, when forming the nitrogen atom-containing layer 7a, it is not necessary to use the rotary oblique ion implantation method, and nitrogen ions may be implanted only into the necessary portions of the floating gate electrode 7 using the normal oblique ion implantation method. Good.

(2) In the first embodiment, when forming the nitrogen atom-containing layer 7a, instead of the ion implantation method,
The following method is used. (A) Exposing the side wall of the floating gate electrode 7 to nitrogen plasma.

(B) After the formation of the floating gate electrode 7, a heat treatment is performed in a nitriding atmosphere (such as NH ₃ ). (3) In the second embodiment, when the tunnel insulating film 8 contains nitrogen atoms, the following method is used instead of performing heat treatment in a nitriding atmosphere.

(A) The tunnel insulating film 8 is exposed to nitrogen plasma. (B) Nitrogen ions are implanted into the tunnel insulating film 8. (C) The doped polysilicon film 34 serving as the control gate electrode 9 contains nitrogen atoms, and the nitrogen in the doped polysilicon film 34 is diffused into the tunnel insulating film 8.

(4) The insulating film 19 is omitted. (5) Each of the insulating films 6 and 8 is replaced with another insulating film containing at least one of silicon oxide, silicon oxynitride, and silicon nitride as a main component. In order to form the insulating film, at least one of a thermal oxidation method, a thermal nitridation method, a thermal oxynitridation method, and a CVD method may be used. Further, a structure in which a plurality of these different insulating films are stacked is replaced.

(6) The material of each of the gate electrodes 7 and 9 is replaced with a conductive material other than doped polysilicon (amorphous silicon, single crystal silicon, various metals including refractory metals, silicide, etc.).

(7) The P-type single crystal silicon substrate 2 is replaced with a P-type well. (8) The impurity ions implanted to form the source region 3 are replaced with N-type impurity ions (arsenic, antimony, etc.) other than phosphorus ions. Further, the impurity ions implanted to form the drain region 4 are replaced with N-type impurity ions (such as phosphorus and antimony) other than arsenic ions.

(9) The P-type single-crystal silicon substrate 2 is replaced with an N-type single-crystal silicon substrate or an N-type well, and P-type impurity ions (P-type impurity ions) are implanted to form the source region 3 and the drain region 4. Boron, indium, etc.).

(10) In the first embodiment, the source region 3 of the split gate memory cell 41 is a drain region, and the drain region 4 is a source region. FIG.
FIG. 2 shows a partial cross-sectional view of the memory cell array 152 in that case. The overall configuration of the flash EEPROM 81 in this case is the same as the conventional configuration shown in FIG. Also,
In this case, the potential of each part in each operation mode of the flash EEPROM 81 is the same as that of the conventional embodiment shown in FIG.

(11) In the second embodiment, the source region 3 of the split gate memory cell 61 is a drain region, and the drain region 4 is a source region. FIG.
FIG. 2 shows a partial cross-sectional view of the memory cell array 152 in that case. The overall configuration of the flash EEPROM 91 in this case is the same as the conventional configuration shown in FIG. Also,
In this case, the potential of each part in each operation mode of the flash EEPROM 91 is the same as that of the conventional embodiment shown in FIG.

(12) The first embodiment and the second embodiment are used together. Although the embodiments have been described above, technical ideas other than the claims that can be grasped from the embodiments will be described below along with their effects.

[0128]

(A) In the method of manufacturing a split gate transistor according to any one of claims 1 to 5 , an insulating film (19) is formed on the floating gate electrode (7) by using the LOCOS method. A method of manufacturing a split gate transistor, comprising a step of forming a projection (7a) on a quad above a floating gate electrode by a bird's beak (19a) formed at an end of the insulating film.

According to the method (a) , since the projection is formed on the floating gate electrode, the movement of the electrons when the electrons accumulated in the floating gate electrode are extracted to the control gate electrode is facilitated, and the efficiency is improved. Can be pulled out.

(B) In the method of manufacturing a split gate transistor according to claim 2 or 5 , the nitriding atmosphere is at least one selected from the group consisting of N ₂ O gas, NO gas, and NH ₃ gas. Of manufacturing a split gate transistor including two gases.

In this way, reliable nitriding can be easily and easily performed.

[0133]

【The invention's effect】

[0134]

[0135] According to the invention described in any one of claims 1 to 5, it is possible to provide a manufacturing method of long life split gate transistor.

According to any one of the second, third , and fifth aspects, a reliable nitriding treatment can be easily and easily performed.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a first embodiment.

FIG. 2B is a partial plan view of the first embodiment, and FIG.
2A is a cross-sectional view taken along line AA of FIG.

FIG. 3 is a schematic cross-sectional view for explaining a manufacturing process of the first embodiment.

FIG. 4 is a schematic cross-sectional view for explaining a manufacturing process of the first embodiment.

FIG. 5 is a schematic cross-sectional view for explaining a manufacturing process of the first embodiment.

FIG. 6B is a partial plan view of the second embodiment, and FIG.
FIG. 7A is a cross-sectional view taken along the line AA of FIG.

FIG. 7 is an explanatory diagram for explaining the operation of the second embodiment.

FIG. 8 is an explanatory diagram for explaining the operation of the second embodiment.

FIG. 9 is an explanatory diagram for explaining the operation of the second embodiment.

FIG. 10 (b) is a partial plan view of another embodiment,
FIG. 10A is a cross-sectional view taken along line AA of FIG.

FIG. 11B is a partial plan view of another embodiment,
FIG. 11A is a cross-sectional view taken along line AA of FIG.

FIG. 12 is a schematic sectional view of a conventional embodiment.

13 (b) is a partial plan view of a conventional embodiment, and FIG. 13 (a) is a cross-sectional view taken along line AA of FIG. 13 (b).

FIG. 14 is a block circuit diagram of the first and second embodiments and a conventional mode.

FIG. 15 is an explanatory diagram of the first and second embodiments and a conventional mode.

16 (b) is a partial plan view of a conventional embodiment, and FIG. 16 (a) is a cross-sectional view taken along line AA of FIG. 16 (b).

FIG. 17 is a block circuit diagram of another embodiment and a conventional embodiment.

FIG. 18 is an explanatory view of another embodiment and a conventional embodiment.

FIG. 19 is a schematic cross-sectional view for explaining manufacturing steps of the second embodiment and a conventional embodiment.

FIG. 20 is a schematic cross-sectional view for explaining manufacturing steps of the second embodiment and a conventional embodiment.

FIG. 21 is a schematic cross-sectional view for explaining a manufacturing process in a conventional mode.

FIG. 22 is a schematic sectional view of a conventional embodiment.

FIG. 23 is a characteristic diagram of a conventional embodiment.

FIG. 24 is a schematic cross-sectional view for explaining a manufacturing process in a conventional mode.

FIG. 25 is a schematic sectional view of a conventional embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 2 ... P type single crystal silicon substrate 3 ... Source region 4 ... Drain region 7 ... Floating gate electrode 7a ... Nitrogen atom containing layer 8 ... Tunnel insulating film 9 ... Control gate electrode 19 ... Insulating film 31 ... Doped polysilicon film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (5)

(57) [Claims] 1. Between a floating gate electrode and a control gate electrode
A tunnel insulating film provided on the floating gate electrode.
Electrons in the electrodes are transferred to the control gate through the tunnel insulating film.
Data is erased by pulling out the
A polysilicon film, amorphous silicon on a semiconductor substrate
Film, selected from the group consisting of single crystal silicon films
Forming one conductive film and patterning the conductive film to form the floating gate electrode;
And nitriding the entire side wall of the floating gate electrode to remove nitrogen atoms.
The step of forming a layer containing silicon and thermal oxidation, thermal nitridation, thermal oxynitridation, and CVD.
Using at least one method, the device formed in the above process
Silicon oxide, silicon oxynitride, silicon nitride on the chair
The tunnel connection mainly comprising at least one of
Forming an edge film and facing the floating gate electrode via the tunnel insulating film
Split gate transients to the step of forming the control gate electrode to be, comprising the
Star manufacturing method. 2. The split gate type transistor according to claim 1,
In the method of manufacturing a transistor , nitrogen ions are implanted when the floating gate electrode is nitrided.
Method, exposure method to nitrogen plasma, heat treatment in nitriding atmosphere
Any one selected from the group consisting of how to do
Split gate type, characterized by using the method of (1).
Manufacturing method of transistor. 3. The split gate type transistor according to claim 1,
In the method for manufacturing a transistor, when nitriding the floating gate electrode, rotation of nitrogen ions is performed.
Split using oblique ion implantation
A method for manufacturing a gate transistor. 4. Between a floating gate electrode and a control gate electrode.
A tunnel insulating film provided on the floating gate electrode.
Electrons in the electrodes are transferred to the control gate through the tunnel insulating film.
Data is erased by pulling out the
Forming the floating gate electrode on a semiconductor substrate; and forming a tunnel insulating layer on the device formed in the above step.
Forming a film and controlling the distribution of nitrogen in the tunnel insulating film to the control gate voltage.
At least near one of the pole and the floating gate electrode.
Nitriding the tunnel insulating film to have a large peak
And facing the floating gate electrode via the tunnel insulating film.
Split gate transients to the step of forming the control gate electrode to be, comprising the
Star manufacturing method. 5. The split gate type transistor according to claim 4,
In the method of manufacturing a transistor , nitrogen ions are implanted when the tunnel insulating film is nitrided.
Method, exposure method to nitrogen plasma, heat treatment in nitriding atmosphere
Any one selected from the group consisting of how to do
Split gate type, characterized by using the method of (1).
Manufacturing method of transistor.