JP2008288479A - Evaluation element for non-volatile memory cell, semiconductor chip containing the same, wafer, and method for manufacturing the cell and chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To comprehend the electric characteristics of a split gate type non-volatile semiconductor memory with high precision. <P>SOLUTION: This evaluation element (1) for a non-volatile memory cell is configured of: a first insulating film (12) formed on a semiconductor substrate (4); a first conductor film (9) formed on the first insulating film (12); second and third conductor films (7)(8) formed so as to be faced to each other at the both ends of the first conductor film (9); and first and second diffusion layers (5)(6) formed inside the semiconductor substrate (4) positioned corresponding to the side faces of the second and third conductor films (7)(8). This evaluation element (1) is also configured of an electrode contact (16) for measurement, and a pad for applying a voltage is connected through the electrode contact (16) for measurement to the first conductor film (9). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an evaluation element for a nonvolatile memory cell, a semiconductor chip including the same, a manufacturing method thereof, and a wafer including an evaluation element for a nonvolatile memory cell, and more particularly to a split gate nonvolatile semiconductor memory. The present invention relates to an evaluation element for evaluating a nonvolatile memory cell constituting a device, a semiconductor chip including the evaluation element, a manufacturing method thereof, and a wafer including an evaluation element for the nonvolatile memory cell.

  A split gate type nonvolatile semiconductor memory device is known as a nonvolatile semiconductor memory device having a characteristic that stored contents do not disappear even when the power is turned off (see, for example, Patent Document 1). FIG. 1 is a cross-sectional view showing a configuration of a split gate nonvolatile semiconductor memory device (hereinafter referred to as a split gate nonvolatile memory) described in Patent Document 1 (US Pat. No. 6,525,371 B2). The split gate nonvolatile memory described in Patent Document 1 includes a plurality of storage elements (hereinafter referred to as split gate nonvolatile memory cells 101).

  As shown in FIG. 1, the split gate nonvolatile memory cell 101 includes a first source / drain diffusion layer 103 and a second source / drain diffusion layer 104. The first source / drain diffusion layer 103 and the second source / drain diffusion layer 104 are formed on the substrate 102. The split gate nonvolatile memory cell 101 includes a floating gate 105 and a control gate 106. The floating gate 105 is formed in an upper layer of the substrate 102 with a gate oxide film 107 interposed therebetween. The control gate 106 is formed on the upper layer of the substrate 102 with the tunnel oxide film 108 interposed therebetween. Further, a tunnel oxide film 108 is formed between the floating gate 105 and the control gate 106. A source plug 109 is formed on the first source / drain diffusion layer 103. The floating gate 105 has an acute angle portion. A spacer 111 is formed on the floating gate 105.

  The operation of the split gate nonvolatile memory cell 101 described in Patent Document 1 will be described with reference to the drawings. FIG. 2 is a diagram showing the operation of the conventional split gate nonvolatile memory cell 101. FIG. 2A shows a write operation of the split gate nonvolatile memory cell 101. FIG. 2B shows an erasing operation of the split gate nonvolatile memory cell 101. FIG. 2C shows the read operation of the split gate nonvolatile memory cell 101. Referring to FIG. 2A, when data is written in the split gate nonvolatile memory cell 101, the first source / drain diffusion layer 103 is used as a drain and the second source / drain diffusion layer 104 is used as a source. It acts as. In the split gate nonvolatile memory cell 101, the first source / drain diffusion layer 103 is set to a higher potential than the second source / drain diffusion layer 104 at the time of data writing. Thereby, hot electrons (electrons in a high energy state) are obtained on the source side of the channel. The hot electrons are injected into the floating gate 105 through the gate oxide film 107, whereby data is written. After writing, the floating gate becomes negatively charged.

  Referring to FIG. 2B, when erasing data in the split gate nonvolatile memory cell 101, electrons are extracted from the floating gate 105 to the control gate 106 through the tunnel oxide film 108 by a tunnel current. Erasing data. In other words, at the time of erasing, a voltage is applied to the control gate 106 to concentrate the electric field on the pointed portion (acute angle portion) of the floating gate 105 and extract electrons from the floating gate 105. After being erased, the floating gate becomes positively charged.

  Referring to FIG. 2C, when data is read from the split gate nonvolatile memory cell 101, a predetermined voltage is applied to the control gate 106, the control gate 106, the first source / drain diffusion layer 103, A transistor composed of the second source / drain diffusion layer 104 is activated. At this time, the value of the current flowing between the source and the drain changes in response to the charge injected into the floating gate 105. As a result, data is read out.

  There is a strong demand for a large capacity for a nonvolatile semiconductor memory device, and therefore, it is essential to miniaturize the split gate nonvolatile memory cell 101. In addition, there is a strong demand for low power consumption for nonvolatile semiconductor memory devices, and writing at a low voltage, erasing at a low voltage, and reading at a low current have been required. In order to satisfy these requirements, it is required that the electrical characteristics satisfy a wide variety of specifications.

  In order to determine whether or not each of the plurality of memory elements constituting the nonvolatile semiconductor memory device satisfies these specifications, a TEG (Test Element Group) is configured, and the electrical of the TEG The characteristics are being measured. For example, when measuring the electrical characteristics of a general MOS transistor using TEG, the drain current required is specified and the voltage applied to the gate is changed. Then, the gate voltage when a desired current flows is measured. As a result, a gate voltage necessary for flowing the specified drain current is obtained.

  Even when the electrical characteristics of the split gate nonvolatile memory cell 101 are obtained, it is preferable to configure a TEG (hereinafter referred to as a TEG for nonvolatile memory cells) and perform the same process. However, in the non-volatile memory cell TEG, the floating gate 105 is electrically insulated from other electrodes. Therefore, when obtaining the electrical characteristics of the split gate nonvolatile memory cell 101 using the TEG for nonvolatile memory cells, it is necessary to obtain the voltage of the floating gate 105 by calculation. In the conventional non-volatile memory cell TEG, the voltage of the floating gate 105 (hereinafter referred to as the voltage of the floating gate 105) is determined based on the capacitance formed by the control gate 106, the floating gate 105 and the tunnel oxide film 108 and the voltage applied to the control gate 106. , Called pseudo floating gate voltage).

FIG. 3 is a graph illustrating the electrical characteristics of the memory element obtained by the TEG for nonvolatile memory cells. For example, when a drain current of 10 ⁻⁶ amperes flows and the pseudo floating gate voltage is 4 volts, the first plot point P1 is plotted. By changing the value of the specified drain current and executing the same operation a plurality of times, a current-voltage characteristic graph G1 showing the electrical characteristics of the split gate nonvolatile memory cell 101 can be obtained. In the conventional nonvolatile semiconductor memory device, the impurity concentration, gate length, gate width, oxide film thickness, etc. of the split-gate nonvolatile memory cell 101 are changed based on the electrical characteristics measured by the TEG for nonvolatile memory cells. As a result, a nonvolatile semiconductor memory device conforming to the design has been configured.

US Pat. No. 6,525,371 B2

  When the conventional split gate nonvolatile memory cell 101 is applied to configure a TEG for a nonvolatile memory cell, a measurement terminal can be drawn from the control gate 106 or the source plug 109. However, in the non-volatile memory cell TEG, it is very difficult to configure a measurement terminal connected to the floating gate 105.

  As shown in FIG. 1 above, in order to form a test terminal that is directly connected to the floating gate 105, a connection having a diameter less than the spacer exposure width W1 and a depth of the spacer film thickness H1 is used. It is required to form a contact. However, the spacer exposure width W1 in the split gate nonvolatile memory cell 101 is very narrow. Therefore, in order to form a connection contact that reaches the floating gate 105 without contacting the control gate 106 or the source plug 109, a contact hole having a very small diameter must be formed with high alignment accuracy. In some cases, the manufacturing cost was increased. Therefore, when obtaining the electrical characteristics of the split gate type nonvolatile memory cell 101 using the TEG for the nonvolatile memory cell, the pseudo floating gate voltage obtained by the calculation as described above is used.

  With the demand for miniaturization of nonvolatile semiconductor memory devices, very precise device design is required. Therefore, a technique for measuring the electrical characteristics of the split gate nonvolatile memory cell 101 with higher accuracy than the measurement using the pseudo floating gate voltage has been demanded.

  The means for solving the problem will be described below using the numbers used in [Best Mode for Carrying Out the Invention]. These numbers are added to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

  In order to solve the above problems, a first insulating film (12) formed on a semiconductor substrate (4) and a first conductor film (1) formed on the first insulating film (12). 9), second and third conductor films (7) and (8) formed to face opposite ends of the first conductor film (9), and the second and third conductor films (9). A voltage can be applied to the first and second diffusion layers (5) and (6) formed in the semiconductor substrate (4) at a position corresponding to the side surfaces of the conductor films (7) and (8). An evaluation element (1) for a nonvolatile memory cell is provided, comprising a measurement electrode contact (16) for connecting a pad and the first conductive film (9).

  According to the present invention, the floating gate voltage can be obtained by actual measurement. Therefore, it is possible to grasp the electrical characteristics of the split gate nonvolatile semiconductor memory device with higher accuracy than the measurement using the pseudo floating gate voltage.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 4 is a cross-sectional view illustrating the configuration of the test element (TEG) 1 of this embodiment. The test element 1 in the present embodiment is an element used for testing a semiconductor chip. It is assumed that the semiconductor chip includes a memory area including a plurality of nonvolatile memory cells. The test element 1 of the present embodiment is effective when measuring the electrical characteristics of the nonvolatile memory cell in the information storage area.

  Referring to FIG. 4, the test element 1 is configured across the first memory cell region 2 and the second memory cell region 3. When normal nonvolatile memory cells are formed, one nonvolatile memory cell is formed in each of the first memory cell region 2 and the second memory cell region 3. The test element 1 is configured as a single element in which a nonvolatile memory cell pattern arranged in the first memory cell region 2 and a nonvolatile memory cell pattern arranged in the second memory cell region 3 are integrated. Yes. The test element 1 includes a first diffusion layer 5 formed on the semiconductor substrate 4 and a second diffusion layer 6 on which the semiconductor substrate 4 is formed. The first diffusion layer 5 is connected to the first diffusion layer contact 15, and the above-described second diffusion layer 6 is connected to the second diffusion device contact 17. The test element 1 includes a first region control gate 7, a second region control gate 8, and a measurement gate electrode 9.

  A first region tunnel insulating film 10 is formed between the first region control gate 7 and the semiconductor substrate 4. A first region control gate side silicide 18 is formed on the upper surface of the first region control gate 7, and the first region tunnel described above is provided between the side surface of the first region control gate 7 and the side surface of the measurement gate electrode 9. An insulating film 10 is configured. A second region tunnel insulating film 11 is formed between the second region control gate 8 and the semiconductor substrate 4. A second region control gate side silicide 19 is formed on the upper surface of the second region control gate 8, and the second region control gate 8 is interposed between the side surface of the second region control gate 8 and the other side surface of the measurement gate electrode 9. A region tunnel insulating film 11 is formed.

  A gate insulating film 12 is formed between the measurement gate electrode 9 and the semiconductor substrate 4. A first region spacer 13 and a second region spacer 14 are formed on the measurement gate electrode 9. The first region spacer 13 and the second region spacer 14 are configured to have a gap. A measurement electrode silicide 20 is formed in a portion corresponding to the surface of the measurement gate electrode 9 in the gap between the first region spacer 13 and the second region spacer 14. The measurement gate electrode 9 is connected to the measurement electrode contact 16 via the measurement electrode silicide 20. Further, as shown in FIG. 4, the measurement gate electrode 9 is configured such that the distance from the side surface to the other side surface is the first length L1. The first length L1 is preferably equal to the gate length (second length L2 described later) under the floating gate of the nonvolatile memory cell configured in the semiconductor chip of this embodiment.

  FIG. 5 is a plan view showing a layout pattern of the test element 1. The test element 1 is separated from a region where other elements are formed by the first element isolation 21 and the second element isolation 22. The first element isolation 21 and the second element isolation 22 are configured along the first direction. In the test element 1 of the present embodiment, the measurement gate electrode 9 is formed on the semiconductor substrate 4. The first region control gate 7 and the second region control gate 8 are formed on the semiconductor substrate 4 along the second direction. The first region control gate 7 and the second region control gate 8 are connected to a measurement terminal (not shown). In addition, the first diffusion layer contact 15, the measurement electrode contact 16, and the second diffusion contact 17 are arranged along a line segment A-A 'parallel to the first direction. The first diffusion layer contact 15, the measurement electrode contact 16, and the second diffusion equipment contact 17 function as measurement terminals. Note that the cross-sectional view illustrated in FIG. 4 described above represents a cross section taken along line A-A ′.

  FIG. 6 is a cross-sectional view illustrating a cross section taken along line B-B ′ in the above-described plan view. The first element isolation 21 and the second element isolation 22 are configured with a predetermined depth from the surface of the semiconductor substrate 4. An insulating film is formed on the first element isolation 21 and the second element isolation 22. By the first element isolation 21 and the second element isolation 22, the test element 1 is isolated from the region where other elements are formed.

  FIG. 7 is a cross-sectional view illustrating the configuration of a split gate nonvolatile memory cell configured in the memory region of the semiconductor chip of this embodiment. FIG. 7 illustrates a cross-sectional view in which the configuration of the split gate nonvolatile memory cell is simplified. In the split gate nonvolatile memory cell of this embodiment, writing is performed by channel hot electrons generated in the substrate being injected into the floating gate. Data is erased by extracting electrons from the floating gate to the control gate. Furthermore, the state (ON, OFF) of the memory cell is detected by applying a read voltage to the control gate. The data erasing operation in the present invention is not limited to the above erasing method. In the present embodiment, the split of FIG. 7 is performed based on the measurement result obtained by measuring the electrical characteristics of the test element 1 described above (for example, the current-voltage characteristics of the region under the measurement gate electrode 9). The electrical characteristics of the gate type nonvolatile memory cell are confirmed. If the measurement result does not correspond to the design specification, an appropriate semiconductor chip can be configured by changing the design.

  Referring to FIG. 7, in the semiconductor chip of this embodiment, two transistors (a first split gate type nonvolatile memory cell 31 and a second split gate type nonvolatile memory cell 32) are configured symmetrically. The first split gate nonvolatile memory cell 31 and the second split gate nonvolatile memory cell 32 of the present embodiment have a self-alignment technique (a technique that can be processed without mask alignment. A pattern already formed on the substrate. In this technique, the pattern is used as a mask for etching, impurity diffusion, etc.). For example, when the first nonvolatile memory floating gate 36 is formed, the first nonvolatile memory floating gate 36 is formed by using the first nonvolatile memory side spacer 39 as a mask.

  The first split gate nonvolatile memory cell 31 and the second split gate nonvolatile memory cell 32 operate independently of each other. The first split gate nonvolatile memory cell 31 includes a source diffusion layer 33, a first nonvolatile memory side drain diffusion layer 34, a first nonvolatile memory side control gate 35, and a first nonvolatile memory floating gate 36. It is comprised including. The source diffusion layer 33 and the first nonvolatile memory side drain diffusion layer 34 are formed in the semiconductor substrate 4. The semiconductor substrate 4 includes a channel region between the source diffusion layer 33 and the first nonvolatile memory side drain diffusion layer 34. In the embodiment described below, the description will be made on the assumption that the semiconductor substrate 4 is a P-type semiconductor substrate. This does not mean that the semiconductor substrate 4 in the present invention is limited to a P-type semiconductor substrate.

  The source diffusion layer 33 is composed of a diffusion region in which impurities are diffused. The source diffusion layer 33 functions as a drain when the storage content is written in the first split gate nonvolatile memory cell 31. The source diffusion layer 33 functions as a source when reading stored contents from the first split gate nonvolatile memory cell 31. Similarly to the source diffusion layer 33, the first nonvolatile memory side drain diffusion layer 34 is also composed of a diffusion region in which impurities are diffused. The first non-volatile memory side drain diffusion layer 34 functions as a source when the memory content is written in the first split gate type non-volatile memory cell 31. The first nonvolatile memory side drain diffusion layer 34 functions as a drain when reading the stored contents from the first split gate nonvolatile memory cell 31.

  The first nonvolatile memory floating gate 36 is formed in the upper layer of the semiconductor substrate 4 via the first nonvolatile memory side gate insulating film 37. The first non-volatile memory side control gate 35 is formed in an upper layer of the semiconductor substrate 4 via a first non-volatile memory side tunnel insulating film 38 acting as a gate insulating film. The first nonvolatile memory floating gate 36 and the first nonvolatile memory side control gate 35 are configured to be adjacent to each other via the first nonvolatile memory side tunnel insulating film 38. A first non-volatile memory side spacer 39 is formed on the first non-volatile memory floating gate 36. A source plug 41 is formed on the source diffusion layer 33. The source plug 41 and the first nonvolatile memory floating gate 36 are electrically insulated by the action of the second sidewall 57. Therefore, the first nonvolatile memory floating gate 36 has the functions of the first nonvolatile memory side gate insulating film 37, the first nonvolatile memory side tunnel insulating film 38, the first nonvolatile memory side spacer 39, and the second sidewall 57. Thus, it is electrically insulated from other conductor portions. The first nonvolatile memory floating gate 36 is configured to include an acute angle portion on the first nonvolatile memory side control gate 35 side. The acute angle portion of the first nonvolatile memory floating gate 36 is formed at an angle at which the data erasing operation can be performed accurately and stably.

  The first nonvolatile memory side drain diffusion layer 34 is connected to the first nonvolatile memory side contact 42 via the first nonvolatile memory side drain diffusion layer silicide 45 formed in the first nonvolatile memory side drain diffusion layer 34. It is connected. The first nonvolatile memory side contact 42 is connected to an upper layer wiring (not shown). The first nonvolatile memory side contact 42 supplies a predetermined voltage to the first nonvolatile memory side drain diffusion layer 34 via the first nonvolatile memory side drain diffusion layer silicide 45. A first nonvolatile memory side control gate silicide 44 is formed on the upper surface of the first nonvolatile memory side control gate 35, and a first sidewall 56 is formed on the side surface. A source plug silicide 43 is formed on the upper surface of the source plug 41.

  The second split gate nonvolatile memory cell 32 is configured in the same manner as the first split gate nonvolatile memory cell 31. The second split gate nonvolatile memory cell 32 includes a source diffusion layer 33, a second nonvolatile memory side drain diffusion layer 46, a second nonvolatile memory side control gate 47, and a second nonvolatile memory floating gate 48. It is comprised including. The source diffusion layer 33 and the second nonvolatile memory side drain diffusion layer 46 are formed on the semiconductor substrate 4. The semiconductor substrate 4 includes a channel region between the source diffusion layer 33 and the second nonvolatile memory side drain diffusion layer 46. The source diffusion layer 33 functions as a drain when the stored content is written in the second split gate nonvolatile memory cell 32. The source diffusion layer 33 functions as a source when reading stored contents from the second split gate nonvolatile memory cell 32. Similarly to the first nonvolatile memory side drain diffusion layer 34, the second nonvolatile memory side drain diffusion layer 46 is also formed of a diffusion region in which impurities are diffused. The second non-volatile memory side drain diffusion layer 46 functions as a source when the memory content is written in the second split gate non-volatile memory cell 32. In addition, the second nonvolatile memory side drain diffusion layer 46 functions as a drain when the stored content is read from the second split gate nonvolatile memory cell 32.

  The second nonvolatile memory floating gate 48 is formed in the upper layer of the semiconductor substrate 4 via the second nonvolatile memory side gate insulating film 49. The second non-volatile memory side control gate 47 is formed in an upper layer of the semiconductor substrate 4 via a second non-volatile memory side tunnel insulating film 51 that acts as a gate insulating film. The second nonvolatile memory floating gate 48 and the second nonvolatile memory side control gate 47 are configured to be adjacent to each other via the second nonvolatile memory side tunnel insulating film 51. A second non-volatile memory side spacer 52 is formed in an upper layer of the second non-volatile memory floating gate 48. The source plug 41 and the second nonvolatile memory floating gate 48 are electrically insulated by the action of the third sidewall 58. Therefore, the second non-volatile memory floating gate 48 has the functions of the second non-volatile memory side gate insulating film 49, the second non-volatile memory side tunnel insulating film 51, the second non-volatile memory side spacer 52, and the third sidewall 58. Thus, it is electrically insulated from other conductor portions. The second nonvolatile memory floating gate 48 is configured to include an acute angle portion on the second nonvolatile memory side control gate 47 side. The acute angle portion of the second nonvolatile memory floating gate 48 is formed at an angle at which the data erasing operation can be performed accurately and stably.

  The second nonvolatile memory side drain diffusion layer 46 is connected to the second nonvolatile memory side contact 53 via the second nonvolatile memory side drain diffusion layer silicide 55 formed in the second nonvolatile memory side drain diffusion layer 46. It is connected. The second nonvolatile memory side contact 53 is connected to an upper layer wiring (not shown) and supplies a predetermined voltage to the second nonvolatile memory side drain diffusion layer 46. A second nonvolatile memory side control gate silicide 54 is formed on the upper surface of the second nonvolatile memory side control gate 47, and a fourth sidewall 59 is formed on the side surface.

As shown in FIG. 7, the first nonvolatile memory floating gate 36 has an effective gate length (in the channel region between the source diffusion layer 33 and the first nonvolatile memory side drain diffusion layer 34). The length from the end of the source diffusion layer 33 to the end of the first nonvolatile memory floating gate 36) is configured to be the second length L2. Similarly, the second nonvolatile memory floating gate 48 is configured such that the effective gate length is the second length L2 in the channel region between the source diffusion layer 33 and the second nonvolatile memory side drain diffusion layer 46. Has been. In the present embodiment, the first length L1 in the test element 1 described above is
1st length L1 = 2nd length L2
It is preferable to configure so as to satisfy this relationship. By making the first length L1 of the test element 1 the same as the second length L2, the first split gate nonvolatile memory cell 31 (or the second split gate nonvolatile memory cell 32) It becomes possible to measure electrical characteristics more precisely.

  FIG. 8 is a plan view showing a layout pattern of the first split gate nonvolatile memory cell 31 and the second split gate nonvolatile memory cell 32. The first split gate nonvolatile memory cell 31 and the second split gate nonvolatile memory cell 32 are separated from the region where other elements are formed by the first element isolation 21 and the second element isolation 22. Yes. The first element isolation 21 and the second element isolation 22 are configured along the first direction. The first nonvolatile memory floating gate 36 of the first split gate nonvolatile memory cell 31 is configured on the semiconductor substrate 4 via an insulating film (not shown). Similarly, the second nonvolatile memory floating gate 48 of the second split gate nonvolatile memory cell 32 is also formed on the semiconductor substrate 4 via an insulating film (not shown).

  The first nonvolatile memory side control gate 35, the source plug 41, and the second nonvolatile memory side control gate 47 are configured along a second direction that is perpendicular to the first direction. The first nonvolatile memory side control gate 35 and the second nonvolatile memory side control gate 47 are connected to a measurement terminal (not shown). In addition, the first nonvolatile memory side contact 42 and the second nonvolatile memory side contact 53 are arranged along a line segment C-C ′ parallel to the first direction. Note that the cross-sectional view illustrated in FIG. 7 described above represents a cross section of the line segment C-C ′.

  FIG. 9 is a cross-sectional view illustrating a cross section of a line segment D-D ′ in the plan view of FIG. 8. The first element isolation 21 and the second element isolation 22 are configured with a predetermined depth from the surface of the semiconductor substrate 4. A source plug 41 is formed on the first element isolation 21 and the second element isolation 22. The source diffusion layer 33 connected to the source plug 41 is separated from the region where other elements are formed by the first element isolation 21 and the second element isolation 22.

  FIG. 10 is a plan view illustrating the configuration of the wafer substrate 23 including the test element 1 of this embodiment. The wafer substrate 23 includes a plurality of circuit patterns that are cut into a plurality of semiconductor chips. The region 24 is a region including one of the plurality of circuit patterns. The circuit pattern (semiconductor chip) 25 in the region 24 is a circuit pattern that becomes a semiconductor chip by dicing the wafer substrate 23 along the scribe line 26. The circuit pattern (semiconductor chip) 25 includes a nonvolatile memory area 27. The nonvolatile memory area 27 includes a plurality of first split gate nonvolatile memory cells 31 (or second split gate nonvolatile memory cells 32).

  A test element 1 is configured on the wafer substrate 23. As shown in FIG. 10, in the present embodiment, there is no restriction on the position where the test element 1 is arranged. When the test element 1 is used for a test performed before dicing the wafer substrate 23 and is not used for a test after dicing, the test element 1 is preferably configured on the scribe line 26. When the test element 1 is used for inspection of the semiconductor chip after dicing, it is preferable to configure a circuit pattern (semiconductor chip) 25 including the test element 1. In addition, by forming the test element 1 in the vicinity of the nonvolatile memory region 27, manufacturing variations between the test element 1 and the first split gate nonvolatile memory cell 31 (or the second split gate nonvolatile memory cell 32). Can be suppressed.

  Hereinafter, an operation for manufacturing the test element 1 of the present embodiment will be described. FIG. 11 illustrates a first stage process for manufacturing the test element 1 of the present embodiment. FIG. 11A shows the first step of the first stage. FIG. 11B shows the second step of the first stage. FIG. 11C shows the third step in the first stage. In the first step of the first stage, first, a first oxide film 61 is formed on the semiconductor substrate 4. Then, a first polysilicon film 62 is formed on the first oxide film 61. Further, a first nitride film 63 is formed on the first polysilicon film 62. The first oxide film 61 is an oxide film that becomes the gate insulating film 12 of the test element 1. The first polysilicon film 62 is a polysilicon film that becomes the measurement gate electrode 9 of the test element 1.

  In the second step of the first stage, a photoresist (not shown) is formed on the first nitride film 63. Then, the first nitride film 63 is patterned by dry etching to form an opening 64 in the first nitride film 63. In the third step of the first stage, the inclined portion 65 is formed by etching the first polysilicon film 62 exposed through the opening 64 into a slope shape. In the first stage, the opening 64 is preferably formed so that the opening width of the opening 64 is the same as the first length L1 of the test element 1. Further, when configuring a plurality of test elements 1, the openings 64 having different opening widths may be formed. As a result, it is possible to configure the test elements 1 having different lengths of the measurement gate electrode 9. By configuring a plurality of test elements 1 having different lengths of the measurement gate electrode 9, it is possible to design a more precise device based on the difference in electrical characteristics obtained from the measurement results. Become.

  FIG. 12 illustrates a second stage process for manufacturing the test element 1 of the present embodiment. FIG. 12A shows the first step in the second stage. FIG. 12B shows the second step of the second stage. FIG. 12C shows the third step in the second stage. In the first step of the second stage, a second oxide film 66 is formed so as to cover the first nitride film 63 and the opening 64. In the second step of the second stage, the second oxide film 66 is etched back to form the first region spacer 13 and the second region spacer 14. In the third step of the second stage, a third oxide film 67 is formed so as to cover the first region spacer 13, the second region spacer 14, the exposed portion of the first polysilicon film 62 and the first nitride film 63. .

  In this second stage, the thickness of the second oxide film 66 is such that when the second oxide film 66 is etched back, the first region spacer 13 and the second region spacer 14 are formed on the side of the first nitride film 63. The film thickness is preferably configured as a wall. The thickness of the third oxide film 67 is preferably the same as that of the first oxide film 61.

  FIG. 13 illustrates a third stage process for manufacturing the test element 1 of the present embodiment. FIG. 13A shows the first step of the third stage. FIG. 13B shows the second step of the third stage. FIG. 13C shows a third step in the third stage. In the first step of the third stage, a second nitride film 68 is formed on the third oxide film 67. In the second step of the third stage, a resist (not shown) is formed on the second nitride film 68. This resist is formed only in a region where the test element 1 is formed. In other regions not masked with resist, a process different from the process of forming the test element 1 in order to form the first split gate nonvolatile memory cell 31 and the second split gate nonvolatile memory cell 32. (Detailed steps will be described later) are executed. In a region where the first split gate nonvolatile memory cell 31 and the second split gate nonvolatile memory cell 32 are formed, the resist is removed when a predetermined process is completed. Then, the second nitride film 68 is etched until the third oxide film 67 is exposed. At this time, the surface of the etched second nitride film 68 is set to the same height as the surface of the third oxide film 67. In the third step of the third stage, the third oxide film 67 is etched back to expose the surface of the first nitride film 63.

  In the third stage, the opening formed between the first region spacer 13 and the second region spacer 14 is filled with the second nitride film 68. Steps for forming the first split gate type nonvolatile memory cell 31 and the second split gate type nonvolatile memory cell 32 in other regions not masked by the resist in the second step of the third stage (details) This process will be described later). In the region where the test element 1 is formed, the first split gate nonvolatile memory cell 31 and the second split gate nonvolatile memory cell 32 are formed (for example, the nonvolatile memory region 27). The state shown in FIG. 13C is maintained until the source plug 41 is formed.

  FIG. 14 illustrates a fourth stage process for manufacturing the test element 1 of the present embodiment. FIG. 14A shows the first step in the fourth stage. FIG. 14B shows the second step in the fourth stage. FIG. 14C shows the third step in the fourth stage. In the first step of the fourth stage, the second nitride film 68 and the first nitride film 63 are removed. In the second step of the fourth step, the first polysilicon film 62 is etched using the first region spacer 13, the second region spacer 14, and the third oxide film 67 as a mask. By etching the first polysilicon film 62, the surface of the first oxide film 61 is exposed. In the third step of the fourth stage, the exposed first oxide film 61 and third oxide film 67 are removed by wet etching.

  In the fourth step, the second nitride film 68 filling the opening formed between the first region spacer 13 and the second region spacer 14 is removed. Then, the measurement gate electrode 9 and the gate insulating film 12 are formed using the first region spacer 13, the second region spacer 14, and the third oxide film 67 as a mask. Through the steps so far, the first nonvolatile memory floating gate 36 of the first split gate nonvolatile memory cell 31 and the second nonvolatile memory floating gate 48 of the second split gate nonvolatile memory cell 32 are integrated. A measurement gate electrode 9 is formed.

  FIG. 15 illustrates a fifth stage process for manufacturing the test element 1 of the present embodiment. FIG. 15A shows the first step in the fifth stage. FIG. 15B shows the second step of the fifth stage. FIG. 15C shows a third step in the fifth stage. In the first step of the fifth stage, a fourth oxide film 69 is formed so as to cover the surface of the semiconductor substrate 4, the first region spacer 13, the second region spacer 14, and the measurement gate electrode 9. Further, a second polysilicon film 70 is formed on the fourth oxide film 69. The fourth oxide film 69 becomes the first region tunnel insulating film 10 and the second region tunnel insulating film 11 in a later step. The second polysilicon film 70 becomes the first region control gate 7 and the second region control gate 8 in a later process.

In the second step of the fifth stage, the second polysilicon film 70 is etched to form the first region control gate 7 and the second region control gate 8. At this time, the fourth oxide film 69 on the first region spacer 13, the second region spacer 14, and the measurement gate electrode 9 is exposed. In the third step of the fifth stage, the first sidewall 28 and the second sidewall 29 are formed on the exposed fourth oxide film 69, the first region control gate 7, the second region control gate 8 and the semiconductor substrate 4. A film (oxide film) for forming is formed. Then, the film is etched back to form the first sidewall 28 and the second sidewall 29, and the fourth oxide film 69 on the first region spacer 13, the second region spacer 14, and the measurement gate electrode 9. Are simultaneously etched. Thereby, the first region tunnel insulating film 10 and the second region tunnel insulating film 11 are formed. Further, the surface of the measurement gate electrode 9 is exposed in a region between the first region spacer 13 and the second region spacer 14.
In the third step of the fifth stage, the exposed fourth oxide film 69 is etched to form the first region tunnel insulating film 10 and the second region tunnel insulating film 11, and then the test element is further formed. Etching back may be performed after an oxide film is formed so as to cover the entire surface. Thus, the first sidewall 28 can be formed on the side surface of the first region control gate 7, and the second sidewall 29 can be formed on the side surface of the second region control gate 8.

  In the fifth stage, after the first region control gate 7 and the second region control gate 8 are formed, the oxide film formed in the upper layer of the measurement gate electrode 9 is removed. This makes it possible to form a contact connected to the measurement gate electrode 9 without using an insulator.

  FIG. 16 illustrates a sixth stage process for manufacturing the test element 1 of the present embodiment. FIG. 16A shows the first step of the sixth stage. FIG. 16B shows the second step in the sixth stage. In the first step of the sixth stage, impurities are implanted into the semiconductor substrate 4 to form the first diffusion layer 5 and the second diffusion layer 6. Thereafter, a first diffusion layer silicide 15 a and a second diffusion layer silicide 17 a are formed on the surface of the semiconductor substrate 4. At this time, the first region control gate side silicide 18 is formed on the surface of the first region control gate 7, and the second region control gate side silicide 19 is formed on the surface of the second region control gate 8. Then, a measurement electrode silicide 20 is formed on the surface of the measurement gate electrode 9. In the second step of the sixth stage, the first diffusion layer contact 15 connected to the first diffusion layer silicide 15a, the second diffusion contact 17 connected to the second diffusion layer silicide 17a, and the measurement electrode silicide 20 A measurement electrode contact 16 to be connected is formed.

  By configuring the test element 1 according to the manufacturing process described above, it is possible to manufacture the test element 1 using the self-alignment technique. With this test element 1, the floating gate voltage can be obtained by actual measurement. Therefore, the electrical characteristics can be measured with higher accuracy than when the floating gate voltage obtained by calculation is used.

  The first split gate nonvolatile memory cell 31 (or the second split gate nonvolatile memory cell 32) of this embodiment can be performed simultaneously with the manufacture of the test element 1. More specifically, in a region where the first split gate nonvolatile memory cell 31 and the second split gate nonvolatile memory cell 32 are formed (hereinafter referred to as a memory cell formation region), a region where the test element 1 is formed. Substantially the same steps are executed up to the second stage (hereinafter referred to as the TEG region). Therefore, in the following, in order to facilitate understanding of the present invention, the first split gate nonvolatile memory cell 31 and the second split gate nonvolatile memory with reference to the drawings, focusing on the steps different from the steps in the TEG region. The manufacturing process of the memory cell 32 will be described.

  FIG. 17 illustrates a third stage process in the memory cell formation region. FIG. 17A shows the first step in the third stage. FIG. 17B shows the second step in the third stage. FIG. 17C shows a third step in the third stage. In the first step of the third stage, the second nitride film 68 is etched to expose the third oxide film 67 in the memory cell formation region. By this etching, it is preferable that the thickness of the second nitride film 68 in the memory cell formation region is smaller than the thickness of the second nitride film 68 to be removed later in the TEG region. In the second step of the third stage, the second nitride film 68 between the first nonvolatile memory side spacer 39 and the second nonvolatile memory side spacer 52 is removed. At this time, in the TEG region, the second nitride film 68 fills the space between the first region spacer 13 and the second region spacer 14. In the third step of the third stage, the third oxide film 67 is etched back and removed. In the memory cell formation region, the surface of the first polysilicon film 62 between the first nonvolatile memory side spacer 39 and the second nonvolatile memory side spacer 52 is exposed by removing the third oxide film 67. .

  FIG. 18 illustrates a third step in the memory cell formation region. FIG. 18A shows a fourth step in the third stage. FIG. 18B shows a fifth step in the third stage. FIG. 18C shows a sixth step in the third stage. In the fourth step of the third stage, the first polysilicon film 62 is etched using the first nonvolatile memory side spacer 39 and the second nonvolatile memory side spacer 52 as a mask. Then, the first oxide film 61 exposed by the etching is removed by etching, and the surface of the semiconductor substrate 4 is exposed. In the fifth step of the third stage, a thin oxide film is formed so as to cover the first nitride film 63, the first nonvolatile memory side spacer 39, the semiconductor substrate 4, and the second nonvolatile memory side spacer 52. Then, the oxide film is etched back to form the second sidewall 57 and the third sidewall 58. In addition to the second side wall 57 and the third side wall 58, ion implantation is performed using the first non-volatile memory side spacer 39 and the second non-volatile memory side spacer 52 previously formed as a mask, and a source diffusion layer is formed. 33 is constituted. In the sixth step of the third stage, the source plug 41 is formed between the first nonvolatile memory side spacer 39 and the second nonvolatile memory side spacer 52. Then, a protective oxide film 41 a is formed on the surface of the source plug 41.

  FIG. 19 illustrates a fourth step in the memory cell formation region. FIG. 19A shows the first step in the fourth stage. FIG. 19B shows the second step in the fourth stage. FIG. 19C shows the third step in the fourth stage. In the first step of the fourth stage, the first nitride film 63 is removed. At this time, in the TEG region, the first nitride film 63 and the second nitride film 68 between the first region spacer 13 and the second region spacer 14 are also removed. In the second step of the fourth stage, the first polysilicon film 62 is etched using the first nonvolatile memory side spacer 39, the second nonvolatile memory side spacer 52, and the protective oxide film 41a as a mask. In the memory cell formation region, the first nonvolatile memory floating gate 36 and the second nonvolatile memory floating gate 48 are formed by this process. In the TEG region, the measurement gate electrode 9 is formed by this process. Therefore, in the present embodiment, the first nonvolatile memory floating gate 36, the second nonvolatile memory floating gate 48, and the measurement gate electrode 9 can be manufactured simultaneously. In the third step of the fourth stage, the first oxide film 61 and the protective oxide film 41a are removed by wet etching. In the memory cell formation region, the first nonvolatile memory side gate insulating film 37 and the second nonvolatile memory side gate insulating film 49 are formed by this process. In the TEG region, the gate insulating film 12 is formed by this process. Therefore, in the present embodiment, the first nonvolatile memory side gate insulating film 37, the second nonvolatile memory side gate insulating film 49, and the gate insulating film 12 can be manufactured simultaneously.

  FIG. 20 illustrates the fifth step in the memory cell formation region. FIG. 20A shows the first step in the fifth stage. FIG. 20B shows the second step in the fifth stage. FIG. 20C shows a third step in the fifth stage. In the first step of the fifth stage, a fourth oxide film 69 is formed so as to cover the surface of the semiconductor substrate 4, the first nonvolatile memory side spacer 39, the second nonvolatile memory side spacer 52, and the source plug 41. Further, a second polysilicon film 70 is formed on the fourth oxide film 69. The fourth oxide film 69 becomes the first nonvolatile memory side tunnel insulating film 51 and the second nonvolatile memory side tunnel insulating film 51 in a later process. In addition, the second polysilicon film 70 becomes the first nonvolatile memory side control gate 35 and the second nonvolatile memory side control gate 47 in a later process.

In the second step of the fifth stage, the second polysilicon film 70 is etched to form the first nonvolatile memory side control gate 35 and the second nonvolatile memory side control gate 47. At this time, the fourth oxide film 69 on the first nonvolatile memory side spacer 39, the second nonvolatile memory side spacer 52, and the source plug 41 is exposed. In the third step of the fifth stage, on the exposed fourth oxide film 69, the first nonvolatile memory side control gate 35, the second nonvolatile memory side control gate 47 and the semiconductor substrate 4, the first sidewall 56 and A film (oxide film) for forming the fourth sidewall 59 is formed. Then, the film is etched back to form the first sidewall 56 and the fourth sidewall 59, and the first nonvolatile memory side spacer 39, the second nonvolatile memory side spacer 52, and the first plug on the source plug 41. The four oxide films 69 are etched simultaneously. Thus, the first nonvolatile memory side tunnel insulating film 38 and the second nonvolatile memory side tunnel insulating film 51 are formed. Further, the surface of the source plug 41 is exposed.
In the third step of the fifth stage, the exposed fourth oxide film 69 is etched to form and source the first nonvolatile memory side tunnel insulating film 38 and the second nonvolatile memory side tunnel insulating film 51. The surface of the plug 41 may be exposed first. Thereafter, an oxide film may be formed over the entire memory cell formation region and then etched back. Thus, the first sidewall 56 can be formed on the side surface of the first nonvolatile memory side control gate 35, and the fourth sidewall 59 can be formed on the side surface of the second nonvolatile memory side control gate 47.

  FIG. 21 illustrates the sixth step in the memory cell formation region. FIG. 21A shows the first step of the sixth stage. FIG. 21B shows the second step in the sixth stage. In the first step of the sixth stage, impurities are implanted into the semiconductor substrate 4 to form the first nonvolatile memory side drain diffusion layer 34 and the second nonvolatile memory side drain diffusion layer 46. Thereafter, a first nonvolatile memory side drain diffusion layer silicide 45 and a second nonvolatile memory side drain diffusion layer silicide 55 are formed on the surface of the semiconductor substrate 4. At this time, the first nonvolatile memory side control gate silicide 44 is formed on the surface of the first nonvolatile memory side control gate 35, and the second nonvolatile memory side control gate 47 is formed on the surface of the second nonvolatile memory side control gate 47. Silicide 54 is formed. Then, a source plug silicide 43 is formed on the surface of the source plug 41. In the second step of the sixth stage, the first nonvolatile memory side contact 42 connected to the first nonvolatile memory side drain diffusion layer silicide 45 and the second nonvolatile memory connected to the second nonvolatile memory side drain diffusion layer silicide 55. The memory side contact 53 is formed.

By configuring the first split gate nonvolatile memory cell 31 and the second split gate nonvolatile memory cell 32 in accordance with the manufacturing process described above, the split gate nonvolatile memory can be manufactured using the self-alignment technique. It becomes possible. Further, the manufacturing process of the test element 1 and the manufacturing process of the split gate nonvolatile memory can be simultaneously manufactured in a series of manufacturing steps. Compared with the case where the test element 1 is manufactured after the first split gate type nonvolatile memory cell 31 (or the second split gate type nonvolatile memory cell 32) is manufactured, the number of man-hours related to the manufacture of the test element 1 is increased. Can be suppressed. In addition, when the test transistor is formed using the completed first split gate nonvolatile memory cell 31 (or the second split gate nonvolatile memory cell 32), the floating gate voltage measured by actual measurement is impossible. Can be measured. Therefore, the electrical characteristics can be measured with higher accuracy than when the floating gate voltage obtained by calculation is used.
In the embodiment described above, the third oxide film 67 and the second nitride film 68 in the process of manufacturing the test element (TEG) 1 are not necessarily formed on the first region spacer 13 and the second region spacer 14. There is no need to be. The third oxide film 67 and the second nitride film 68 only need to have a function of masking the surface of the first polysilicon film 62 between the first region spacer 13 and the second region spacer 14. The third oxide film 67 and the second nitride film 68 are formed when the first polysilicon film 62 between the first nonvolatile memory side spacer 39 and the second nonvolatile memory side spacer 52 is etched. If the first polysilicon film 62 has a function of suppressing etching, the measurement gate electrode 9 of the test element (TEG) 1 can be appropriately configured.

[Second Embodiment]
Below, with reference to drawings, 2nd Embodiment for implementing this invention is described. FIG. 22 is a cross-sectional view illustrating a cross-sectional configuration of the test element 1 of the second embodiment. The test element 1 of the second embodiment is manufactured without using a self-alignment technique. Therefore, the test element 1 of the second embodiment has a very different shape from the test element 1 of the first embodiment. In the test element 1 of the second embodiment, an opening is formed between the first region control gate 7 and the second region control gate 8 in the manufacturing process. As shown in FIG. 22, the test element 1 includes a measurement electrode contact 16 connected to the measurement gate electrode 9 using the opening.

  In the manufacturing process of the test element 1 of the second embodiment, an oxide film to be the first region tunnel insulating film 10 and the second region tunnel insulating film 11 is formed, and the first region control gate 7 and the oxide film are formed on the oxide film. A polysilicon film to be the second region control gate 8 is formed. Thereafter, patterning is performed to form the measurement gate electrode 9, and etching is performed according to the pattern. At this time, the etching is finished when the polysilicon film to be the measurement gate electrode 9 is exposed by the etching. Thus, an opening is formed between the first region control gate 7 and the second region control gate 8, and the measurement electrode contact 16 connected to the measurement gate electrode 9 is configured using the opening. ing. As described above, the test element 1 of the second embodiment is manufactured without using the self-alignment technique. Therefore, patterning using a resist is performed as necessary. In the test element 1 of the second embodiment, the measurement electrode contact 16 is formed according to the pattern for forming the measurement gate electrode 9.

In the above-described plurality of embodiments, the case where the first length L1 is equal to the second length L2 has been described as an example. This does not limit the configuration of the test element 1 of the present embodiment. For example,
1st length L1 ≠ 2nd length L2
In such a case, it is possible to perform high-accuracy measurement in the same manner as in the above-described embodiment by correcting using a predetermined arithmetic expression. Further, the above-described plurality of embodiments can be implemented in combination within a range in which there is no contradiction in the configuration and operation.

FIG. 1 is a cross-sectional view showing a configuration of a conventional split gate nonvolatile semiconductor memory device. FIG. 2 is a diagram showing the operation of the conventional split gate nonvolatile memory cell 101. FIG. 3 is a graph illustrating the electrical characteristics of the transistor. FIG. 4 is a cross-sectional view illustrating the configuration of the test element (TEG) 1 of the first embodiment. FIG. 5 is a plan view showing a layout pattern of the test element 1. FIG. 6 is a cross-sectional view illustrating a cross section of the test element 1. FIG. 7 is a cross-sectional view illustrating the configuration of a split gate nonvolatile memory cell. FIG. 8 is a plan view showing a layout pattern of the split gate type nonvolatile memory cell. FIG. 9 is a cross-sectional view illustrating a cross section of a split gate nonvolatile memory cell. FIG. 10 is a plan view illustrating the configuration of the wafer substrate 23 including the test element 1 of this embodiment. FIG. 11 is a diagram illustrating a first stage process for manufacturing the test element 1 of the present embodiment. FIG. 12 is a diagram illustrating a second stage process for manufacturing the test element 1 of the present embodiment. FIG. 13 is a diagram illustrating a third stage process for manufacturing the test element 1 of the present embodiment. FIG. 14 is a diagram illustrating a fourth step of manufacturing the test element 1 of this embodiment. FIG. 15 is a diagram illustrating a fifth step of manufacturing the test element 1 of this embodiment. FIG. 16 is a diagram illustrating a sixth step of manufacturing the test element 1 of this embodiment. FIG. 17 is a diagram illustrating a third step in the memory cell formation region. FIG. 18 is a diagram illustrating a third step in the memory cell formation region. FIG. 19 is a diagram illustrating a fourth step in the memory cell formation region. FIG. 20 is a diagram illustrating a fifth step in the memory cell formation region. FIG. 21 is a diagram illustrating a sixth step in the memory cell formation region. FIG. 22 is a cross-sectional view illustrating the configuration of the test element (TEG) 1 of the second embodiment.

Explanation of symbols

1 ... Test element (TEG)
2 ... 1st memory cell area 3 ... 2nd memory cell area 4 ... Semiconductor substrate 5 ... 1st diffusion layer 6 ... 2nd diffusion layer 7 ... 1st area | region control gate 8 ... 2nd area | region control gate 9 ... Gate electrode for a measurement DESCRIPTION OF SYMBOLS 10 ... 1st area | region tunnel insulating film 11 ... 2nd area | region tunnel insulating film 12 ... Gate insulating film 13 ... 1st area | region spacer 14 ... 2nd area | region spacer 15 ... 1st diffusion layer contact 15a ... 1st diffusion layer silicide 16 ... Measurement electrode contact 17 ... second diffusion device contact 17a ... second diffusion layer silicide 18 ... first region control gate side silicide 19 ... second region control gate side silicide 20 ... measurement electrode silicide 21 ... first element isolation 22 ... Second element isolation 23 ... wafer substrate 24 ... region 25 ... circuit pattern (semiconductor chip)
26 ... scribe line 27 ... nonvolatile memory region 28 ... first sidewall 29 ... second sidewall 31 ... first split gate type nonvolatile memory cell 32 ... second split gate type nonvolatile memory cell 33 ... source diffusion layer 34 ... First nonvolatile memory side drain diffusion layer 35 ... First nonvolatile memory side control gate 36 ... First nonvolatile memory floating gate 37 ... First nonvolatile memory side gate insulating film 38 ... First nonvolatile memory side tunnel insulation Film 39 ... First nonvolatile memory side spacer 41 ... Source plug 41a ... Protective oxide film 42 ... First nonvolatile memory side contact 43 ... Source plug silicide 44 ... First nonvolatile memory side control gate silicide 45 ... First nonvolatile Memory side drain diffusion layer silicide 46... Second nonvolatile Memory-side drain diffusion layer 47 ... second nonvolatile memory side control gate 48 ... second nonvolatile memory floating gate 49 ... second nonvolatile memory-side gate insulating film 51 ... second nonvolatile memory-side tunnel insulating film 52 ... second Non-volatile memory side spacer 53 ... second non-volatile memory side contact 54 ... second non-volatile memory side control gate silicide 55 ... second non-volatile memory side drain diffusion layer silicide 56 ... first sidewall 57 ... second sidewall 58 ... third sidewall 59 ... fourth sidewall 61 ... first oxide film 62 ... first polysilicon film 63 ... first nitride film 64 ... opening 65 ... tilted portion 66 ... second oxide film 67 ... third oxide film 68 ... 2nd nitride film 69 ... 4th oxide film 70 ... 2nd polysilicon film L1 ... 1st length L2 ... 2nd length 101 ... Plit gate type nonvolatile memory cell 102 ... Substrate 103 ... First source / drain diffusion layer 104 ... Second source / drain diffusion layer 105 ... Floating gate 106 ... Control gate 107 ... Gate oxide film 108 ... Tunnel oxide film 109 ... Source plug 111 ... spacer W1 ... spacer exposure width H1 ... spacer film thickness

Claims (20)

A first insulating film formed on the semiconductor substrate;
A first conductor film formed on the first insulating film;
Second and third conductor films formed on opposite ends of the first conductor film, respectively,
First and second diffusion layers formed in the semiconductor substrate at positions corresponding to side surfaces of the second and third conductor films;
An evaluation element for a nonvolatile memory cell, comprising: a measurement electrode contact that connects a pad to which a voltage can be applied and the first conductive film. The evaluation element for a nonvolatile memory cell according to claim 1, further comprising:
A first spacer insulating film configured on the first conductor film;
A second spacer insulating film configured on the first conductive film,
The measurement electrode contact is
An evaluation element for a non-volatile memory cell configured between the first spacer insulating film and the second spacer insulating film. The evaluation element for a nonvolatile memory cell according to claim 2,
The second conductive film is
Formed on the side surfaces of the first conductor film and the first spacer insulating film via the first tunnel insulating film;
The third conductor film is
An evaluation element for a non-volatile memory cell formed on a side surface of the first conductor film and the second spacer insulating film via a second tunnel insulating film. The evaluation element for a nonvolatile memory cell according to any one of claims 1 to 3,
The first conductor film is
Acts as a measurement gate electrode,
The gate length of the first conductive film is
An evaluation element for a nonvolatile memory cell, which is equivalent to the effective gate length of the floating gate of the nonvolatile memory cell to be evaluated. A pair of non-volatile memory cells having a common source or drain as a first diffusion layer formed in a semiconductor substrate at a position corresponding to the separated region; An evaluation element for a non-volatile memory cell formed corresponding to the non-volatile memory cell of
The evaluation element is
Having a measurement gate electrode formed without separating the conductive film for the floating gate;
The measurement gate electrode is
A semiconductor chip connected to a pad to which a voltage can be applied. The semiconductor chip according to claim 5,
The evaluation element is
First and second conductor films formed on opposite ends of the measurement gate electrode, respectively,
First and second diffusion layers formed in the semiconductor substrate at positions corresponding to side surfaces of the first and second conductor films;
A semiconductor chip comprising: a measuring electrode contact connecting the pad and the measuring gate electrode. The semiconductor chip according to claim 5 or 6,
The gate length of the measurement gate electrode is
A semiconductor chip that is equivalent to an effective gate length of a floating gate of the nonvolatile memory cell. A semiconductor chip comprising: a pair of nonvolatile memory cells having a first diffusion layer as a common source or drain; and an evaluation element for the nonvolatile memory cell formed corresponding to the pair of nonvolatile memory cells There,
The evaluation element is
A first conductor film formed on a semiconductor substrate;
Second and third conductor films formed at opposite ends of the first conductor film, respectively,
First and second diffusion layers formed in the semiconductor substrate at positions corresponding to side surfaces of the second and third conductor films;
A semiconductor chip comprising a measurement electrode contact connecting a pad to which a voltage can be applied and the first conductor film. The semiconductor chip according to claim 8, wherein
The evaluation element further includes:
A first spacer insulating film configured on the first conductor film;
A second spacer insulating film configured on the first conductor film,
The measurement electrode contact is
A semiconductor chip configured between the first spacer insulating film and the second spacer insulating film. The semiconductor chip according to claim 9,
The second conductive film is
Formed on the side surfaces of the first conductor film and the first spacer insulating film via the first tunnel insulating film;
The third conductor film is
A semiconductor chip formed on a side surface of the first conductor film and the second spacer insulating film via a second tunnel insulating film. The semiconductor chip according to any one of claims 8 to 10,
The first conductor film is
Acts as a measurement gate electrode,
The gate length of the first conductive film is
A semiconductor chip that is equivalent to an effective gate length of a floating gate of the nonvolatile memory cell. The semiconductor chip according to claim 11,
The floating gate of the nonvolatile memory cell is configured by separating the first conductive film,
The nonvolatile memory cell is
A semiconductor chip comprising a diffusion layer acting as a common source or drain in a semiconductor substrate at a position corresponding to the separated region. A wafer including a plurality of semiconductor chips divided by a scribe line,
The wafer is
A pair of nonvolatile memory cells and an evaluation element;
The evaluation element is
A first insulating film formed on the semiconductor substrate;
A first conductor film formed on the first insulating film;
Second and third conductor films formed on opposite ends of the first conductor film, respectively,
First and second diffusion layers formed in the semiconductor substrate at positions corresponding to side surfaces of the second and third conductor films;
A wafer comprising: a measuring electrode contact connecting a pad to which a voltage can be applied and the first conductor film. The wafer according to claim 13,
The evaluation element is
A wafer placed in a region where scribe lines are formed in the scribe process. Forming a first conductor film on a semiconductor substrate via a first insulating film;
Forming a measurement gate electrode by selectively removing the first conductor film using a second insulating film formed on the first conductor film as a mask;
Forming second and third conductor films on both ends of the measurement gate electrode so as to face each other;
Forming a contact for connecting to a pad to which a voltage can be applied to the measurement gate electrode. A method for producing an evaluation element for a nonvolatile memory. In the manufacturing method of the evaluation element for nonvolatile memory according to claim 15,
The second insulating film is
A spacer insulating film having an opening, and an oxide film formed on the spacer insulating film and the opening,
The step of forming the measurement gate electrode includes:
Etching the first conductor film using the oxide film as a mask;
Removing the oxide film after etching the first conductor film,
The step of forming the second and third conductor films includes
Forming a tunnel insulating film;
Etching back a polysilicon film formed on the tunnel insulating film,
The step of forming the contact includes
Removing the tunnel insulating film formed on the opening to expose the surface of the first conductor film;
Forming a contact connected to the surface of the first conductor film. A method of manufacturing an evaluation element for a nonvolatile memory. A method of manufacturing a semiconductor chip having a nonvolatile memory cell formed in a first region and an evaluation element formed in a second region,
(A) forming a first conductive film for a floating gate on a semiconductor substrate via a first insulating film;
(B) forming a second insulating film having an opening on the first conductive film formed in the first region, and forming the first insulating film in the second region; Forming a third insulating film on the conductor film;
(C) When the third insulating film is formed on the first conductor film in the second region, the second insulating film in the first region is used as a mask. Separating the first conductor film formed in the first region;
(D) forming a plug whose upper portion is covered with a fourth insulating film at a position corresponding to the separated region in the first region;
(E) A floating gate is formed by selectively removing the first conductor film in the first region using the fourth insulating film as a mask, and using the third insulating film as a mask. Selectively removing the first conductor film in the second region to form a measurement gate electrode;
(F) forming a contact for connecting to the measurement gate electrode to a pad to which a voltage can be applied, and a method for manufacturing a semiconductor chip. In the manufacturing method of the semiconductor chip according to claim 17,
The third insulating film is
A fifth insulating film having an opening;
A method for manufacturing a semiconductor chip, comprising: a sixth insulating film formed in the opening of the fifth insulating film. The method of manufacturing a semiconductor chip according to claim 18,
The step (b)
Forming the sixth insulating film on the second insulating film and the fifth insulating film;
Forming a resist layer on the sixth insulating film in the second region and then removing the sixth insulating film in the first region;
After peeling off the resist layer, all the sixth insulating film in the first region is removed, and the sixth insulating film is left in the opening of the fifth insulating film in the second region. Process,
The step (c)
Separating the first conductor film in the first region when the sixth insulating film is left in the opening of the fifth insulating film in the second region; A method for manufacturing a semiconductor chip. In the manufacturing method of the semiconductor chip according to claim 19,
The step (e)
The first conductive film in the first region is exposed using the fourth insulating film as a mask, and the first conductive film in the second region is exposed using the third insulating film as a mask. The manufacturing method of a semiconductor chip including the process of exposing a body film.

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