KR100824157B1 - Method for forming test pattern in flash memory device - Google Patents

Abstract

A method for forming test pattern in a flash memory device is provided to test transistor characteristics by transferring a gate bias to a floating gate directly, by forming a conductive film for a control gate after removing a capping film and a dielectric film formed on a test pattern region sequentially. A tunnel insulation film(304) and a conductive film(306) for a control gate are formed on a semiconductor substrate(302) in sequence. The semiconductor substrate is defined as a main memory cell region and a test pattern region. A trench is formed by etching the conductive film for a floating gate, the tunnel insulation film formed on an isolation region of the main memory cell region and the test pattern region, and the semiconductor substrate. An isolation film(308) is formed by burying an insulation film in the trench. A dielectric film is formed on the whole structure including the isolation film. A capping film is formed on the whole structure including the dielectric film. The dielectric film is exposed by removing a part of the capping film formed on a selection transistor region of the main memory cell region and the capping film formed on the test pattern region is removed at the same time. The conductive film for a floating gate is exposed by removing the exposed dielectric film. A conductive film(314) for a control gate and a metal conductive layer are stacked sequentially on the whole structure including the exposed conductive film for a floating gate.

Description

Method for forming Test Pattern in Flash memory Device}

1 is a cross-sectional view of a device for describing a flash memory device according to the prior art.

2A is a layout view of a main cell formation region of a flash memory device according to an exemplary embodiment.

2B is a layout view of a test pattern formation region of a flash memory device according to an exemplary embodiment.

3A is a cross-sectional view taken along the line AA ′ of FIG. 2A.

FIG. 3B is a cross-sectional view taken along the line BB ′ of FIG. 2B.

<Description of the symbols for the main parts of the drawings>

302 semiconductor substrate 304 tunnel oxide film

306: conductive film for floating gate 308: device isolation film

310: dielectric film 312: capping film

314: conductive film for the control gate

The present invention relates to a test pattern forming method of a flash memory device, and more particularly, to a test pattern forming method of a flash memory device having a SAFG structure.

In general, semiconductor memory devices are classified into volatile memory and non-volatile memory.

Volatile memory is occupied by RAM, such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and data can be input and stored when power is applied, but data is volatilized when power is removed. It is impossible to preserve. In DRAM, a transistor functions as a switch and a capacitor functions as a data storage function. When the power supply is cut off, internal data is automatically destroyed. In addition, the SRAM has a flip-flop type transistor structure and stores data according to the driving degree difference between the transistors. Also, when the power supply is cut off, the internal data is automatically destroyed.

On the contrary, non-volatile memory, which does not lose stored information even when power supply is interrupted, has been developed and developed for the purpose of programming and supplying data or an operating system related to the operation of a system. Non-volatile memory is being used by commercially available EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable and Programmable Read Only Memory), and flash memory. In particular, NAND-type flash memory has been in the spotlight with the explosive growth in mobile communication devices, MP3, and digital cameras.

Flash memory cells generally have a structure including a tunnel dielectric layer, a floating gate, an interlayer dielectric layer, and a control gate formed on a silicon substrate. Data storage of flash memory cells having such a structure is achieved by applying an appropriate voltage to the control gate and the substrate to insert or withdraw electrons into the floating gate.

Such a flash memory device can be used to separate devices already formed on the substrate, as the design rule is lowered below 70 nm, resulting in smaller actual accuracy than the overlay accuracy limit of lithography equipment. Self alignment floating gate (SAFG) structure, which forms a floating gate on a trench in a self-aligned manner, has to be adopted.

The self-aligning floating gate (SAFG) structure forms a trench in a semiconductor substrate on which a tunnel oxide layer and a polysilicon layer are formed, forms a device isolation layer by filling a trench, wet-etches the upper portion of the device isolation layer, and then dielectric and capping poly A film and a control gate layer are formed by depositing sequentially.

1 is a cross-sectional view of a device for describing a flash memory device according to the prior art.

Referring to FIG. 1, in a flash memory device having a self-aligning floating gate (SAFG) structure, a tunnel oxide film 102 and a polysilicon film 104 are formed on a semiconductor substrate 100, and a polysilicon film in a device isolation region is formed. The trench 104 and the tunnel oxide film 102 are sequentially etched to form trenches, the trench is buried to form an isolation layer 106, and an upper portion of the isolation layer 106 is wet-etched, followed by the dielectric layer 108. And the capping poly film 110 and the control gate layer 112 are sequentially deposited.

In general, the method of confirming at the wafer level whether the process has been performed correctly after the completion of the semiconductor manufacturing process has been conducted at the device side and the product side. In the device side, the space between the semiconductor product and the product, In the scribe line, a number of test patterns were added to check the general properties of the device, and the DC items and values were measured.

As described above, the test pattern is intended to monitor the characteristics of the actual device by performing various electrical measurements by a so-called TEG (Test Element Group), which is completed by the whole process or partial process of the device. Such a test pattern is simultaneously formed in the form of a transistor in a scribe line region, which is a free region that is removed during chip separation between individual chips when cells are formed in the memory cell region.

In the flash memory device, since the gate bias applied to the control gate layer 112 during the transistor characteristic test operation of the device is reduced by the coupling ratio by the dielectric film 108, the flash memory device is transferred to the floating silicon polysilicon film 104. There is a difficulty in verifying the characteristics of the transistors, and the transistor characteristics of the polysilicon film 104 for floating gates are tested in the test pattern for the characteristics analysis.

However, in a flash memory device having a self-aligning floating gate (SAFG) structure, the floating gate polysilicon film 104 formed on the active region is electrically separated in the device isolation region between the cell and the floating cell of the selected cell. There is a problem of failing to transfer the bias directly to the gate.

SUMMARY OF THE INVENTION An object of the present invention is to form a floating gate using a method of forming a self-aligned floating gate of a flash memory device, and to form a dielectric film and a capping film, and then a part of the capping film formed on the selected transistor region of the main memory cell region. By simultaneously removing the capping film and the dielectric film formed on the test pattern region and forming the conductive film for the control gate, a test pattern of a flash memory device capable of directly testing a transistor characteristic by transferring a gate bias directly to the floating gate. It is to provide a formation method.

According to one or more exemplary embodiments, a method of forming a test pattern of a flash memory device includes sequentially forming a tunnel insulating film and a conductive film for a floating gate on a semiconductor substrate defined by a main memory cell region and a test pattern region, and a device isolation region. Forming a trench by etching the floating gate conductive film, the tunnel insulating film, and the semiconductor substrate formed at a predetermined depth, forming a device isolation film by embedding an insulating film in the trench, and including the device isolation film. Forming a dielectric film over the entire structure, forming a capping film over the entire structure including the dielectric film, and removing a portion of the capping film formed on the selected transistor region of the main memory cell region to expose the dielectric film. At the same time formed on the test pattern area Removing the capping layer, removing the exposed dielectric layer to expose the floating gate conductive layer, and exposing the control gate conductive layer and the metal conductive layer on the entire structure. Laminating sequentially.

Removing the capping layer on the test pattern region removes the capping layer on the region where the select transistor and the plurality of word lines are formed. The removing of the capping layer on the test pattern region is formed at an intermediate position between the select transistor and the word line and drain select transistor and the source select transistor closest to the select transistor.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

2A and 2B are layout views of a main cell formation region and a test pattern region of a flash memory device according to example embodiments.

Referring to FIG. 2A, an isolation process is performed on a semiconductor substrate to divide the active region 200 and the isolation region 202. In addition, layers constituting a plurality of word lines WL are stacked in a direction perpendicular to the device isolation region 202. In this case, the stacked films are a tunnel oxide film, a floating gate conductive film, a dielectric film, and a capping film. Subsequently, an etching process using an ONC mask is performed to electrically connect the control gate conductive layer and the floating gate conductive layer that are formed next to the selection transistor regions DSL and SSL. As a result, the capping film and the dielectric film formed on the partial region of the selection transistor regions DSL and SSL are removed.

Referring to FIG. 2B, a mask for removing a capping layer and a dielectric layer formed on a portion of the selection transistor regions DSL and SSL regions illustrated in FIG. 2A is enlarged to the entire test pattern region. The capping film and the dielectric film are removed on the substrate. The above-described process proceeds simultaneously with the operation of removing the capping film and the dielectric film formed on the partial region of the selection transistor regions DSL and SSL of the main cell region. In the flash memory device, since the transistor characteristics of the top line WL0, the bottom line WLn, and the middle line of the word line WL are the most important, the flash memory device is similar to the first mask ONC Mask1 or the second mask ONC Mask2. The capping film and the dielectric film formed on the line may be selectively removed by selecting a predetermined line.

3A is a cross-sectional view taken along the line AA ′ of FIG. 2A.

FIG. 3B is a cross-sectional view taken along the line BB ′ of FIG. 2B.

An embodiment of the present invention will be described in more detail with reference to FIGS. 3A and 3B as follows.

3A and 3B, a tunnel oxide film 304 and a floating gate conductive film 306 are sequentially formed on the semiconductor substrate 302. The floating gate conductive film 306 is preferably formed of a polysilicon film.

Thereafter, the conductive gate 306 for floating gate, the tunnel oxide film 304 and the semiconductor substrate 302 formed in the device isolation region are etched to a predetermined depth to form a trench. An isolation layer 308 is formed by filling an insulating layer in the trench. Thereafter, the dielectric film 310 is formed over the entire structure including the device isolation film 308. The dielectric film 310 is preferably formed of an ONO oxide film having a structure in which a first oxide film, a nitride film, and a second oxide film are sequentially stacked. The capping film 312 is formed on the entire structure including the dielectric film 310. The capping film 312 is preferably formed of a polysilicon film.

Thereafter, a portion of the capping layer 312 formed on the selection transistor region of the main memory cell region using the mask is removed to expose a portion of the dielectric layer 310, and then the exposed dielectric layer 310 is removed. In this case, as shown in FIG. 3B, the capping layer 312 formed on the test pattern region is removed and the dielectric layer 310 formed on the test pattern region is removed.

The control gate conductive film 314 is formed on the entire structure including the exposed floating gate conductive film 306.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to an embodiment of the present invention, after forming a floating gate using a method of forming a self-aligned floating gate of a flash memory device, and forming a dielectric film and a capping film, a part of a capping film formed on a selected transistor region of a main memory cell region is formed. By simultaneously removing the capping film and the dielectric film formed on the test pattern region and forming the conductive film for the control gate, the gate bias can be directly transmitted to the floating gate to test transistor characteristics.

Claims (3)

Sequentially forming a tunnel insulating film and a floating gate conductive film on a semiconductor substrate defined by a main memory cell region and a test pattern region; Forming a trench by etching the floating gate conductive layer, the tunnel insulating layer, and the semiconductor substrate formed in the device isolation region between the main memory cell region and the test pattern region; Forming an isolation layer by filling an insulating layer in the trench; Forming a dielectric film on the entire structure including the device isolation film; Forming a capping film on the entire structure including the dielectric film; Removing a portion of the capping layer formed on the selection transistor region of the main memory cell region to expose the dielectric layer and simultaneously removing the capping layer formed on the test pattern region; Removing the exposed dielectric film to expose the floating gate conductive film; And And sequentially depositing a control gate conductive film and a metal conductive layer on the entire structure including the exposed floating gate conductive film. The method of claim 1, The removing of the capping layer on the test pattern region may include removing the capping layer on a region where a select transistor and a plurality of word lines are formed. The method of claim 1, The removing of the capping layer on the test pattern region may include a word line formed at an intermediate position between a drain select transistor and a source select transistor among a select transistor, a word line closest to the select transistor, and a plurality of word lines. Test pattern formation method.

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