JPH03250748A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable the film quality of an insulating film to be monitored by a method wherein an element for evaluating the quality of the insulating film is provided to measure the characteristics of the same. CONSTITUTION:An element T for evaluating the quality of an insulating film 5 is provided. At this time, it is recommended that the structure of the element T shall be similar to that of the element formed of the first electrode FG (floating gate), the insulating film 5 and the second electrode CG(control gate). Through these procedures, since said element T for evaluating the film quality is provided, the film quality of the insulating film 5 can be monitored by measuring the characteristics of the insulating film 5 using said element for evaluating the film quality.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, and is suitable for application to, for example, a semiconductor device having a floating gate type element.

1. Summary of the Invention The present invention provides a semiconductor device having a structure in which a second electrode is laminated on a first electrode with an insulating film interposed therebetween. This allows the quality of the insulating film to be monitored.

[Conventional technology]

EPROM (Erasabl
, e and Programmable Read
0nly Mem.

ry) and EEPROM (Electrical
ly Erasable and Programma
bl, e Read ONLY Memory). Here, the floating gate is usually formed by a first layer of polycrystalline silicon (Si) film doped with impurities, and the control gate is formed by a second layer of polycrystalline silicon (Si) film doped with impurities. .

In such a floating gate type memory transistor, the quality of the insulating film between the floating gate and the control gate is extremely important for the following reasons. That is, firstly, the quality of the insulating film determines the charge retention characteristic, which indicates how difficult it is for the charges accumulated in the floating gate to escape to the control gate.

Secondly, since a high voltage is applied to the control gate during programming, this insulating film has sufficient withstand voltage and excellent TDD B (time dependent).
This is because it is necessary to have the nt dielectric breakdown characteristic.

In addition, Japanese Patent Application Laid-open No. 63-67786 describes the EFROM
The lower and upper layers of the floating gate are formed by a polycrystalline Si film doped with impurities and a polycrystalline Si film not doped with impurities, respectively. A method of manufacturing a semiconductor device has been proposed in which the quality of the insulating film is improved by forming an insulating film.

[Problems to be Solved by the Invention] However, although the quality of the insulating film between the floating gate and the control gate is important as described above, in conventional EPROMs and EEPROMs,
The quality of this insulating film was not monitored, and therefore the quality of this insulating film was not controlled.

Therefore, an object of the present invention is to provide a semiconductor device in which the quality of an insulating film can be monitored.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a first electrode (F
C) A semiconductor device having an element having a structure in which a second electrode (CC) is laminated thereon via an insulating film (5), including an element (T) for evaluating the film quality of the insulating film (5).

Here, the structure of the element (T) for evaluating the film quality of the insulating film (5) preferably includes a first electrode (FG), an insulating film (5), and a second electrode (FG).
The structure is similar to that of the element formed by the electric current i (CG).

[Effect]

According to the semiconductor device of the present invention configured as described above,
Since it has an element (T) for evaluating the film quality of the insulating film (5), this element (T) for evaluating the film quality can be used to evaluate the insulating film (5).
By measuring the characteristics of the insulating film (5), the quality of the insulating film (5) can be monitored.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This embodiment is an embodiment in which the present invention is applied to an EFROM. In addition, in all the drawings of the embodiment, the same parts are given the same reference numerals.

As shown in FIG. 1, in the EPROM according to this embodiment, a field insulating film 2 such as silicon dioxide (SiOz) M is selectively formed on the surface of a p-type silicon (Si) substrate J. Isolation between elements is performed by Reference numeral 3 indicates a P'' type channel stop region, for example.

Furthermore, on the surface of the active region surrounded by the field insulating film 2, a gate insulating film 4 such as a 5iOz film is formed.

FG indicates a floating gate. This floating gate FC is formed of a polycrystalline Si film doped with an impurity such as phosphorus (P), for example. Reference numeral 5 indicates an insulating film (coupling insulating film). This insulating film 5 is
5in2 film, SiO□ film/silicon nitride (5i3Na
) film/SiO□ film ○N○ (oxide-ni
tride-oxide) film, 5i3Na film/S
i N O (nitride-oxide) consisting of O2 film
e) Formed by a film or the like. A control gate CG is stacked on the floating gate FC via this insulating film 5. This control gate CG is formed of a polycrystalline Si film doped with an impurity such as P, for example. The control gate CG can also be formed of a polycide film in which a high melting point metal silicide film such as a tungsten silicide (WSiz) film is superimposed on a polycrystalline Si film doped with impurities. In addition, for example, Si
An insulating film 6 such as an O□ film is formed. On the other hand, in the P-type Si substrate 1, for example, an n-type source region 7 and drain region 8 are formed in self-alignment with the control gate CG and floating gate FC. A memory transistor is formed by the control gate CG, floating gate FG, source region 7, and drain region 8.

G indicates a gate electrode. This gate electrode G is, for example, P
It is formed from a polycrystalline Si film doped with impurities such as. Note that this gate electrode G can also be formed of a polycide film in which a high melting point metal silicide film such as a W S i z film is superimposed on a polycrystalline Si film doped with impurities. On the other hand, in the p-type S1 substrate 1, for example, an n-type source region 9 and drain region 10 are formed in self-alignment with respect to the gate electrode G. The gate electrode G, source region 9, and drain region 10 form an n-channel MOS transistor for a peripheral circuit.

In this embodiment, in addition to the above-mentioned memory transistor and n-channel MOS transistor for peripheral circuits,
An element T for evaluating the film quality of the insulating film 5 of the memory transistor is formed. This film quality evaluation element T is a polycrystalline S constituting a floating gate FG of a memory transistor.
It is formed of a polycrystalline Si film 11 similar to the i film, an insulating film 5, and a polycrystalline Si film 12 similar to the polycrystalline Si film constituting the control gate CG of the memory transistor.

Reference numeral 13 indicates an interlayer insulating film such as a phosphosilicate glass (PSG) film. Further, C1 to C6 indicate contact holes. And contact holes C,,C2
Electrodes 14 and 15 contact the source region 7 and drain region 8 of the memory transistor through the capacitor, respectively. Furthermore, electrodes 16 and 17 are in contact with the source region 9 and drain region 10 of the n-channel MOS transistor for the peripheral circuit, respectively, through contact holes C3 and C4. Furthermore, electrodes 18 and 19 are in contact with the polycrystalline Si films 11 and 12 of the film quality evaluation element T through contact holes C6 and C6, respectively. These electrodes 14 to 19 are made of aluminum (AI), for example.

Next, the EPR according to this embodiment configured as described above
A method for manufacturing OM will be explained.

As shown in FIG. 2A, first, the surface of the p-type S1 substrate 1 is selectively thermally oxidized to form a field insulating film 2 to provide isolation between elements. During this thermal oxidation, a P-type impurity such as boron (B), which has been selectively ion-implanted into the p-type Si substrate 1 in advance, diffuses and forms a chaff on the underside of the field insulating film 2. Rustomb region 3 is formed. Next, a gate insulating film 4 is formed on the surface of the active region surrounded by this field insulating film 2 by thermal oxidation. Next, a first layer of polycrystalline Si film 11 is formed on the entire surface by CVD method, and this polycrystalline film is doped with an impurity such as P to lower the resistance.
The i-film 11 is patterned into a predetermined shape by etching. In this case, the polycrystalline Si film 11 patterned in this manner exists only in the memory transistor formation area and the film quality evaluation element formation area.

Next, as shown in FIG. 2B, an insulating film M5 such as an S:Oz film is formed on the patterned polycrystalline Si film 11 by thermal oxidation. Note that when using an ONO film as this insulating film 5, for example, the polycrystalline Si film 11
A Si0g film is formed on top by a thermal oxidation method, and this 5iOz
After forming a Si3N4 film on the film by CVD method, a 510z film is formed on this Si3N film by thermal oxidation method.

A film can be formed. Next, a second layer of polycrystalline Si film 12 is formed on the entire surface by CVD, and then this polycrystalline Si film 12 is doped with an impurity such as P to lower its resistance. Thereafter, a first layer resist pattern 20 having a predetermined shape is formed on the polycrystalline Si film 2 by lithography.

Next, using this resist pattern 20 as a mask, the polycrystalline Si film 12 is etched by, for example, reactive ion etching (RIE).
By anisotropic etching in the direction perpendicular to the substrate surface,
As shown in FIG. 2C, the control gate CG of the memory transistor and the gate electrode G of the n-channel MO3) transistor for the peripheral circuit are formed, and a polycrystalline Si film 12 of a predetermined shape of the element T for film quality evaluation is formed. do.

Next, as shown in the second diagram, a second layer of a predetermined shape is formed by lithography on the surface of the n-channel MOS transistor formation area for the peripheral circuit and a part of the surface of the element formation area for film quality evaluation. After covering with two resist patterns,
For example, using the resist patterns 20 and 21 as a mask,
The insulating film 5 is anisotropically etched in a direction perpendicular to the substrate surface using the IE method.

Next, using the resist patterns 20 and 21 as a mask, the first layer polycrystalline Si film 11 is anisotropically etched in a direction perpendicular to the substrate surface by, for example, RIE. by this,
As shown in the 22nd picture, a floating gate FG is formed in the memory transistor formation area in a self-aligned manner with respect to the control gate CG, and a polycrystalline Si film 11 having a predetermined shape is formed in the film quality evaluation element formation area. Ru.

Next, after removing the resist patterns 20 and 21, the second
As shown in FIG. F, the portions of the gate insulating film 4 other than the polycrystalline Si film 11 in the floating gate FC, gate electrode G, and film quality evaluation element formation area are removed by etching.

Next, by performing thermal oxidation, as shown in FIG. , an insulating film 6 is formed on the surfaces of the gate electrode G and the polycrystalline Si films 11 and 12. Next, using the control gate CG, floating gate FC, and gate electrode G as a mask, p
An n-type impurity such as arsenic (As) is ion-implanted into the Si-based Fi.1. As a result, for example, an n-type source region 7 and a drain region 8 are formed in a self-aligned manner with respect to the control gate CG and floating gate 1-FC, and, for example, an n-type source region 9
A drain region 10 is formed in a self-aligned manner with respect to the gate electrode G. Thereafter, a glabellar insulating film I3 is formed on the entire surface by, for example, a CVD method.

Next, as shown in FIG. 1, predetermined portions of the interlayer insulating film 13, gate insulating film 4, and insulating film 60 are removed by etching to form contact holes C1 to C6. Next, after forming an A1 film over the entire surface by, for example, sputtering, this AI film is patterned into a predetermined shape by etching to form electrodes 14 to 19, thereby completing the intended EPROM.

As described above, since the EPROM according to this embodiment has the element T for evaluating the film quality of the insulating film 5, the film quality of the insulating film 5 can be monitored on-chip using the element T for evaluating the film quality. , thereby the floating gate FG and control gate CG of the memory transistor
The film quality of the insulating film 5 between the two can be evaluated. In this case, the film quality of the insulating film 5 using this film quality evaluation element T can be evaluated by, for example, applying a predetermined voltage between the electrodes 18 and 19 of this film quality evaluation element T and measuring the leakage current at that time. A constant current (tunnel current) is passed between these electrodes 18 and 19 to measure the time until dielectric breakdown occurs (constant current TDDB), or a constant voltage is passed between these electrodes 18 and 19. This can be done by applying constant current TDDB and measuring the time until dielectric breakdown of the insulating film 5 occurs (constant current TDDB). Furthermore, the film quality of the insulating film 5 may be evaluated by measuring the capacitance-voltage (C-V) characteristics of this film quality evaluation element T.

Note that when actually evaluating the film quality of the insulating film 5, the film quality is evaluated by, for example, statistically processing a large number of measurement data using Weibull Pronto or the like.

Since the film quality of the insulating film 5 between the floating gate FG and the control gate CG can be evaluated as described above, the film quality of the insulating film 5 can be managed. By feeding the evaluation results of the film quality of the insulating film 5 to the process for forming the insulating film 5, a high-quality insulating film 5 with excellent charge retention characteristics, TDDB characteristics, and breakdown voltage can be formed. You will be able to do this. This makes it possible to realize an EPROM with high reliability.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in the above embodiment, the element T for evaluating the film quality of the insulating film 5 is formed on the active region, but the element T for evaluating the film quality can also be formed, for example, on the field insulating film 2. . Furthermore, the shape of this film quality evaluation element T can be different from that of the above embodiment.

In general, the larger the area of the insulating film 5 of the film quality evaluation element T, the higher the probability of failure of this insulating film 5. By evaluating the film quality of the insulating film 5 for each of the plurality of film quality evaluation elements T, the causes of defects in the insulating film 5 (for example, initial defects and other defects in the insulating film 5 itself, It is possible to separate defects (such as defects caused by dust adhering to the insulating film 5).

Furthermore, as a method of manufacturing the EPROM according to the above embodiment, it is also possible to use a manufacturing method different from that described in the above embodiment. Furthermore, in the above-described embodiments, the case where the present invention is applied to an EPROM has been described, but the present invention can also be applied to, for example, an EEPROM.

As shown in FIG. 3, a chip 53 dedicated to evaluating the film quality of the insulating film is prepared separately from the chip 52 actually used on the semiconductor wafer 51, and the above-mentioned film quality evaluation element T is attached to this thousand knob 53. It may also be formed. Furthermore, as shown in FIG. 4, a film quality evaluation element T may be formed on the scribe line 54.

(Effects of the Invention) As described above, since the present invention includes an element for evaluating the film quality of an insulating film, the characteristics of the insulating film can be measured using this element for evaluating the film quality. The film quality can be monitored.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an EPROM according to an embodiment of the present invention, FIGS. 2A to 2G are cross-sectional views for explaining the manufacturing method of the EPROM shown in FIG. 1 in the order of steps, and FIG. A plan view showing another example in which an element for evaluating the film quality of an insulating film is formed on a chip dedicated to film quality evaluation, and FIG. 4 is an enlarged view of the main part showing still another example in which an element for evaluating the film quality of an insulating film is formed on a scribe line. FIG. Explanation of main symbols in the drawings: Lap type Si substrate, 2: Field insulating film, 4: Gate insulating film, 5: Insulating film, 79: Source region,
8.10+ drain region, 11°12: polycrystalline S
1 film, FG: floating gate, CG: control gate, T: element for film quality evaluation.

Claims (1)

[Claims] A semiconductor device having an element having a structure in which a second electrode is laminated on a first electrode with an insulating film interposed therebetween, the semiconductor device comprising an element for evaluating the quality of the insulating film.