JP3229991B2 - PSK modulator - Google Patents
PSK modulatorInfo
- Publication number
- JP3229991B2 JP3229991B2 JP03740592A JP3740592A JP3229991B2 JP 3229991 B2 JP3229991 B2 JP 3229991B2 JP 03740592 A JP03740592 A JP 03740592A JP 3740592 A JP3740592 A JP 3740592A JP 3229991 B2 JP3229991 B2 JP 3229991B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- carrier
- output
- digital filter
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明はＰＳＫ変調装置に関し、
特に誤りを有するデータで変調されたキャリアの出力を
防止できるＰＳＫ変調装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PSK modulator.
In particular, the present invention relates to a PSK modulator that can prevent the output of a carrier modulated with erroneous data.
【０００２】[0002]
【従来の技術】従来のディジタルフィルタを用いた４相
ＰＳＫ変調装置を図３に示し、このディジタルフィルタ
２４を図４に示す。まず、図３において、Ｐチャンネル
入力信号１Ａ，およびＱチャンネル入力信号１Ｂとクロ
ック信号２とはＰチャンネル用ディジタルフィルタ２４
Ａ、およびＱチャンネル用ディジタルフィルタ２４Ｂに
供給され、その出力が、乗算器２０Ａおよび２０Ｂに入
力される。乗算器２０Ａ，２０Ｂに達した信号はキャリ
ア発振器１６から得られるキャリア周波数信号１７と、
９０°移相器１８により９０°移相偏移されたキャリア
周波数１９とそれぞれ掛け合わされ、この２つの信号を
加算器２１で加算することにより４相ＰＳＫ信号２３が
得られる。次にディジタルフィルタ２４Ａ，２４Ｂ内は
同じ構成で図４に示すように、入力信号１および補助入
力信号６が、シリアル／パラレル変換器３にてパラレル
信号５に変換され、メモリ７にアドレス信号として入力
してアクセスし、メモリ７内部にあらかじめ設定してお
いたデータ８が出力される。メモリ７より出力されたデ
ータ８は、Ｄ／Ａ変換器１０によりアナログ信号１１に
変換され、ローパスフィルタ（ＬＰＦ）１２により高調
波成分を遮断し、ディジタルフィルタの出力信号１３と
して出力される。2. Description of the Related Art A conventional four-phase PSK modulator using a digital filter is shown in FIG. 3, and this digital filter 24 is shown in FIG. First, in FIG. 3, the P-channel input signal 1A, the Q-channel input signal 1B and the clock signal 2 are connected to the P-channel digital filter 24.
The signals are supplied to the A and Q channel digital filters 24B, and their outputs are inputted to the multipliers 20A and 20B. The signals reaching the multipliers 20A and 20B are a carrier frequency signal 17 obtained from a carrier oscillator 16,
The signals are multiplied by the carrier frequency 19 shifted by 90 ° by the 90 ° phase shifter 18, and the two signals are added by the adder 21 to obtain a four-phase PSK signal 23. Next, the input signal 1 and the auxiliary input signal 6 are converted into a parallel signal 5 by the serial / parallel converter 3 as shown in FIG. Access is made by inputting, and data 8 preset in the memory 7 is output. The data 8 output from the memory 7 is converted into an analog signal 11 by a D / A converter 10, a high-frequency component is cut off by a low-pass filter (LPF) 12, and output as an output signal 13 of a digital filter.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来のディジ
タルフィルタは、送り側の出力信号の誤り判定能力がな
いので、データ誤りが生じた際に、誤ったデータの出力
がそのまま送信されることになるので、復調された出力
波形が歪むという欠点がある。The above-mentioned conventional digital filter does not have the capability of judging the error of the output signal on the transmitting side, so that when a data error occurs, the output of the erroneous data is transmitted as it is. Therefore, there is a disadvantage that the demodulated output waveform is distorted.
【０００４】[0004]
【課題を解決するための手段】本発明のディジタルフィ
ルタは、メモリを用いたディジタルフィルタを有するＰ
ＳＫ変調装置において、そのメモリの出力データとして
通常のディジタルフィルタの出力データの他にパリティ
信号を追加し、これらのメモリ出力データを入力して誤
りを検出して誤りと判定した場合にキャリアオフ信号を
出力する誤り判定器と、このキャリアオフ信号を入力し
てキャリアをオフするキャリアオンオフ制御器とを備え
ている。According to the present invention, there is provided a digital filter having a digital filter using a memory.
In the SK modulator, a parity signal is added to the output data of the memory in addition to the output data of the ordinary digital filter, and when these memory output data are input, an error is detected and a carrier-off signal is determined. And a carrier on / off controller that inputs the carrier off signal to turn off the carrier.
【０００５】[0005]
【実施例】次に、本発明について図面を参照して説明す
る。図１は、本発明の一実施例のディジタルフィルタを
用いた４相ＰＳＫ装置構成図、図２は、図１の実施例の
ディジタルフィルタを示す構成図である。図１の実施例
は本実施例のディジタルフィルタ２５Ａ，２５Ｂから出
力される。キャリアオフ信号１５Ａ，１５Ｂを受けてキ
ャリア信号をオフするゲート２２を備えている。次に本
実施例のディジタルフィルタ２５Ａ，２５Ｂを図２によ
り説明する。図２において、キャリアオフ信号１５を発
生させるために、メモリ７の出力データのパリティ信号
９と、この信号を用いた誤り判定器１４を追加する。パ
リティ信号９のデータはあらかじめメモリ７に格納され
ている。メモリ７からの出力データ８は、ディジタルフ
ィルタ出力信号１３を作るためにＤ／Ａ変換器１０に渡
される信号と、データ誤りを判定しキャリアオフ信号１
５を作るために、データの誤り判定器１４に渡される信
号の２つに分かれる。Ｄ／Ａ変換器１０に渡された信号
はアナログ信号１１に変換され、ローパスフィルタ１２
を経て、ディジタルフィルタ出力信号１３となる。ま
た、誤り判定器１４に渡された信号は、パリティ信号９
を含むすべてのビットでパリティチェックを受け、その
結果誤りがあればキャリアオフ信号１５が発生される。
このキャリアオフ信号１５は、出力制御用のゲート２２
に入力され、キャリア出力のオンオフ制御を行う。Next, the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a four-phase PSK device using a digital filter according to one embodiment of the present invention, and FIG. 2 is a configuration diagram illustrating the digital filter of the embodiment of FIG. 1 is output from the digital filters 25A and 25B of the present embodiment. A gate 22 is provided which receives the carrier-off signals 15A and 15B and turns off the carrier signal. Next, the digital filters 25A and 25B of this embodiment will be described with reference to FIG. 2, in order to generate a carrier-off signal 15, a parity signal 9 of output data of the memory 7 and an error determiner 14 using this signal are added. The data of the parity signal 9 is stored in the memory 7 in advance. The output data 8 from the memory 7 includes a signal passed to a D / A converter 10 for producing a digital filter output signal 13 and a carrier-off signal 1
5 is split into two signals which are passed to the data error determiner 14. The signal passed to the D / A converter 10 is converted into an analog signal 11,
, And becomes a digital filter output signal 13. The signal passed to the error determiner 14 is a parity signal 9
Are subjected to a parity check, and if there is an error, a carrier-off signal 15 is generated.
This carrier-off signal 15 is supplied to an output control gate 22.
To perform on / off control of the carrier output.
【０００６】[0006]
【発明の効果】以上説明したように本発明は、ディジタ
ルフィルタにおけるメモリ出力データのパリティチェッ
クを行い、誤りと判定された場合には、キャリアオフ信
号を送ることにより、メモリデータの誤りによる歪み波
形の出力を未然に防ぐという効果がある。As described above, according to the present invention, a parity check of memory output data in a digital filter is performed, and when an error is determined, a carrier-off signal is sent to generate a distortion waveform due to an error in the memory data. This has the effect of preventing the output of.
【図１】本発明の一実施例の構成図である。FIG. 1 is a configuration diagram of an embodiment of the present invention.
【図２】本実施例のディジタルフィルタの構成図であ
る。FIG. 2 is a configuration diagram of a digital filter of the present embodiment.
【図３】従来のＰＳＫ変調装置の構成図である。FIG. 3 is a configuration diagram of a conventional PSK modulation device.
【図４】従来のディジタルフィルタの構成図である。FIG. 4 is a configuration diagram of a conventional digital filter.
３ シリアルパラレル変換器 ４ 誤り判定器 ７ メモリ １０ Ｄ／Ａ変換器 １２ ローパスフィルタ １６ キャリア発振器 １８ ９０°移相器 ２０Ａ，２０Ｂ 乗算器 ２１ 加算器 ２２ ゲート ２４Ａ，Ｂ、２５Ａ，Ｂ ディジタルフィルタ Reference Signs List 3 serial / parallel converter 4 error judging device 7 memory 10 D / A converter 12 low-pass filter 16 carrier oscillator 18 90 ° phase shifter 20A, 20B multiplier 21 adder 22 gate 24A, B, 25A, B digital filter
Claims (1)
するＰＳＫ変調装置において、そのメモリの出力データ
として通常のディジタルフィルタの出力データの他にパ
リティ信号を追加し、これらのメモリ出力データを入力
して誤りを検出して誤りと判定した場合にキャリアオフ
信号を出力する誤り判定器と、このキャリアオフ信号を
入力してキャリアをオフするキャリアオンオフ制御器と
を備えていることを特徴とするＰＳＫ変調装置。In a PSK modulation apparatus having a digital filter using a memory, a parity signal is added as output data of the memory in addition to output data of a normal digital filter, and these memory output data are input to output an error. A PSK modulation apparatus comprising: an error determiner that outputs a carrier-off signal when detecting an error and detecting a carrier; and a carrier-on-off controller that inputs the carrier-off signal to turn off the carrier. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03740592A JP3229991B2 (en) | 1992-02-25 | 1992-02-25 | PSK modulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03740592A JP3229991B2 (en) | 1992-02-25 | 1992-02-25 | PSK modulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05236038A JPH05236038A (en) | 1993-09-10 |
| JP3229991B2 true JP3229991B2 (en) | 2001-11-19 |
Family
ID=12496621
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03740592A Expired - Fee Related JP3229991B2 (en) | 1992-02-25 | 1992-02-25 | PSK modulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3229991B2 (en) |
-
1992
- 1992-02-25 JP JP03740592A patent/JP3229991B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05236038A (en) | 1993-09-10 |
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