JPS6039960A - Digital modulating circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and to attain circuit integration by controlling the magnitude of a digital frequency waveform in response to the transmission data speed in a modulation circuit used for a constant envelope narrow band communication system. CONSTITUTION:A level setting circuit 4 setting the magnitude of the digital frequency waveform produced in response to a digital transmission data to I/N corresponding to the change in the I/N of the input speed of the digital transmission data is provided. After the digital frequency waveform adjusted for the magnitude is integrated and a phase waveform is produced, a modulation signal is obtained by applying sine/cosine transformation to the result.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital modulation circuit with a simple configuration that can sufficiently cope with different input speeds of digital transmission data.

[Technical background of the invention and its problems]

In communication systems that include nonlinear amplifiers in the transmission system, such as mobile communication and satellite communication systems, a constant envelope narrowband communication method is used in which the envelope of the modulated wave is kept constant and the spectrum is a narrow band. is used. Traditionally, F) TFM (Tamed Freq) is a typical communication method of this type.
Uency Modulation) and GMSK (
Gaussian Fi tered Minimum
5hiftKeying) etc. are known.

FIG. 1 shows a schematic configuration of a digital modulation circuit used in such a communication system, and is generally composed of a dinotal frequency conversion circuit 1, an accumulative addition circuit 2, and a sine/cosine conversion circuit 3. The Dinocle frequency conversion circuit 1 converts input digital transmission data into a digital frequency waveform corresponding to the data under a predetermined operating clock frequency.

The cumulative addition circuit 2 cumulatively adds and integrates the digital frequency waveform in accordance with the predetermined operation clock to generate a dinotal phase waveform corresponding to the data. The sine/cosine conversion circuit 3 performs sine/cosine conversion on the phase of the digital phase waveform to obtain mutually orthogonal analog modulated signals.

By the way, the input speed, that is, the bit rate, of transmission data modulated using such a digital modulation circuit depends on the modulation signal spread9, the encoding quality when digitally encoding an analog signal, and the output data. This is a basic parameter of 971z that determines the coding rate of the 971z correction code. For this reason, depending on the specifications of various systems, the bit L/-1
l: Each is often defined separately. Therefore, it is desired that this type of digital modulation circuit be able to flexibly cope with changes in the bit rate of the transmission data.

In response to such requests, the input speed of the transmitted data is reduced by 1/2.
'N (N: integer), it is considered that all the operating clocks (sampling frequency bit rates) of each of the circuits 1, 2, and 3 are set to 1/H accordingly. When the frequency of the operating clock is changed in this way, the filter characteristics required of the analog low-pass filter (LPF) for removing sampling harmonics used in the sine/cosine conversion circuit 3 change. It has become necessary to prepare a large number of LPFs with different cutoff frequency characteristics depending on the bit rate. Additionally, this has been a major hindrance in integrating this type of digital modulation circuit. For this reason, there was a problem in that it was not possible to adequately cope with variations in the bit rate of transmission data.

[Purpose of the invention]

The present invention has been made in consideration of these circumstances, and its purpose is to provide a simple and efficient method that can sufficiently cope with changes in the input speed of digital transmission data and effectively modulate the transmission data. An object of the present invention is to provide a digital modulation circuit that can be easily integrated into a circuit.

[Summary of the invention]

The present invention includes a level setting circuit that sets the magnitude of a digital frequency waveform generated in accordance with digital transmission data to 1//N in response to a change of 1/H of the input speed of the digital transmission data. , this magnitude-adjusted disortal frequency waveform 'f' is integrated to generate a phase waveform, which is then subjected to sine/cosine transformation to obtain an anomalous signal. That is, the magnitude of the digital frequency waveform is controlled according to the input speed of digital transmission data.
After this, digital modulation processing is performed.

〔Effect of the invention〕

Thus, according to the present invention, since the magnitude of the digital phase waveform is varied in accordance with the input speed of digital transmission data, it is possible to perform modulation without changing the operating clock for digital modulation processing. Therefore,
There is no need to prepare an LPF whose cut-off frequency characteristics vary depending on the input speed of the transmission data. In addition, it becomes possible to sufficiently cope with changes in the input velocity of the digital transmission data without changing the specifications of the circuit. Moreover, the circuit configuration is simple, and the basic configuration of the circuit shown in Figure 1 can be used as is, so it is easy to integrate it into an integrated circuit, so it has extremely practical advantages.
[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a schematic diagram of the structure of the embodiment circuit. The digital frequency waveform changing circuit 1 includes a data register 1a that temporarily stores input digital transmission data, a waveform memo I) 1b that digitally stores a frequency waveform corresponding to the transmission data, and this waveform memo. It is constituted by selective reading fr of the frequency waveform from IJ 1 b and a controlling counter lc. The above frequency waveform is
The waveform corresponding to the 4 data is a signal sequence sampled during a predetermined period.
It is selectively read out at a predetermined sampling rate according to the data completely stored in a.

Therefore, the frequency waveform read from this waveform memo I) lb is changed by 1/N of the manual speed of the digital transmission data via a level setting circuit 4 consisting of, for example, a digital multiplier, a shift register, etc. After its size is adjusted to 1/N in accordance with , it is applied to the cumulative 4λ adder circuit 2. This cumulative recruitment round! As is well known, the i82 is composed of a blade counter 2a and a cumulative register 2b, and operates at the predetermined sampling rate. As a result, the output of the accumulation register 111 is a digital position error waveform, which is the integrated waveform.

The sine/cosine conversion circuit 3 includes a sine/cosine memory 9 a
, a D/A converter 3b, and an LPF 3c. The above sine/cosine memo IJ3a is generated digitally using a sine conversion signal and a cosine conversion circuit corresponding to the phase at each sampling point of the previous 6-phase waveform as modulation signals, and these signals are D. /A
After being converted into an analog signal by the converter 3b, it is outputted via an LPF 3cf for removing sampling harmonics. Thus, here, the envelope of the modulated wave = W is constant,
Modulated signals that are directly fired from each other will be obtained.

Now, in the modulation circuit configured in this way,
When digital transmission data with a period T is input as shown in FIG.
) is output. This waveform is subjected to integration processing to obtain a digital phase waveform as shown in FIG. 3(C), and a modulation waveform corresponding to the phase is obtained.

On the other hand, when the input speed of the digital transmission data changes to 1/2 as shown in FIG. 3(d), the bit rate becomes 2T. In this case, waveform memory 1
The period of the dinotal frequency waveform read from b is also doubled as shown by the broken line in FIG. 3(e). The level setting circuit 4 performs, for example, 1-bit shift processing on such a frequency waveform in order to set its magnitude to 172, and outputs this at the constant sampling frequency. As a result, the size of the distal frequency waveform is reduced to 172, and the time is doubled. By inputting such a frequency waveform, the accumulation register 2b obtains an integral waveform as shown in FIG. 3(f). That is, a signal whose magnitude is doubled in time and whose magnitude is set to 1/2 is repeatedly integrated twice. As a result, regardless of the input speed of the transmission data, the amount of phase rotation for the bit rate remains constant, and it is possible to obtain a modulated signal corresponding to the transmission data.

Also, what should be noted here is the sine/cosine conversion circuit 3.
The point is that the operating speed is constant regardless of the input speed of digital transmission data. This means that the D/A converter 3b operates while keeping its sampling rate constant, and there is no need to change the custom cutoff frequency of the LPF 3c. Therefore, the above configuration According to the modulation circuit, it is possible to cope with digital transmission data having different input speeds without changing its basic configuration or operating characteristics. Therefore, it is easy to make this into a fully integrated circuit, and a great practical effect can be achieved.

Note that the present invention is not limited to the above embodiments. For example, any of the frequency waveform generation method, phase waveform generation method, and sine/cosine conversion method can be used in addition to other well-known methods. Further, these sampling frequencies and the basic bit rate of transmission data can be determined according to specifications. In addition, the level setting circuit itself can generally be configured using not only a bit shift circuit but also a digital multiplier, and the multiplier value is given according to changes in the bit rate of input transmission data. It's good to pass.

In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of a digital modulation circuit, FIG. 2 is a schematic configuration diagram of a digital modulation subcircuit according to an embodiment of the present invention, and FIGS. 3(a) to (f) show how the embodiment circuit operates. It is a signal waveform diagram for explaining the effect. l...Disoccul frequency waveform conversion circuit, 2...cumulative addition circuit, 3...sine/cosine conversion circuit, 4...level setting circuit. Out + Hici agent Patent attorney Takehiko Tsurie Figure 1 Figure 2N Figure 3

Claims (1)

[Claims] means for generating a digital frequency waveform corresponding to digital transmission data; and means for variably setting the magnitude of the digital frequency waveform to 17H when the input speed of the digital transmission data changes to 1/N (N two integers). , comprising means for integrating the digital frequency waveform whose magnitude has been adjusted to generate a digital phase waveform, and means for generating a modulation signal by performing sine/cosine conversion on the phase of the digital phase waveform. Digital modulation circuit.