JPH0787144A - Balanced modulation circuit - Google Patents

Abstract

PURPOSE:To provide a balanced modulation circuit where balance adjustment of differential inputs is automatically performed based on the modulation output. CONSTITUTION:In a balanced modulation circuit 10, the carrier generated by an oscillator 11 and the carrier which has the phase shifted by a pi/2 phase shifter 13 are multiplied by the data of a differential input I and the data of a differential input Q in multipliers 12 and 14, and multiplication results are added in an adder 15 to output a modulated signal. This modulation output is detected by a directional coupler 16 and is fetched into a CPU 19 as the carrier suppression level. The CPU 19 compares the carrier suppression level at a timing other than the burst transmission operation timing of TDMA out of the carrier suppression level with basic carrier suppression level data stored in a ROM 20 based on the TDMA pulse signal, and an adjustment pulse signal is so outputted that the carrier suppression level is maximum, thus adjusting data of the differential input I and data of the differential input Q.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a balanced modulation circuit,
More specifically, the present invention relates to a balanced modulation circuit that automatically adjusts the balance of differential inputs.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 2, a balanced modulation circuit 1 generates a carrier wave by an oscillator 2, divides the carrier wave generated by the oscillator 2, and inputs one to the multiplier 3 as it is. The other of the divided carriers is shifted in phase by the π / 2 phase shifter 4 and input to the multiplier 5.

The differential input (input signals) I signal and Q signal are input to the multiplier 3 and the multiplier 5, respectively, and the multiplier 3 and the multiplier 5 input the differential input I signal and the differential input to the carrier wave. The Q signals are respectively multiplied (modulated) and output to the adder 6.

The adder 6 adds the output of the multiplier 3 and the output of the multiplier 5 and outputs the result.

However, the balanced modulation circuit 1 has a differential input I
The condition for modulation is that the signal and the differential input Q signal are balanced.

Therefore, the conventional balanced modulation circuit 1 is provided with a balance adjustment circuit composed of a variable resistor 7 and a variable resistor 8 on both the input lines of the differential input I signal and the differential input Q signal, and outputs the modulated output. While detecting with another detection circuit, this variable resistor 7
The variable resistor 8 adjusts the balance between the differential input I signal and the differential input Q signal.

[0007]

However, in such a conventional balanced modulation circuit, the balance of differential inputs is manually adjusted by a balance circuit composed of a variable resistor. Since it is necessary to manually perform the delicate differential input balance adjustment work, not only is the adjustment work troublesome, but the balance of the differential input is lost due to temperature changes after the balance adjustment, and proper balanced modulation can be performed. There was a problem that it was difficult.

Therefore, the present invention provides a balanced modulation circuit that automatically adjusts a differential input based on a modulation output, does not require a balance adjustment work of the differential input, and can perform an appropriate balanced modulation. Has an aim.

[0009]

A balanced modulation circuit of the present invention comprises a modulation means for superimposing an input signal on at least two types of carrier waves having different phases, and then synthesizing and modulating the same.
Detecting means for detecting the output level of the modulating means; and balance adjusting means for adjusting the balance of the input signal input to the modulating means based on the detection result of the detecting means when the modulating means has no input signal. The above-mentioned object is achieved by including the.

In this case, for example, as described in claim 2, the modulating means may modulate an input signal input based on a time division multiplexing system.

[0011]

According to the balanced modulation circuit of the present invention, after the input signals are respectively superimposed on at least two types of carrier waves having different phases, the output level of the modulation means for synthesizing and modulating is detected, and the input signals are inputted to this modulation means. Since the balance of the input signal input to the modulation means is adjusted based on the output level detection result when there is no, the differential input can be automatically adjusted based on the modulation output, and the manual differential input It is possible to omit the adjustment work of the balance adjustment of, and to perform appropriate balanced modulation.

[0012]

EXAMPLES Examples will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the balanced modulation circuit of the present invention.

First, the structure will be described.

In FIG. 1, the balanced modulation circuit 10 includes an oscillator 11, a multiplier 12, a π / 2 phase shifter 13, a multiplier 14,
An adder 15, a directional coupler 16, a detection circuit 17, a control circuit 18, etc. are provided, and the control circuit 18 is a CPU (Cent).
ral Processing Unit) 19, ROM (Read Only Memor)
y) 20, a low pass filter (LPF) 21, an A / D conversion circuit 22, D / A conversion circuits 23 and 24, low pass filters 25 and 26, and the like.

The oscillator 11 is composed of a crystal oscillation circuit,
Generate a carrier wave of a predetermined frequency. The oscillator 11 outputs the generated carrier wave to the multiplier 12 and the π / 2 phase shifter 13.

The π / 2 phase shifter 13 shifts the phase of the carrier wave input from the oscillator 11 by π / 2, and the multiplier 14
Output to.

The multiplier 13 and the multiplier 14 further include
The differential input I signal and the differential input Q signal are input in time division by the TDMA method, respectively, and the multiplier 13 and the multiplier 1
4 is a differential input I signal and a differential input Q on the carrier respectively.
The signals are multiplied (modulated) and the multiplication result (modulated signal) is output to the adder 15.

The adder 15 includes a multiplier 12 and a multiplier 14.
The signals input from are added, and the addition result is output.

That is, the oscillator 11, the multiplier 12,
The π / 2 phase shifter 13, the multiplier 14, and the adder 15 together constitute a balanced modulation circuit 10 that modulates an input signal input by the TDMA method.

The directional coupler 16 is composed of, for example, a resistor and a strip line, and takes out the modulation signal output from the adder 15, particularly the carrier wave when the differential input I signal and the differential input Q signal are not input. Then, the detection signal is output to the detection circuit 17.

The detection circuit 17 detects the level of the input detection signal (carrier suppression level) and outputs the carrier suppression level to the low-pass filter 21 of the control circuit 18.

The low-pass filter 21 A / A only the low frequency signal of the carrier suppression levels output from the detection circuit 17.
The signal is output to the D conversion circuit 22, and the A / D conversion circuit 22 converts this carrier suppression level into a digital signal, and the CPU
It outputs to 19.

The ROM 20 stores the program as the control circuit 18 and the carrier wave suppression at the maximum, that is, the multiplier 1
2 and the differential input to the multiplier 14 are balanced, the carrier suppression level (basic carrier suppression level data) is stored, and the CPU 19 stores the carrier suppression level input from the A / D conversion circuit 22. Is compared with the basic carrier suppression level data stored in the ROM 20, and the adjustment pulse signal is adjusted so that the carrier suppression level detected by the directional coupler 16 is closest to the maximum.
Output to the A conversion circuit 24.

The TDMA pulse signal is also input to the CPU 19, and the CPU 19 determines from this TDMA pulse signal when the modulated output from the adder 15 is only the carrier wave. The suppression level is compared with the basic carrier suppression level data.

That is, the balanced modulation circuit 10 uses the TDMA
The differential input I signal and the differential input Q signal are input and modulated and output by the (Time Division Multiple Access) method, except when the burst transmission operation of the TDMA method is performed, that is, the differential input I signal and the differential input signal. The directional coupler 16 outputs the modulation output when the input Q signal is not input (only the carrier wave).
The carrier suppression level is detected by detecting the carrier suppression level.

The carrier suppression level detected by the directional coupler 16 at times other than this burst transmission operation is compared by the basic carrier suppression level data in the ROM 20 with the CPU 19 so that the carrier suppression level is maximized. The pulse signal is converted into a D / A conversion circuit 23 and a D / A conversion circuit 24.
Output to.

The adjusted pulse signal output to the D / A conversion circuit 23 is supplied to the D / A conversion circuit 23 and the low pass filter 25.
Is converted into a voltage by means of and is added as a bias of the differential input I signal.

The adjusted pulse signal output to the D / A conversion circuit 24 is converted into a voltage by the D / A conversion circuit 24 and the low pass filter 26, and added as a bias of the differential input Q signal.

Next, the operation of this embodiment will be described.

The balanced modulation circuit 10 transmits a modulation output based on the TDMA method, and performs modulation at a timing other than the TDMA burst transmission operation, that is, at a timing when the differential input I signal and the differential input Q signal are not input. The carrier suppression level is detected from the output (only the carrier), the detected carrier suppression level is compared with the basic carrier suppression level data, and balance adjustment is performed so that the detected carrier suppression level becomes maximum.

That is, the balanced modulation circuit 27 includes the oscillator 1
The carrier wave generated in 1 and the carrier wave whose phase is shifted by the π / 2 phase shifter 13 are added to the TDM by the multiplier 12 and the multiplier 14.
The differential input I signal and the differential input Q signal input by the A system are multiplied, and the multiplication result is added by the adder 15 and output as a modulation signal.

This modulated output is detected by the directional coupler 16 and detected by the detection circuit 17, and then converted into digital data by the low-pass filter 21 and the A / D conversion circuit 22 of the control circuit 18 to suppress the carrier wave suppression level. Is taken into the CPU 19.

Based on the TDMA pulse signal, the CPU 19 sets the carrier suppression level of the carrier suppression level at a timing other than the TDMA burst transmission operation, that is, at the timing when the differential input I signal and the differential input Q signal are not input. The adjustment pulse signal is compared with the D / A conversion circuit 23 and the D / A conversion circuit 23 so that the carrier suppression level becomes maximum as compared with the basic carrier suppression level data stored in the ROM 20.
Output to the / A conversion circuit 24.

This adjustment pulse signal is supplied to the D / A conversion circuit 2
3 and the low-pass filter 25, and the D / A conversion circuit 24 and the low-pass filter 26 respectively convert the voltages into voltages, which are added as biases of the differential input I signal and the differential input Q signal, respectively.

Therefore, in the balanced modulation circuit 10, it is not necessary to manually adjust the balance of the differential input I signal and the differential input Q signal, and the balance adjustment work can be omitted. Further, the balance adjustment of the differential input I signal and the differential input Q signal can be accurately performed, and appropriate balanced modulation can be performed.

In the above embodiment, the case where the present invention is applied to the balanced modulation circuit 10 of the TDMA system has been described, but it goes without saying that the present invention is not limited to this.

[0038]

Since the differential input can be automatically adjusted based on the modulation output, the adjustment work of the balance adjustment of the differential input can be omitted and appropriate balanced modulation can be performed.

[Brief description of drawings]

FIG. 1 is a circuit block configuration diagram of an embodiment of a balanced modulation circuit of the present invention.

FIG. 2 is a circuit block configuration diagram of an example of a conventional balanced modulation circuit.

[Explanation of symbols]

 10 Balanced Modulation Circuit 11 Oscillator 12, 14 Multiplier 13 π / 2 Phase Shifter 15 Adder 16 Directional Coupler 17 Detection Circuit 18 Control Circuit 19 CPU 20 ROM 21, 25, 26 Low Pass Filter 22 A / D Conversion Circuit 23 , 24 D / A conversion circuit

Claims (2)

[Claims] 1. A modulation means for superimposing an input signal on at least two types of carrier waves having different phases and then synthesizing and modulating the carrier wave, a detection means for detecting an output level of the modulation means, and an input signal to the modulation means. Balance adjusting means for adjusting the balance of the input signal input to the modulating means based on the detection result of the detecting means when there is no 2. The balanced modulation circuit according to claim 1, wherein said modulation means modulates an input signal inputted based on a time division multiplexing system.