JPH04142847A - Carrier recovery circuit - Google Patents

Carrier recovery circuit

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Publication number
JPH04142847A
JPH04142847A JP2265004A JP26500490A JPH04142847A JP H04142847 A JPH04142847 A JP H04142847A JP 2265004 A JP2265004 A JP 2265004A JP 26500490 A JP26500490 A JP 26500490A JP H04142847 A JPH04142847 A JP H04142847A
Authority
JP
Japan
Prior art keywords
complex
phase
circuit
signal
detection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2265004A
Other languages
Japanese (ja)
Other versions
JP3058906B2 (en
Inventor
Hidehiro Takahashi
英博 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2265004A priority Critical patent/JP3058906B2/en
Publication of JPH04142847A publication Critical patent/JPH04142847A/en
Application granted granted Critical
Publication of JP3058906B2 publication Critical patent/JP3058906B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To eliminate a steady-state phase error by obtaining a complex correlation between a complex signal subject to phase rotation and a reference signal corresponding to a complex signal waveform, detecting a phase from a peak level for a prescribed period and controlling a VCO circuit based on the phase. CONSTITUTION:A received modulation wave is fed to a phase rotation circuit 21 as a complex signal and subject to phase rotation by complex multiplication with an output of a VCO(voltage controlled oscillator) circuit 22, the result is fed to a complex correlation detection circuit 23, which generates a reference signal corresponding to the modulation signal waveform in its inside and outputs a complex correlation of both the signals. The complex correlation is fed to a peak detection circuit 24, which detects a complex peak for each symbol, a phase detection circuit 25 extracts a phase from the complex peak and uses a loop filter 26 to eliminate the noise component and the result is converted into a voltage control signal, which controls the VCO circuit 22. Thus, a steady- state phase error is eliminated regardless of the modulation system and an excellent carrier is recovered.

Description

【発明の詳細な説明】 [発明の目的コ (産業上の利用分野) この発明は、デジタル位相変調波の受信機にて、キャリ
アを再生して同期検波に用いるキャリア再生回路に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Industrial Application Field) The present invention relates to a carrier regeneration circuit used for coherent detection by regenerating a carrier in a digital phase modulated wave receiver.

(従来の技術) 従来のデジタル位相変調波を受信する受信機にあっては
、第4図に示すようなキャリア再生回路を用いて、受信
変調波から同期検波に必要とされるギヤリアを再生して
いる。すなわち、第4図のキャリア再生回路では、受信
変調波は位相回転回路1jに供給され、ここて複素信号
としてVCO(電圧制御発振)回路12の出力との複素
乗算による位相回転を受けて、位相検出回路I3に供給
される。この位相検出回路13は上記複素乗算によって
得られた信号の位相量を抽出するものである。この位相
量は、VCO回路I2の出力と受信キャリアとの位相差
に相当する。そこで、位相検出回路13で得られた位相
量をループフィルタ14で積分して電圧信号に変換し、
この電圧信号でVCO回路12を制御することにより、
受信変調波に追随するキャリアを再生している。
(Prior art) In a conventional receiver that receives digital phase modulated waves, a carrier regeneration circuit as shown in Fig. 4 is used to regenerate the gear carrier required for coherent detection from the received modulated wave. ing. That is, in the carrier regeneration circuit of FIG. 4, the received modulated wave is supplied to the phase rotation circuit 1j, where it undergoes phase rotation by complex multiplication with the output of the VCO (voltage controlled oscillation) circuit 12 as a complex signal, and the phase The signal is supplied to the detection circuit I3. This phase detection circuit 13 extracts the phase amount of the signal obtained by the above-mentioned complex multiplication. This phase amount corresponds to the phase difference between the output of the VCO circuit I2 and the received carrier. Therefore, the phase amount obtained by the phase detection circuit 13 is integrated by the loop filter 14 and converted into a voltage signal.
By controlling the VCO circuit 12 with this voltage signal,
It reproduces the carrier that follows the received modulated wave.

しかしながら、上記構成のキャリア再生回路では、特に
オフセットQPSK変調波においては再生キャリアに定
常的な位相誤差が生じ、誤り率特性が劣化するとの不都
合かあった。このような不都合を回避する手段として、
変調波形の収束的部分、すなイつち、いわゆるアイパタ
ーン中央点での位相誤差のみ、キャリア再生ループに入
力することが考えられる。しかし、このためにはまずク
ロック同期が確立していることが条件になるため、受信
機全体の同期確立時間が長くなるとの不都合かある。さ
らに、変調波形として収束点を有する、いわゆるコサイ
ンロールオフ型変調波形に応用が限られるという不都合
がある。
However, in the carrier regeneration circuit having the above configuration, a steady phase error occurs in the regenerated carrier, especially in the case of an offset QPSK modulated wave, resulting in deterioration of error rate characteristics. As a means to avoid such inconvenience,
It is conceivable that only the convergent part of the modulated waveform, that is, the phase error at the so-called center point of the eye pattern, is input to the carrier recovery loop. However, this requires that clock synchronization be established first, which is disadvantageous in that it takes a long time to establish synchronization for the entire receiver. Furthermore, there is a disadvantage that the application is limited to so-called cosine roll-off type modulation waveforms that have a convergence point as a modulation waveform.

(発明か解決しようとする課題) 以上述べたように従来のキャリア再生回路では、再生キ
ャリアに定常的な位相誤差が生じ、これを改善するため
にはクロック同期の確立が要求され、さらには変調方式
か特定されてしまう。
(Problem to be solved by the invention) As described above, in the conventional carrier regeneration circuit, a steady phase error occurs in the regenerated carrier, and in order to improve this, it is required to establish clock synchronization, and furthermore, The method will be specified.

この発明は上記の問題を解決するためになされたもので
、デジタル位相変調であるならば、クロック同期の確立
を必要とせず、また変調方式にかかイっらずに定常的な
位相誤差をなくし、良好なキャリアを再生することので
きるキャリア再生回路を提供することを目的とする。
This invention was made to solve the above problem. Digital phase modulation eliminates the need to establish clock synchronization and eliminates steady phase errors regardless of the modulation method. It is an object of the present invention to provide a carrier regeneration circuit that can regenerate a good carrier without removing the carrier.

[発明の構成] (課題を解決するための手段) 上記目的を達成するためにこの発明に係るキャリア再生
回路は、受信変調波を複素信号として入力すると共に周
波数信号を入力し、当該周波数信号に基づいて前記複素
信号を位相回転させる位相回転回路と、この位相回転回
路から出力される複素信号を入力して内部で複素信号波
形に対応した参照信号を発生し、前記複素信号との複素
相関値を出力する複素ト1」閉検出回路と、この複素相
関検出回路の出力の一定期間毎の複素ピーク値を検出す
るピーク検出回路と、このピーク検出回路の出力から複
素ピーク値の位相量を抽出し、雑音成分を除去して電圧
制御信号に変換するループフィルタと、このループフィ
ルタで得られた電圧制御信号に応じて前記位相回転回路
への周波数信号を発生する電圧制御発振回路とを具備し
て構成される。
[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a carrier regeneration circuit according to the present invention inputs a received modulated wave as a complex signal and also inputs a frequency signal. a phase rotation circuit that rotates the phase of the complex signal based on the input of the complex signal output from the phase rotation circuit, generates a reference signal corresponding to the complex signal waveform internally, and generates a complex correlation value with the complex signal. A complex peak detection circuit that detects the complex peak value of the output of this complex correlation detection circuit at fixed intervals, and extracts the phase amount of the complex peak value from the output of this peak detection circuit. and includes a loop filter that removes a noise component and converts it into a voltage control signal, and a voltage controlled oscillation circuit that generates a frequency signal to the phase rotation circuit in accordance with the voltage control signal obtained by the loop filter. It consists of

(作用) 上記構成によるキャリア再生回路では、位相回転された
複素信号について、複素信号波形に対応した参照信号と
の複素相関値を求め、一定期間におけるピーク値から位
相量を検出し、この位相量に基づいて電圧制御発振回路
を制御しているので、電圧制御発振回路から出力される
キャリア再生信号を受信変調波の位相変化に確実に追随
させ、定常的な位相誤差をなくし、例えば振幅制限のよ
うな非直線歪みに起因する誤り率特性の劣化を改善する
ことができる。
(Operation) In the carrier regeneration circuit having the above configuration, the complex correlation value of the phase-rotated complex signal with the reference signal corresponding to the complex signal waveform is obtained, the phase amount is detected from the peak value in a certain period, and the phase amount is Since the voltage controlled oscillator circuit is controlled based on It is possible to improve the deterioration of error rate characteristics caused by such nonlinear distortion.

(実施例) 以下、第1図乃至第3図を参照してこの発明の一実施例
を説明する。
(Embodiment) Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 3.

第3図はその全体構成を示すもので、受信変調波は複素
信号として位相回転回路21に供給され、VCO回路2
2の出力との複素乗算によって位相回転を受け、さらに
複素相関検出回路23に送られる。
FIG. 3 shows its overall configuration. The received modulated wave is supplied as a complex signal to the phase rotation circuit 21, and the VCO circuit 21 receives the modulated wave as a complex signal.
It undergoes phase rotation by complex multiplication with the output of 2, and is further sent to the complex correlation detection circuit 23.

この複素相関検出回路23は、内部で変調信号波形に対
応した参照信号を発生し、両信号の複素相関値を出力す
るものである。この複素相関値は1シンボル毎に高い絶
対値を示す。
This complex correlation detection circuit 23 internally generates a reference signal corresponding to the modulation signal waveform and outputs a complex correlation value of both signals. This complex correlation value shows a high absolute value for each symbol.

この複素相関値はピーク検出回路2.4に供給される。This complex correlation value is supplied to a peak detection circuit 2.4.

このピーク検出回路24は上述した1シンボル毎の複素
ピーク値を検出するものである。ここで検出された複素
ピーク値の位相成分はVco回路22の出力と受信キャ
リアとの位相差を示す。そこで、位相検出回路25によ
りこの位相差、すなわち複素ピーク値から位相量を抽出
し、ループフィルタ26によって雑跨成分を除去して電
圧制御信号に変換し、この信号によってVCO回路22
を制御する。
This peak detection circuit 24 detects the above-mentioned complex peak value for each symbol. The phase component of the complex peak value detected here indicates the phase difference between the output of the Vco circuit 22 and the received carrier. Therefore, the phase detection circuit 25 extracts the phase amount from this phase difference, that is, the complex peak value, and the loop filter 26 removes the miscellaneous components and converts it into a voltage control signal.
control.

すなわち、従来のキャリア再生回路では、瞬時の位相判
定値を全て取り込み、これをループフィルタで平均化し
ているため、帯域制限の形式によっては正しい位相誤差
が得られなかったが、上記構成のキャリア再生回路では
、相関検出によって1シンボル(あるいは数シンボルで
もよい)の期間に渡った位相誤差を検出しているので、
どのような形式の帯域制限に対しても正しい位相誤差か
得られる。
In other words, in conventional carrier regeneration circuits, all instantaneous phase determination values are taken in and averaged by a loop filter, so depending on the type of band limiting, it may not be possible to obtain the correct phase error. The circuit detects the phase error over a period of one symbol (or several symbols) by correlation detection, so
The correct phase error can be obtained for any type of bandlimiting.

したかって、上記(1−1成によるキャリア再生回路は
、正しい位相誤差が得られるので、再生キャリア位相に
定常誤差か現れなくなり、ビット誤り率の劣化を防ぐこ
とかできる。さらに、サイクルスリップ特性を改善する
ことができ、さらには複素相関検出の期間を調節するこ
とによって初期位相引込み特性を変化させることができ
、設計上の自由度を向上させることができる。
Therefore, since the carrier regeneration circuit based on the 1-1 configuration described above can obtain a correct phase error, a steady error will not appear in the reproduced carrier phase, and deterioration of the bit error rate can be prevented.Furthermore, the cycle slip characteristics can be improved. Furthermore, by adjusting the period of complex correlation detection, the initial phase pull-in characteristic can be changed, and the degree of freedom in design can be improved.

以下、オフセットQPSK変調方式の場合を例にとり、
第1図及び第2図を参照してさらに具体的に説明する。
Taking the case of offset QPSK modulation method as an example,
This will be explained in more detail with reference to FIGS. 1 and 2.

すなわち、衛星利用の移動体通信にオフセット(以下O
と記す)QPSK変調方式を採用する例が多く見られる
か、これは周波数利用効率が良いこと、電力利用効率の
良いC級増幅器を通したときのスペクトル劣化が少ない
こと等の利点によるものである。一方、OP S K変
調方式には、符号点での位相が一定でなく、従来のキャ
リア再生回路では再生位相誤差が生じゃすいという難点
がある。
In other words, offset (hereinafter O
There are many cases where QPSK modulation is adopted, and this is due to its advantages such as good frequency usage efficiency and less spectrum deterioration when passing through a class C amplifier with good power usage efficiency. . On the other hand, the OPSK modulation method has the disadvantage that the phase at the code point is not constant, and a reproduction phase error is likely to occur in a conventional carrier reproduction circuit.

これを改善するために、送受信双方にコサインロールオ
フフィルタを配置する手法が考えられている。すなわち
、OQ P S r<波の位相特性について、コサイン
ロールオフフィルタ系を前提にしたとき、Q P S 
Kでは符号判定時点の位相は90度おきに4点のみであ
る。このことからキャリア位相検出の容易さが理解でき
、特に符号判定点でサンプルする場合は明白である。一
方、0PQSK波は符号判定時点て保証されるのは、直
交2成分のいずれかが一定値になることだけて、信号点
は線」二に存在する。
In order to improve this, a method has been considered in which cosine roll-off filters are placed on both the transmitter and receiver. In other words, regarding the phase characteristics of OQ P S r<wave, assuming a cosine roll-off filter system, Q P S
In K, the phase at the time of sign determination is only 4 points every 90 degrees. From this, the ease of carrier phase detection can be understood, especially when sampling at a sign determination point. On the other hand, in the case of the 0PQSK wave, the only thing guaranteed at the time of sign determination is that one of the two orthogonal components will be a constant value, and the signal point will exist on the line "2".

しかしながら、上記フィルタを配置する手法では、0P
SK波をC級増幅器を介して伝送すると、符号量干渉を
生じてアイパターンの劣化、つまり誤り率特性の劣化を
招く。0PQSK波に定常位相回転を与えた場合の位相
誤差平均値をプロットしてみると、第2図中のパターン
Aのようになる。
However, in the above method of arranging filters, 0P
When an SK wave is transmitted through a class C amplifier, code amount interference occurs, leading to deterioration of the eye pattern, that is, deterioration of error rate characteristics. If the average phase error value when a steady phase rotation is applied to the 0PQSK wave is plotted, it will look like pattern A in FIG. 2.

これは、計算機上で1シンボル当り4サンプルのデータ
を生成し、全てのサンプルの位相安定点(±45°、1
35°)からのずれ(瞬時位相判定値)を求めて平均化
したものである。同図から、位相回転量0付近で不安定
な特性を示していることがわかる。
This generates data of 4 samples per symbol on the computer, and the phase stability point of all samples (±45°, 1
35°) (instantaneous phase determination value) is calculated and averaged. It can be seen from the figure that unstable characteristics are exhibited near the amount of phase rotation of 0.

そこで、この発明では第3図に示した回路構成を利用し
、複素相関回路23を例えば第1図に示すように構成し
て、位相比較特性を改善する。
Therefore, the present invention uses the circuit configuration shown in FIG. 3 and configures the complex correlation circuit 23 as shown in FIG. 1, for example, to improve the phase comparison characteristics.

第1図において、231は8ビツトシリアル形式の0Q
PSK波入力を順次8ビツトパラレルで出力するための
複素アナログシフトレジスタ、232は#1 (00,
00,00,00)から#256(1]、  11.、
 1.1.、 11.)の複素軌跡参照パターンを格納
する記憶装置、233はシフトレジスタ231からの○
PQSK入力について#1〜#256全でのパターンと
の相関をとる相関検出部である。
In Figure 1, 231 is 0Q in 8-bit serial format.
A complex analog shift register for sequentially outputting PSK wave input in 8-bit parallel, 232 is #1 (00,
00,00,00) to #256(1], 11.,
1.1. , 11. ), 233 is a storage device that stores the complex locus reference pattern of
This is a correlation detection unit that takes the correlation with all patterns #1 to #256 for PQSK input.

すなわち、0QPSKの複素軌跡のパターンは有限であ
り、その数はロールオフ係数で定まる。
That is, the number of complex trajectory patterns of 0QPSK is finite, and the number is determined by the roll-off coefficient.

そこで、この相関検出回路23では8ビツト0QPSK
波入力に対して256個の複素軌跡参照パターン#1〜
#256を用意し、その全てについて0QPSK波入力
との相関をとり、絶対値最大の相関値の位相、すなわち
複素相関−F均を検出位相として出力するようしている
。その処理結果を第2図に重ねて示す(図中パターンB
)。パ] O ターンA、Bを比較して明らかなように、位相比較特性
の改善が認められる。
Therefore, in this correlation detection circuit 23, the 8-bit 0QPSK
256 complex locus reference patterns #1 for wave input
#256 is prepared, all of them are correlated with the 0QPSK wave input, and the phase of the correlation value with the maximum absolute value, that is, the complex correlation - F average, is output as the detected phase. The processing results are shown in Fig. 2 (pattern B in the figure).
). [P] O As is clear from comparing Turns A and B, an improvement in the phase comparison characteristics is recognized.

したがって、第1図の構成によれば、従来の瞬時位相判
定では0近傍で大きかった誤差を改善して定常的な位相
誤差をなくし、非直線歪みに起因する誤り率特性の劣化
を改善することかできる。
Therefore, according to the configuration shown in FIG. 1, it is possible to improve errors that were large near 0 in conventional instantaneous phase determination, eliminate steady phase errors, and improve the deterioration of error rate characteristics caused by nonlinear distortion. I can do it.

尚、0QPSK波入力を例にとって説明したか、他のデ
ジタル位相変調方式であっても同様に実施可能であるこ
とはいうまでもない。
It should be noted that although the explanation has been made using the 0QPSK wave input as an example, it goes without saying that the same implementation is possible even with other digital phase modulation methods.

[発明の効果] 以上のようにこの発明によれば、デジタル位相変調であ
るならば、クロック同期の確立を必要とせず、また変調
方式にかかわらすに定常的な位相誤差をなくし、良好な
キャリアを再生することのできるキャリア再生回路を提
供することができる。
[Effects of the Invention] As described above, according to the present invention, if digital phase modulation is used, it is not necessary to establish clock synchronization, and regardless of the modulation method, steady phase errors can be eliminated, and a good carrier can be obtained. It is possible to provide a carrier regeneration circuit that can regenerate.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第3図はこの発明に係るキャリア再生回路の
一実施例を示すもので、第1図はこの発明の特徴となる
相関検出回路の具体的な構成を示すブロック回路図、第
2図は従来回路と本願発明に係る回路との位相特性を比
較して示す特性図、第3図はこの発明に係るキャリア再
生回路の全体構成を示すブロック回路図、第4図は従来
のキャリア再生回路の構成を示すブロック回路図である
。 11、21−・・位相回転回路、12.22−= V 
C0回路、13、25・・・位相検出回路、14.28
・・・ループフィルタ、23・・・複素(■量検出回路
、231・・複素アナログシフトレジスタ、232 ・
・格納する記憶装置、233・・・相関検出部、#1〜
#256・・複素軌跡参照パターン、24・・・ピーク
検出回路。
1 to 3 show an embodiment of the carrier regeneration circuit according to the present invention, FIG. 1 is a block circuit diagram showing a specific configuration of the correlation detection circuit which is a feature of the invention, and FIG. The figure is a characteristic diagram showing a comparison of the phase characteristics of a conventional circuit and a circuit according to the present invention, Fig. 3 is a block circuit diagram showing the overall configuration of the carrier regeneration circuit according to the present invention, and Fig. 4 is a conventional carrier regeneration circuit. FIG. 2 is a block circuit diagram showing the configuration of a circuit. 11, 21-...phase rotation circuit, 12.22-=V
C0 circuit, 13, 25...phase detection circuit, 14.28
... Loop filter, 23 ... Complex (■Quantity detection circuit, 231 ... Complex analog shift register, 232 ・
-Storage device, 233...Correlation detection unit, #1~
#256...Complex locus reference pattern, 24...Peak detection circuit.

Claims (3)

【特許請求の範囲】[Claims] (1)受信変調波を複素信号として入力すると共に周波
数信号を入力し、当該周波数信号に基づいて前記複素信
号を位相回転させる位相回転回路と、この位相回転回路
から出力される複素信号を入力して内部で複素信号波形
に対応した参照信号を発生し、前記複素信号との複素相
関値を出力する複素相関検出回路と、この複素相関検出
回路の出力の一定期間毎の複素ピーク値を検出するピー
ク検出回路と、このピーク検出回路の出力から複素ピー
ク値の位相量を抽出し、雑音成分を除去して電圧制御信
号に変換するループフィルタと、このループフィルタで
得られた電圧制御信号に応じて前記位相回転回路への周
波数信号を発生する電圧制御発振回路とを具備するキャ
リア再生回路。
(1) A phase rotation circuit that inputs a received modulated wave as a complex signal and a frequency signal, rotates the phase of the complex signal based on the frequency signal, and inputs the complex signal output from this phase rotation circuit. a complex correlation detection circuit that internally generates a reference signal corresponding to a complex signal waveform and outputs a complex correlation value with the complex signal, and detects a complex peak value of the output of the complex correlation detection circuit every fixed period. A peak detection circuit, a loop filter that extracts the phase amount of the complex peak value from the output of this peak detection circuit, removes noise components, and converts it into a voltage control signal; and a voltage controlled oscillation circuit that generates a frequency signal to the phase rotation circuit.
(2)前記複素相関検出回路は、入力複素信号をシリア
ル/パラレル変換する複素アナログシフトレジスタと、
前記入力複素信号のシンボル数に応じた複素軌跡参照パ
ターンを格納する記憶装置と、前記シフトレジスタから
のパラレル複素入力について前記記憶装置に格納された
全てのパターンとの相関をとり、複素相関平均を検出位
相として出力する相関検出部とで構成されることを特徴
とする請求項1記載のキャリア再生回路。
(2) The complex correlation detection circuit includes a complex analog shift register that converts an input complex signal from serial to parallel;
A storage device that stores complex locus reference patterns corresponding to the number of symbols of the input complex signal is correlated with all patterns stored in the storage device regarding the parallel complex input from the shift register, and a complex correlation average is calculated. 2. The carrier regeneration circuit according to claim 1, further comprising a correlation detection section that outputs a detected phase.
(3)前記受信変調波は振幅制限を受けたオフセットQ
PSK変調波であることを特徴とする請求項1記載のキ
ャリア再生回路。
(3) The received modulated wave has an amplitude limited offset Q
2. The carrier regeneration circuit according to claim 1, wherein the carrier regeneration circuit is a PSK modulated wave.
JP2265004A 1990-10-04 1990-10-04 Carrier regeneration circuit Expired - Fee Related JP3058906B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2265004A JP3058906B2 (en) 1990-10-04 1990-10-04 Carrier regeneration circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2265004A JP3058906B2 (en) 1990-10-04 1990-10-04 Carrier regeneration circuit

Publications (2)

Publication Number Publication Date
JPH04142847A true JPH04142847A (en) 1992-05-15
JP3058906B2 JP3058906B2 (en) 2000-07-04

Family

ID=17411235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2265004A Expired - Fee Related JP3058906B2 (en) 1990-10-04 1990-10-04 Carrier regeneration circuit

Country Status (1)

Country Link
JP (1) JP3058906B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002082758A1 (en) * 2001-03-22 2002-10-17 Mitsubishi Denki Kabushiki Kaisha Frequency error estimating receiver, and frequency error estimating method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102517392B1 (en) * 2021-05-24 2023-04-04 주식회사 디섹 Scaffolding structure for liquefied gas storage tank and installation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002082758A1 (en) * 2001-03-22 2002-10-17 Mitsubishi Denki Kabushiki Kaisha Frequency error estimating receiver, and frequency error estimating method
US7139333B2 (en) 2001-03-22 2006-11-21 Mitsubishi Denki Kabushiki Kaisha Frequency error estimating receiver, and frequency error estimating method

Also Published As

Publication number Publication date
JP3058906B2 (en) 2000-07-04

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