JPH04123555A - Data demodulation circuit - Google Patents

Abstract

PURPOSE:To make a low C/N operation compatible with a high speed locking at a broad band by detecting a beat component from a non-modulation wave and setting a parameter so that a center frequency of a tank circuit section is in matching with an intermediate frequency of a reception signal. CONSTITUTION:An analog demodulation data Sa from a quasi-synchronization detection section 21 is coded by an A/D converter 22 and the result is a digital demodulation signal D' including a beat component, divided into three, the one is fed to a beat detection section 26, from which a parameter control signal Cp corresponding to the beat component is outputted and it is used for parameter control in a digital tank circuit section 25. A digital inverse modulation section 24 receiving the other signal receives a digital demodulation signal D from which the beat component is eliminated and a non-modulation wave of an intermediate frequency is inputted to the tank circuit section 25. A digital phase rotating section 23 receives an intermediate frequency signal from the tank circuit section 25 and the digital demodulation data D' including the beat component and outputs the digital demodulation data D from which the beat component is eliminated. Thus, a low C/N (C is carrier power and N is noise power) operation and high speed locking at a broader frequency range are made compatible.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a data demodulation circuit that synchronously detects a received signal converted to an intermediate frequency and demodulates the data included in the received signal, and has a wide range of input power without being affected by temperature fluctuations. The purpose of this invention is to provide a data demodulation circuit that can simultaneously satisfy high-speed acquisition in a frequency range and low C/N operation. a quasi-synchronous detection section for reproducing analog demodulated data including the beat component;
an analog/digital converter that converts into digital demodulated data including a beat component; and an analog/digital converter that receives the digital demodulated data and operates only at the reception timing of an unmodulated wave portion located at the beginning of the received signal, and corresponds to the beat component. a beat detection unit that outputs a parameter control signal that is determined by the parameter control signal, a digital tank circuit unit that performs a bandpass filtering operation at a center frequency that matches the beat frequency according to the parameter control signal, and a signal of the beat frequency from the digital tank circuit unit. , a digital phase rotation unit that receives digital demodulated data including the beat component and outputs digital demodulated data from which the beat component has been removed; digital demodulated data from which the beat component has been removed; and digital demodulated data including the heat component. and a digital inverse modulator which operates after the reception timing of the unmodulated wave component, generates an unmodulated wave of the beat frequency, and inputs the unmodulated wave to the digital tank circuit.

[Industrial application field]

The present invention relates to a data demodulation circuit that synchronously detects a received signal converted to an intermediate frequency and demodulates data included in the received signal.

For example, a data demodulation circuit is essential for demodulating data included in a PSK-modulated received signal and reproducing the original data. In this case, a carrier regeneration circuit plays an important role in synchronously detecting the received signal.

The present invention describes a data demodulation circuit in which a carrier recovery circuit for receiving and synchronously detecting a burst signal transmitted under a TDMA communication system is particularly improved in a satellite communication system.

[Conventional technology]

FIG. 6 is a block diagram showing a conventional data demodulation circuit. In a satellite communication system, a signal transmitted from another earth station under the TDMA communication method is relayed and amplified by a satellite on the ground, and then received by a receiving earth station. This received signal passes through a high frequency device and is usually converted into an intermediate frequency received signal. Sif in this figure is its intermediate frequency (IF
) is the received signal converted into Furthermore, it is well known that under the TDMA communication system, the received signal Sif appears in a burst form. This received signal Sif is demodulated by a data demodulation circuit 10 and becomes demodulated data. Since orthogonal modulation is generally performed to transmit a large amount of data, the demodulated data is represented in this figure as in-phase data DI and quadrature data DQ.

In the conventional data demodulation circuit IO, the received signal Sif is first inputted to a bandpass filter 11 whose center frequency is an intermediate frequency to remove noise, and then quadrature-detected by a quadrature detector 12. Analog demodulated data of the channel and Q (orthogonal) channel are obtained, and these are digitized by an analog/digital converter (A/D) 13 to obtain demodulated data D1 and Do.

This quadrature detector 12 is a so-called mixer, and combines the received signal Sif that has passed through the bandpass filter 11 with the carrier wave CR (carri
er) and match. Although this carrier wave CR is actually an intermediate frequency (IF) signal, it is usually called a carrier wave. Inverse modulator 4 is widely used to generate this carrier wave. The inverse modulator 14 receives the received signal Sif that has passed through the filter 11 and the analog demodulated data from the detector 12 as input, and reproduces a carrier wave CR" (intermediate frequency).
A carrier wave CR with less noise is obtained through a tank circuit 15 whose center frequency is an intermediate frequency. In order to obtain an ideal sine wave as the carrier wave CR', both the received signal Sif and the analog demodulated data must be applied to the inverse modulator 14 in complete synchronization. In this case, the carrier wave CR required to generate analog demodulated data is accompanied by a time delay when passing through the tank circuit 15. Therefore, in order to satisfy the above synchronization, the received signal Sif is delayed by the delay circuit (τ) 16 by an amount commensurate with the time delay.

[Problem to be solved by the invention]

The data demodulation circuit IO shown in FIG.
and a delay circuit 16 are employed. In this case, since the output phase of the tank circuit 15 changes depending on the frequency, it is necessary to compensate for the phase-frequency characteristics in order to expand the specifiable frequency range to a practical range. , converts the frequency into a low-frequency signal, and transmits the second signal to the tank circuit consisting of a low-pass filter (LPF).
low-pass filters (LPF2) are connected in parallel, and the output of the above low-pass filter (LPF, ) is connected to the second low-pass filter (LPF2).
Negative feedback is provided to the input of a low-pass filter (LPF) through the filter, and the frequency is converted to the original intermediate frequency.

However, for low C/N operation, when the passband of the tank circuit 15 is narrowed in an attempt to remove -layer noise, the above phase-frequency characteristics change greatly, and even after the above compensation, the paper sheet The possible frequency range becomes narrower and narrower.
It becomes difficult to widen the above-mentioned paper sheet possible frequency range. In other words, it is not possible to achieve both low C/N operation and high-speed pull-in over a wider frequency range.

However, in the current situation where the frequency devices mentioned above have become more sophisticated and the coding gain of error correction devices has improved, low C//
There is a strong demand for both N operation and high-speed pull-in in a wider pull-in range. In addition, the data demodulation circuit 1
The operation speed is too fast to assemble 0 with cheap LSI,
Normally, data demodulation circuit 10 can only be constructed from analog circuits. For this reason, there is a problem in that characteristics change due to temperature fluctuations inherent in analog circuits make it even more difficult to achieve the above-mentioned compatibility.

Therefore, in view of the above problems, it is an object of the present invention to provide a data demodulation circuit that can simultaneously satisfy high-speed pull-in over a wide pull-in frequency range and low C/N operation without being affected by temperature fluctuations. It is something to do.

[Means to solve the problem]

FIG. 1 is a principle block diagram of a data demodulation circuit according to the present invention. In this figure, the data demodulation circuit 20 includes a quasi-synchronous detection section 21 that performs quasi-synchronous detection of the received signal Sif, an anarcho/digital conversion section 22 that converts the output into a digital signal, and a digital phase rotation section that receives the output. 23, an inverse modulation section 24, a beat detection section 26, and a digital tank circuit section 25 that is controlled by the output of the beat detection section 26 and passes the output from the inverse modulation section 24 to the digital phase rotation section 23. Here, the phase rotation section 23
Obtain the demodulated data D from the output of
On the other hand, is input to the inverse modulation section 24.

[Effect]

The quasi-synchronous detection section 21 performs orthogonal detection using an intermediate frequency close to the intermediate frequency that is the frequency of the received signal Sif, and has been developed in recent years because it can directly obtain a baseband signal without intervening complicated carrier recovery means. It is becoming widely used. In this case, for example, the received signal Si of several MHz
With respect to the frequency (intermediate frequency) of f, the intermediate frequency built in the quasi-synchronous detection section 21 has a deviation of several kHz, for example.
The deviation becomes a beat component and is superimposed on the base band signal. However, even if beat components are included, subsequent processing can be done in the low frequency bass hunt band, so L
Digital circuitization using SI can be realized extremely easily.

If it becomes possible to introduce digital circuits using LSI, fairly complex signal processing will become easier. Taking advantage of this advantage,
Complex parameter control can be performed at high speed on the LSI forming the digital tank circuit section 25. For example, since the digital tank circuit section 25 can be configured with a digital transversal filter or a recursive filter, its tap coefficients can be controlled complexly and quickly. Here, high-speed pull-in and low C/N operation in a wide pull-in frequency range can be simultaneously satisfied.

Furthermore, since it is a digital circuit, the effects of temperature fluctuations inherent in analog circuits can be almost ignored.

Referring to FIG. 1, analog demodulated data S containing a beat component from the quasi-synchronous detection section 21 is encoded by an analog/digital conversion section 22 to become digital demodulated data D'' containing a beat component. This D' is branched into three branches, one of which is applied to the beat detection section 26. This detecting section 26 outputs a parameter control signal CP corresponding to the beat component, which is used for parameter control in the digital tank circuit section 25. This beat component detection can be performed accurately using the non-modulated wave portion of the received signal Sif.

FIG. 2 is a diagram showing the signal format of a general burst signal, and is for explaining the above-mentioned non-modulated wave portion. A burst signal in the TDMA communication system usually has a signal portion called a preamble added to its beginning. That is, a non-modulated wave portion always exists at the beginning of the received signal Sif. However, it is possible to add a similar non-modulated wave portion to systems other than the TDMA communication system.

As shown in Figure 2, this preamble consists of a series of data "1" (for example, 48 bits) and a series of data "OI" (
For example, 48 bits) and a unique word for taking autocorrelation, followed by the original data (.The part after the continuous "0" is the modulated wave part. Therefore, the continuous part of the data "l" A non-modulated wave portion can be obtained.Therefore, the beat detection section 26 shown in Fig. 1 operates only at the reception timing of the above-mentioned non-modulated wave portion.This reception timing may vary depending on the fluctuation of the card time. Although there are some errors, the approximate timing can be known in advance from the receiving earth station.

As described above, the parameter control signal Cp corresponding to the beat component thus detected is sent to the digital tank circuit section 25. The circuit section 25 performs a bandpass filtering operation on the output from the digital inverse modulation section 24 at a center frequency matching the beat frequency according to the parameter control signal Cp, and outputs a noise-free intermediate frequency as a carrier wave CR.

The digital phase rotation section 23 inputs the intermediate frequency signal from the tank circuit section 25 and the digital demodulated data D° including the beat component, and outputs the digital demodulated data D from which the beat component has been removed.

The digital inverse modulator 24 inputs the digital demodulated data D from which the beat component has been removed and the digital demodulated data D'' that includes the beat component, operates after the reception timing of the non-modulated wave portion described above, and de-modulates the intermediate frequency. The modulated wave is generated as a carrier wave CR' and inputted to the tank circuit section 25.

〔Example〕

FIG. 3 is a block diagram showing an embodiment of a data demodulation circuit according to the present invention. Note that similar components are designated with the same reference numbers or symbols throughout the drawings. This figure shows the case of orthogonal modulation, where there are a ■ channel and a Q channel, and finally I channel and Q channel demodulated data D1
and Do shall be obtained. The quasi-synchronous detection unit 21 includes a mixer 41 and an intermediate frequency signal source 42, and this intermediate frequency takes a value close to the intermediate frequency of the received signal Sif.

A close value means that a deviation of several kHz may occur, for example. Further, the digital tank circuit section 25 has a sin
It consists of a sideband filter 43 and a cos sideband filter 44, both of which are constructed from digital transversal filters. 1 channel and Q from quasi-synchronous detection section 21
analog demodulated data S including a beat component of the channel;
are respectively I forming the analog/digital converter 22
It is applied to the channel side A/D 45 and the Q channel side A/D 46 to obtain digital demodulated data D+' and Do' each containing a beat component. In addition, in the previous stage of these,
Low pass filters 31 and 32 are provided. This is to remove the sum frequency component caused by frequency mixing in the mixer 41.

The above data D+' and DQ' are stored in the beat detection section 26
is applied to detect the beat component.

A gate signal Sg is input to the detection section 26. The gate signal Sg is turned on only at the reception timing of the non-modulated wave portion. The parameter control signal Cp corresponding to the beat component thus detected is input to a read-only memory (ROM) 35. The ROM 35 stores in advance tap coefficients to be applied to bandpass filters 43 and 44, each of which is a digital transversal filter.

Various tap coefficients are available and differ depending on the size of the beat component. An overview is shown in the table below with an example. Note that Δf is a beat component.

K represents a tap coefficient. "Δf=0", "
Δf is large" is determined by the parameter control signal Cp described above (see FIG. 4).

FIG. 4 is a graph showing the relationship between the parameter control signal Cp and the beat component Δf. For ease of understanding, it is expressed as an analog quantity. 8f is large in this figure, Δf is MAX.
Δf=0 corresponds to the origin of the graph. The area actually used is the hatched area in the figure.

Returning to FIG. 3, the above data D1' and DQo are applied to the phase rotation section 23, where they are converted into demodulated data D+ and Do from which beat components have been removed. For this purpose, sin side and cos side intermediate frequencies (carrier wave CR) are applied to this phase rotation unit 23 from the sin side and COS side bandpass filters 43 and 44. These sine side and CO5 side intermediate frequencies are set based on the parameter control signal Cp from the beat detection section 26 at the beginning of burst signal reception. That is, bandpass filters 43 and 44 are operated with tap coefficients determined by Cp. This tap coefficient is supplied from the ROM 35. In this case, the inverse modulator 2
4 is in a stopped state. This stop period is during the reception timing of the non-modulated wave portion described above, and therefore the gate signal Sg, which is an inverted signal of the gate signal Sg described above, is supplied to the inverse modulation section 24. Here, the digital transversal filters (43, 44) have the following tap coefficients:
The center frequency of the tank circuit can be immediately matched to the intermediate frequency of the received signal Sif, and can be set to a narrow band that can increase the necessary S/N ratio (low C/N operation).

After the reception timing of the non-modulated wave part, the gate signal Sg
is off, the gate signal Sg is turned on, and the inverse modulation section 24 receives the digital demodulated data D+' and DQ'' including the beat component and the digital demodulated data D1 and DQ from which the beat component has been removed, and outputs the intermediate frequency (CR'). is output from the inverse modulation section 24. Note that the data DI' and Do'
On the other hand, adding delays in the delay circuits (τ) 33 and 34 is the same as providing the delay circuit 16 in the conventional circuit. The tap coefficients used when the digital transversal filter (43.degree. 44) operates upon receiving this intermediate frequency (CR") are selected from values that allow high-speed pull-in in a wide pull-in frequency range, and are supplied from the ROM 35.

FIG. 5 is a circuit diagram specifically showing some blocks in FIG. 3. In this figure, especially the block 23 in FIG.
．． 24 and 26 are shown in detail, and the digital tank circuit section 25 is a digital transversal filter D.
Denoted as TP. In this figure, the parts marked with X are multipliers, the parts marked with earth are adders, and some of the inputs to the adders are subtraction inputs. As shown in the figure, both the digital phase rotation section 23 and the inverse modulation section 24 perform similar functions.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to first detect the beat component in the non-modulated wave portion and quickly set the parameters to match the center frequency of the tank circuit section to the intermediate frequency of the received signal. can be made narrowband. Next, by quickly changing the parameter setting section, high-speed pull-in can be achieved with a wide pull-in frequency. In this way, it is possible to achieve both low C/N operation and high-speed pull-in over a wide band3.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of a data demodulation circuit according to the present invention, Fig. 2 is a diagram showing a signal format of a general burst signal, and Fig. 3 is a block diagram showing an embodiment of a data demodulation circuit according to the present invention. Figure 4 is a graph showing the relationship between the parameter control signal Cp and the beat component Δf, Figure 5 is a circuit diagram specifically showing some blocks in Figure 3, and Figure 6 is a conventional data demodulation circuit. FIG. In the figure, 20... data demodulation circuit, 21... quasi-synchronous detection section, 22... analog/digital conversion section, 23...
- Digital phase rotation section, 24... Digital inverse modulation section, 25... Digital tank circuit section, 26... Beat detection section, Sif... Received signal. The principle of the data recovery circuit according to the present invention Part 1
Graph diagram showing the relationship between the parameter control signal C1 and the second component △f

Claims (1)

[Claims] In a data demodulation circuit that synchronously detects a received signal (Sif) converted to an intermediate frequency and demodulates data included in the received signal (Sif), quadrature detection is performed using a frequency close to the intermediate frequency. and converts the analog demodulated data (S_a) containing the beat component into digital demodulated data (D') containing the beat component. Analog/digital converter (22
), a parameter control signal (Cp) that receives the digital demodulated data (D'), operates only at the reception timing of the unmodulated wave portion located at the beginning of the received signal (Sif), and corresponds to the beat component. a beat detection section (26) that outputs a beat frequency, a digital tank circuit section (25) that performs a bandpass filtering operation at a center frequency that matches the beat frequency according to the parameter control signal (Cp), and the digital tank circuit section (25). The digital demodulated data (D') from which the beat component has been removed is obtained by inputting the signal at the beat frequency and the digital demodulated data (D') containing the beat component.
), inputs the digital demodulated data (D) from which the beat component has been removed, and the digital demodulated data (D') including the beat component, and outputs the unmodulated wave component. A data demodulation circuit comprising a digital inverse modulation section (24) that operates after the reception timing and generates an unmodulated wave of the beat frequency and inputs it to the digital tank circuit section (25).