JP3211034B2 - Noise removal equipment for digital signals - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for removing a noise component of a digital signal, and more particularly to a device for removing a noise component due to a bit error of a digital signal in digital data transmission.

[0002]

2. Description of the Related Art Data transmission by digital signals is represented by L
It is used in ANs, data transmission between computers, integrated public communication networks, and the like.

In digital data transmission, a digital signal used for data transmission is composed of "1" and "1" using a rectangular wave pulse defined in advance, such as a Manchester encoding method.
Since the signal is a simple binary signal of "0", even if the transmission signal is deformed in the transmission line, the correction and reproduction can be performed reliably, and the fidelity is superior to the data transmission by the analog signal. Reliable data transmission is performed.

Therefore, in digital data transmission, it is not necessary to pay attention to transmission of a signal having a waveform with little distortion as in analog transmission. However, even if it is a digital signal, if the waveform is greatly disturbed by noise, a bit error may occur during reproduction depending on the sampling timing of the received signal, and the originally one rectangular pulse may be replaced by two rectangular pulses. In other words, so-called pulse cracking may occur. When this pulse crack occurs, correct data transmission cannot be performed.

[0005]

Conventionally, data transmission is performed according to a transmission protocol such as performing a parity check or the like and issuing a data retransmission request to a transmission source when data is abnormal. . However, requesting the source to retransmit data when data is abnormal is an obstacle to improving data transmission efficiency, and the parity check cannot reliably detect the occurrence of noise components such as pulse cracks. I can't compensate.

The present invention has been made in view of the above-mentioned problems in the conventional digital data transmission, and detects the occurrence of noise components such as pulse cracks with high reliability. It is an object of the present invention to provide a digital signal noise component elimination device that automatically eliminates noise components such as cracks.

[0007]

SUMMARY OF THE INVENTION According to the present invention, a digital signal is divided into a predetermined number of bits to be sequentially inputted in synchronization with a sampling clock having a frequency higher than the clock frequency of the digital signal. A synchronous shift register, a signal inverting circuit for latching and selectively inverting a predetermined bit signal of the synchronous shift register, and a signal of each bit inputted to the synchronous shift register being inputted in parallel. , The input signal “1”,
A switching circuit for controlling the operation of the signal inverting circuit based on a combination of "0".

[0008]

According to the above construction, the digital signal is divided by the synchronous shift register according to the clock frequency and latched in time series by the number corresponding to the bit number of the synchronous shift register. The operation of the signal inversion circuit is controlled based on the output signal of each bit of the synchronous shift register, that is, the combination of "1" and "0" of the divided digital signal. A predetermined bit input signal (divided digital signal) is selectively inverted to remove noise components.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 1 shows a basic configuration of a digital signal noise component removing apparatus according to the present invention. This noise component removing device has an input data sampling circuit 1 and a switching circuit 3.

FIG. 2 shows an embodiment of the detailed configuration of the digital signal noise component removing apparatus according to the present invention. In this embodiment, the input data sampling circuit 1
Is a circuit for inputting a digital signal (input data), and includes five D-type flip-flops 5, 7,
9, 11 and 13, a 5-bit synchronous shift register 15, a third D-type flip-flop 9 and a fourth D-type flip-flop 9.
A two-input one-output multiplexer 17 as a signal inversion circuit provided between the fourth D-type flip-flop 11 and the fifth D-type flip-flop 13. And a two-input one-output multiplexer 19 as another signal inverting circuit.

Each of the D-type flip-flops 5, 7, 9, 11, and 13 of the synchronous shift register 15 receives a clock signal (system clock signal) synchronized with a clock signal of an input digital signal to a clock input CLK, Each time a clock signal is supplied to the clock input CLK, input data supplied to the input D is sequentially latched. The synchronous shift register 15 directly takes in input data from the outside into the D-type flip-flop 5 of the first bit, and the D-type flip-flop 13 of the most significant bit.
It is designed to output more data.

In this case, the frequency of the system clock signal is set to about 32 MHz, while the baud rate is a value corresponding to about 2 MHz in the digital signal by the Manchester encoding method.

Therefore, the input data is divided by the system clock frequency and each D-type flip-flop 5, 7,
Samples 9, 11 and 13 are sequentially input.

The five D-type flip-flops 5, 7,
Out of 9, 11, and 13, the first D-type flip-flop 5, the second D-type flip-flop 7, and the most significant bit D-type flip-flop 13 have only the non-inverted output Q as an output. However, the third D-type flip-flop 9 and the fourth D-type flip-flop 11 have the non-inverted output Q
And the inverted output QN. The non-inverted output Q of the D-type flip-flop 9 is used as the input A of the multiplexer 17, and the inverted output QN of the input A is input B of the multiplexer 17.
The non-inverted output Q of the other D-type flip-flop 11 is used as the input A of the multiplexer 19, and the inverted output QN is used as the input B of the multiplexer 19.

Each of the multiplexers 17 and 19 selects the input A as the output Y when the select signals SEL1 and SEL2 are "1", while the select signals SEL1 and SE
When L2 is "0", input B is selected as output Y. As a result, when the select signal SEL is "1", the multiplexers 17 and 19 respectively use the input data input to the preceding D-type flip-flop 9 or 11 as they are, as they are, in the subsequent D-type flip-flop 11 or 1 respectively.
3 and the select signals SEL1, SEL2
Is "0", the input data input to the preceding D-type flip-flop 9 or 11 is inverted and output to the subsequent D-type flip-flop 11 or 13.

Thus, the input signals of the fourth bit and the most significant bit of the synchronous shift register 15 are selectively inverted.

The number of bits for this signal inversion is one state (""
In the input data of "1" or "0"), it is set according to the number of system clocks at which noise may continuously occur. When this number of clocks is Cn, it is necessary for noise determination. The sampling number S of the input data (the sampling number of the divided input data) is represented by the following equation.

S ≧ 2Cn + 1 The number of samplings S of the input data is determined by the number of bits of the synchronous shift register 15. In this embodiment, the number of system clocks Cn which is likely to cause noise is 2 so that The sampling number Bs must be at least 5, and the number of bits of the synchronous shift register 15 is set to 5 based on this.

Each of the multiplexers 17 and 19 individually receives the select signals SEL1 and SEL2 from the switching circuit 3.

The switching circuit 3 inputs the output signal of each bit of the synchronous shift register 15 from the output Q of each of the D-type flip-flops 5, 7, 9, 11, and 13, and outputs "1", "1" of this output signal. Multiplexer 1 based on the combination of 0 "
Select signals SEL1, SEL2 output to 7 and 19
Are individually switched between “1” and “0”. This is based on a predetermined rule based on a combination of “1” and “0” of the output signal of each bit of the synchronous shift register 15. The input signal is determined to be normal or abnormal in accordance with the following equation (1). When the input data is determined to be normal, the select signals SEL1 and SEL2 are both set to "1". "Is switched to.

FIG. 3 shows an example of a switching rule for the select signals SEL1 and SEL2. In FIG.
Q1 is the output Q of the D-type flip-flop 5, Q2 is the output Q of the D-type flip-flop 7, Q3 is the output Q of the D-type flip-flop 9, Q4 is the output Q of the D-type flip-flop 11, and Q5 is the D-type flip-flop. 13 is the output Q,
The asterisk indicates that Q1 or Q2 may be either "1" or "0".

The outputs Q1 to Q5 of the D-type flip-flops 5 to 13 other than the six cases shown in FIG.
In the combination, the normal judgment is performed, and the select signals SEL1 and SEL2 are both set to "1" which is a steady value.

With the above configuration, the input data is sequentially taken into the D-type flip-flop 5 of the first bit of the synchronous shift register 15 in synchronization with the clock signal.
"Q" of each output Q1 to Q5 of the D-type flip-flops 5 to 13
If the combination of 1 "and" 0 "is other than the six cases as shown in FIG. 3, it is determined that the input data contains no noise component, and both the select signals SEL1 and SEL2 are steady values." 1 ", so that the input data remains unchanged as the most significant bit D of the synchronous shift register 15.
The output from the type flip-flop 13 is performed.

On the other hand, D-type flip-flops 5 to 1
In the case where the combination of "1" and "0" of the outputs Q1 to Q5 of FIG. 3 fits any of the six cases shown in FIG.
Assuming that a noise component is included in the input data, the select signal SEL2 is set to "" according to the rule shown in FIG.
The signal is switched from "1" to "0" and the select signal SE
L2 is selectively switched from "1" to "0".

As a result, as shown in FIGS. 4A to 4H, the output data taken out of the D-type flip-flop 13 of the most significant bit of the synchronous shift register 15 is output from the synchronous shift register 15. D of the first bit
The input data input to the type flip-flop 5 is compensated to remove noise components.

The rules shown in FIG. 3 are found from empirical values and the like, and may be arbitrarily set to suit each digital data transmission system.

[0028]

As can be understood from the above description, according to the digital signal noise component removing apparatus according to the present invention,
The digital signal is divided by the synchronous shift register according to the clock frequency and latched in time series by the number corresponding to the number of bits of the synchronous shift register, and the switching circuit outputs an output signal of each bit of the synchronous shift register. Control the operation of the signal inverting circuit based on the combination of, the signal inverting circuit selectively inverts the input signal of a predetermined bit of the synchronous shift register for noise component removal,
The occurrence of noise components such as pulse cracks is detected with high certainty, and based on this, noise components such as pulse cracks are automatically and appropriately eliminated, whereby the rising edge and falling edge of the digital signal can be reliably recognized. And reliable and high quality digital data transmission can be performed.

This digital signal noise component elimination device can be constituted only by a synchronous shift register and a logic circuit, whereby the noise component elimination device can be easily incorporated into an LSI or the like. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a digital signal noise component removing apparatus according to the present invention.

FIG. 2 is a block diagram showing one embodiment of a detailed configuration of a digital signal noise component elimination device according to the present invention.

FIG. 3 is a table showing an example of a select signal output rule of a multiplexer in the digital signal noise component elimination device according to the present invention.

FIGS. 4A to 4H are signal waveform diagrams each showing an example of correcting output data with respect to input data.

[Explanation of symbols]

 Reference Signs List 1 input data sampling circuit 3 switching circuit 5 D-type flip-flop 7 D-type flip-flop 9 D-type flip-flop 11 D-type flip-flop 13 D-type flip-flop 15 Synchronous shift register 17 Multiplexer 19 Multiplexer

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 25/08

Claims (1)

(57) [Claims] (1) a frequency greater than a clock frequency of a digital signal;
In synchronization with the sampling clock of the threshold frequency,
A synchronous shift register having a predetermined number of bits to be sequentially inputted by dividing the digital signal, a signal of a predetermined bit of said synchronous shift register latch
A signal inverting circuit for selectively inverting each bit, and a signal of each bit input to the synchronous shift register.
And a switching circuit for controlling the operation of the signal inverting circuit based on a combination of “1” and “0” of the input signal. Component removal device.