KR100393621B1 - Apparatus and method for immunities in a data receiver - Google Patents

Abstract

The present invention relates to an apparatus and method for removing noise induced in a received signal from a transmitter in a data receiver. The present invention monitors a received signal using a reference clock and outputs the same value if the same value is received for a predetermined period. If this is not received, the noise canceller and the method of outputting the same value as the previous output value can be implemented, thereby increasing the reliability of the transmitted signal.

Description

Noise canceling device and method in data receiver {APPARATUS AND METHOD FOR IMMUNITIES IN A DATA RECEIVER}

The present invention relates to a data receiving apparatus and method, and more particularly, to an apparatus and method for removing noise induced by a signal on a transmission path.

In general, in order to transmit and receive signals between two different devices, a transmitter for transmitting a signal through a predetermined transmission path and a receiver for receiving the signal are required. One of the most important considerations for such a transmitter and a receiver is that noise is affected while a predetermined signal is transmitted through a transmission path.

1 is a diagram showing an example of a typical transmission system configuration. As shown in FIG. 1, a typical transmission system has a structure in which a transmitter 110 and a receiver 120 are connected through a predetermined transmission path 130. The predetermined transmission path 130 may be largely a cable network, a telephone network, or the like, and may be implemented by various media such as a bus connecting a board or a PBA.

The transmission system shown in FIG. 1 transmits data to be transmitted from the transmitter 110 to a predetermined transmission path 130 in synchronization with a frame sync signal (FS) and a clock (Clock). An example of transmitting data in synchronization with the FS and a clock is shown in FIG. 2. As shown in FIG. 2, the data is transmitted by the FS at the start of a new frame, and the data is transmitted according to the clock. Meanwhile, the receiver 120 receiving the data through the predetermined transmission path 130 receives the data using the FS and the clock.

In the case of the data transmitter and the receiver having the structure as described above, not only the data but also the FS and the clock also cause noise due to noise induced in the transmission path or signal characteristics such as chattering when transmitting signals between TTLs. This can happen.

Due to these problems, various methods have been studied to improve data reliability by preventing data errors due to noise induced unexpectedly in the transmission path.

A representative example of such methods is signal transmission by a non retune to zero (NRZ) method. The NRZ method is a method of transmitting data using +1 and -1, and may be referred to as a method of minimizing an influence from noise. As another example, there is a signal transmission method using a differential signal. The signal transmission method using the differential signal is a method of transmitting a signal of one bit as a positive signal and a negative signal, and the receiver recovers the bit by the difference between the positive signal and the negative signal. That is, when the receiver receives the differential signal, it is determined to be +1 if the difference between the positive signal and the negative signal of the differential signal is positive, and -1 if it is negative.

However, the above-described methods are not only completely resistant to noise but are more resistant to noise than other transmission methods. Therefore, if noise is induced in a signal transmitted by the above-described scheme, the receiver may not know whether the noise is induced and not remove the noise. If noise is induced in the FS in transmitting data by the above-described method, frame synchronization is broken, and data corresponding to one frame may be corrupted or lost. In addition, when noise is induced in the CLK, synchronization with the data is shifted, which causes problems such as data being transmitted in the wrong order. Similarly, error data is received even when noise is induced in the data. This is a fatal cause of the receiver's inability to recover the original signal, resulting in system degradation.

Accordingly, an object of the present invention for solving the above problems is to provide a noise removing device and method for improving reliability by removing noise components included in a received signal.

Another object of the present invention is to provide a noise canceling apparatus and method for removing noise generated during signal transmission in a receiver.

In a first aspect for achieving the above object, the present invention provides a noise canceling apparatus of a receiver for receiving a signal transmitted from a transmitter through a predetermined transmission medium, and removing the noise induced in the received signal, A first delay flip-flop for inputting the received signal and a reference clock having a higher frequency than a clock used in the transmitter, and latching the received signal by the reference clock; A buffer for storing a bit latched within the predetermined size, an input of the bits stored in the buffer, and an NOR gate for performing an AND operation on the bits, and stored in the buffer. An OR gate for inputting the existing bits, and performing an OR operation on the bits; And a second delayed flip-flop for latching an output signal fed back by inputting the output from the negative AND gate as the input of the preset stage and the output from the OR gate as the input of the reset stage. .

In a second aspect for achieving the above object, the present invention provides a noise reduction method of a receiver for receiving a signal transmitted from a transmitter through a predetermined transmission medium, and removing the noise induced in the received signal, Latching the received signal by a reference clock having a higher frequency than a clock used in the transmitter and storing the received signal in a buffer having a predetermined size, and when all bits stored in the buffer have a bit value of 1 Outputting 1 as a removed bit value, outputting 0 as the noise-removed bit value when all bits stored in the buffer have a bit value of 0, and bits stored in the buffer And outputting previously output bit values when the values have different values.

1 is a diagram showing the configuration of a typical data transmission / reception system.

2 illustrates a transmission signal between the transmitter and the receiver of FIG.

3 is a diagram illustrating a configuration of a data transmission / reception apparatus according to an embodiment of the present invention.

4 is a diagram illustrating a detailed configuration of an apparatus for removing noise constituting a receiver according to an embodiment of the present invention.

5 is a view showing an operation example of the noise removing device of FIG.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating a configuration of a data transmission / reception system according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the transmitter 310 transmits the frame sync signal FS, the clock CLK, and data through separate paths. Reference numeral 330 denotes a transmission medium for transmitting FS, CLK, and data between the transmitter 310 and the receiver 320. If the transmitter 310 and the receiver 320 are provided in one device such as a board or a PBA, the transmission medium 330 may be a ribbon cable or the like, and the transmitter 310 and the receiver 320 may be separated. When present as a device, the transmission medium 330 may be a communication network such as a telephone network, a cable network, or the like. The receiver 310 receives FS and CLK and data through the transmission medium 330, and receives data by the FS and CLK. In this case, the noise canceller 322 is provided inside the receiver 320 to remove the noise induced in the received FS, CLK, and data using a reference clock REF_CLK, which is its own clock. FS_O), the noise-free CLK (CLK_O), and the noise-free data DATA_O are output. In this case, the REF_CLK should have a higher rate than the CLK provided from the transmitter 310.

FIG. 4 is a view illustrating only a part of the noise canceller 322 provided in the receiver 320 shown in FIG. 5 and removes only the noise induced in the FS among the components of the noise canceller 322. It is shown. The configuration for removing noise induced in CLK and the configuration for removing noise induced in data are not the same as those shown in FIG. Therefore, the detailed description according to the embodiment of the present invention described below replaces the configuration and operation corresponding to the CLK and data by explaining the configuration and operation of removing the noise induced in the FS with reference to FIG. 4.

Referring to FIG. 4, the delay flip-flop (D F / F) 410 is provided with FS as an input and a reference clock REF_CLK is provided as a clock to output a predetermined signal. That is, the D F / F 410 latches the input signal FS at every rising edge of the REF_CLK. For this purpose, a clock having a rate of at least 10 times higher than the signal transmission rate is used as the REF_CLK used to latch the input signal FS. If the rate of the REF_CLK is too large compared to the signal transmission rate, the output may have a low delay. However, if the duty of the noise component is large, the number of bits that can be stored by the buffer 412 to be described later should increase.

The buffer 412 stores a predetermined signal output from the D F / F 410 in units of bits. In this case, the buffer 412 has a predetermined length n as a first-in first-out (FIFO). That is, the bits provided from the D F / F 410 are shifted and stored one bit from the lower bit to the higher bit by the buffer 412. The predetermined length n determines the number of bits that can be stored in the buffer 412. In this case, the predetermined length n may be determined by the duty of the noise component and the frequency of REF_CLK. For example, when the duty of the noise component is large and the frequency of the REF_CLK is large, the number of ns, that is, the number of bits that the buffer 412 can store, needs to be large to remove the noise component. Therefore, the values of the REF_CLK and the n must be adjusted to properly remove noise components within a range in which cost increases in terms of systems. 4 illustrates a case where n of the buffer 412 is set to 5, the buffer 412 can store the signal provided from the D F / F 410 in 5 units.

The noise detector 420 compares the bits stored in the buffer 412 to check whether noise is induced, and then outputs the test result. The noise detector 420 checks whether the NANDgate 414 checks whether all the bits stored in the buffer 412 are "1" and the logical sum checks whether all the bits stored in the buffer are "0". OR gate 416.

The NAND gate 414 inputs each of the bits stored in the buffer 412 and presets the result of the negative AND of the bits in the delay flip-flop (DF / F) 418. (Hereinafter referred to as "/ PRE"). The NAND gate 414 outputs "0" only if all inputs are "1" and outputs "1" for all other combinations of inputs. Accordingly, the NAND gate 414 outputs "0" only when all of the bits Q0 to Q4 stored by the buffer 412 have a value of "1".

The OR gate 416 inputs each of the bits stored in the buffer 412, and resets the result of the OR of the delay flip-flop (DF / F) 418. "/ RST"). The OR gate 416 outputs "1" when any one of all inputs is "1" and outputs "0" only when all inputs are "0". Accordingly, the OR gate 416 outputs "0" only when all of the bits Q0 to Q4 stored by the buffer 412 have a value of "0".

The D F / F 418 outputs a predetermined bit value by / PRE and / RST provided from the NAND gate 414 and the OR gate 416. The output Q of the D F / F 418 is a frame synchronization signal FS_O from which noise is removed. The truth table showing the output Q of the D F / F 418 by the / PRE and the / RST is shown in Table 1 below.

/ PRE / RST D Q L H x One H L x 0 H H 0 0 H H One One

In Table 1, the / PRE and the / RST are described as "L", "H" but this should be interpreted as the same meaning as "0", "1" described above.

In the operation of the DF / F 418 according to the truth table of Table 1, if "L" is output from the NAND gate 414, the DF / F 418 outputs "1". When "L" is output from the OR gate 416, the DF / F 418 outputs "0". In addition, when "H" is output from the NAND gate 414 and the OR gate 416, the previous value is maintained. That is, when the previous output is "0", "0" is output, and when the previous value is "1", "1" is output. The output of “H” from the NAND gate 414 and the OR gate 416 is when bit values stored in the buffer 412 are stored with different values.

FIG. 5 is a timing diagram illustrating an example of an operation in which noise is removed by the noise removing device 322 shown in FIG. 4.

In FIG. 5, (a) shows a normal FS, and (b) shows an FS having a noise component in some sections. 5, (c) shows a reference clock REF_CLK, and (d) shows examples of bits stored in the buffer 412. Finally, (d) of FIG. 5 shows FS_O from which noise components are removed.

Hereinafter, an operation according to an exemplary embodiment of the present invention will be described in detail with reference to the above-described drawings. First, the operation of the present invention to be described below will be described in advance with reference to the timing diagram showing an example of the operation of the noise canceling device 322 in FIG. In addition, the operation of the noise removing device 322 according to the embodiment of the present invention can be largely divided into three. The first operation is when the values stored in the internal buffer all have "1", the second operation is when the values stored in the internal buffer all have "0", and finally The third operation is when the value stored in the internal buffer is mixed with "1" and "0". Operation according to an embodiment of the present invention to be described later will be described by separating the above three operations.

1. If all the values stored in the internal buffer have "1"

The DF / F 410 latches the high value by REF_CLK in the high section until the falling edge 510 of the FS including the noise component shown in FIG. Output 1 ". As a result, the buffer 412 is filled with bits having a value of "1" sequentially output from the D F / F 410. This corresponds to examples of the uppermost (reference number 516) and the lowermost (reference number 524) among the examples shown in (d) of FIG. When "1" is stored in five bits that can be stored in the buffer 415 by the above-described operation, that is, when the value stored in the buffer 415 is "11111", the NAND gate 414 having the input thereof is "0". Outputs " Since “0” output from the NAND gate 414 is input to / PRE of the D F / F 418, the D F / F 418 outputs “1”. At this time, as the OR gate 416 outputs "1", it does not affect the output of the D F / F 418.

2. The value stored in the internal buffer is mixed with "1" and "0".

At 510, the FS is falling edge to start the low section. When the row period of the reference number 510 starts, the D F / F 410 latches the bit value "0" by the REF_CLK. Thus, the least significant bit of the buffer 412 will be stored as "0". That is, "11110" is stored in the buffer 412. In this case, both the NAND gate 414 and the OR gate 416 output “1”, and the outputs of each of the NAND gate 414 and the OR gate 416 are input to / PRE and / RST. The DF / F 418 outputs "1" which is a previously output value.

On the other hand, at the reference numeral 514, the FS is a rising edge to start the high section. When the high section of the reference number 514 starts, the D F / F 410 continuously outputs "0" and latches the bit value "1" by the REF_CLK. Thus, the least significant bit of the buffer 412 will be stored as "1". That is, "00001" is stored in the buffer 412. In this case, both the NAND gate 414 and the OR gate 416 output “1”, and the outputs of each of the NAND gate 414 and the OR gate 416 are input to / PRE and / RST. The DF / F 418 outputs "0" which is a previously output value.

As described above, the state in which the value stored in the buffer 412 is mixed with "1" and "0" may occur at the reference numeral 510 and the reference numeral 514 or the noise induced reference numeral 512. That is, the state where the value stored in the buffer 412 is mixed with "1" and "0" occurs at the point where the level of the FS changes. The state in which the reference numeral 510 is mixed with "1" and "0" in reference numeral 514 may be referred to as a transition state in which the FS changes. Thus, the mixed state of "1" and "0" is maintained until all bits of the buffer 412 are filled with "1" or "0". Therefore, the DF / F 418 outputs the previously output value until all the bits of the buffer 412 are filled with " 1 " or " 0 " Even if it is changed, the noise-free FS_O is output from the DF / F 418. However, the operation according to the induced noise shown at 512 is limited for the duration of the induced noise.

3. If all the values stored in the internal buffer have "0"

As the low section starts due to the falling edge of the FS at point 510, when the operation according to the state where "1" and "0" are mixed a predetermined number (five times) is performed, All five bits are filled with "0". This corresponds to reference numeral 518 in the examples shown in FIG. When "0" is stored in five bits that can be stored in the buffer 415 by the above-described operation, that is, when the value stored in the buffer 415 is "00000", the OR gate 416 having an input thereof is "0". Outputs " Since "0" output from the OR gate 414 is input to / RST of the D F / F 418, the D F / F 418 outputs "0". At this time, as the NAND gate 414 outputs "1", the NAND gate 414 has no influence on the output of the D F / F 418.

Values output from each configuration according to the above three operations are as shown in Table 2 below.

.... t1 t2 .... t3 t4 t5 t6 t7 t8 t9 .... t10 t11 FS x 0 0 0 One One 0 0 0 0 0 x One One FS_REG xxxxx 10000 00000 00000 00001 00011 00110 01100 11000 10000 00000 xxxxx 01111 11111 NAND One One One One One One One One One One One One One 0 OR One One 0 0 One One One One One One 0 0 One One / PRE One One One One One One One One One One One One One 0 / RST One One 0 0 One One One One One One 0 0 One One FS_O One One 0 0 0 0 0 0 0 0 0 0 0 One

In Table 2, all the values stored in the buffer 412 have "1" as t11, and all the values stored in the buffer 412 have "0" as t2 and t9. . On the other hand, when the values stored in the buffer 412 are mixed with "1" and "0", they are shown as t1, t3, t4, t5, t6, t7, t8 and t10. However, in the case where the value stored in the buffer 412 is mixed with "1" and "0", the noise removing device 322 performs the same operation but may be classified into two types in its meaning. One of the two cases is when the received signal level before and after the above-described operation is the same due to the induction of noise, and the other is the received signal level before and after the above-described operation is changed If it is. According to an embodiment of the present invention, the first case is a case in which "1" and "0" are mixed due to noise induced in a received signal as the period between t3 and t8. In this case, the D F / F 418 continuously outputs "0" regardless of noise as the previous output is maintained as it is. However, since the duty of the induced noise is long, the noise becomes impossible when all bits of the buffer 412 are filled with "1" due to the noise. Therefore, the size of the buffer 412 should be determined in consideration of the duty maximum of noise that can be induced.

Meanwhile, in the above-described operation description, FS is the object, but it is obvious that all of the received signals such as clock and data received from the transmitter can be implemented by applying the same technique as described above.

As described above, the present invention has the effect of performing reliable data transmission without incurring additional costs for improving the quality of the transmission medium by removing noise induced in the received signal at the receiver.

Claims (10)

In the noise removing device of the receiver for receiving a signal transmitted from the transmitter through a predetermined transmission medium, and removes the noise induced in the received signal, A first delay flip-flop for inputting the received signal and a reference clock having a higher frequency than the clock used in the transmitter, and latching the received signal by the reference clock; A buffer having a predetermined size and storing bits sequentially latched from the delay flip flop within the predetermined size; A negative AND gate for inputting the bits stored in the buffer and performing a negative AND operation on the bits; An OR gate for inputting the bits stored in the buffer and performing an OR operation on the bits; And a second delayed flip-flop for latching an output signal fed back by inputting an output from the negative AND gate as an input of a preset stage and an output from the OR gate as an input of a reset stage. Said device. The method of claim 1, Wherein the reference clock has a frequency 10 times higher than the frequency of the clock used in the transmitter. The method of claim 1, The predetermined size of the buffer is determined by the maximum duty of the noise induced in the received signal and the frequency of the reference clock. The method of claim 1, wherein the second delay flip flop, Outputs 1 when the output from the negative AND gate is low, outputs 0 when the output from the AND gate is low, and both the output from the AND gate and the output from the AND gate are high. And latching the output signal inputted to the feed back. A noise reduction method of a receiver for receiving a signal transmitted from a transmitter through a predetermined transmission medium, and removing the noise induced in the received signal, Latching the received signal by a reference clock having a higher frequency than a clock used in the transmitter and storing the received signal in a buffer having a predetermined size; Outputting a 1 as a noise-removed bit value when all bits stored in the buffer have a bit value of 1; Outputting 0 as the noise-free bit value when all bits stored in the buffer have a bit value of 0; And outputting a previously output bit value when the bit value is different between the bits stored in the buffer. The method of claim 5, The reference clock has a frequency 10 times higher than a frequency of a clock used in the transmitter. The method of claim 5, The predetermined size of the buffer is determined by the maximum duty of the noise induced in the received signal and the frequency of the reference clock. The method of claim 5, And determining whether all bits stored in the buffer have a bit value of 1 by a negative AND operation of the bits stored in the buffer. The method of claim 5, And determining whether all of the bits stored in the buffer have a bit value of zero by an OR operation of the bits stored in the buffer. 6. The method of claim 5, wherein the bits stored in the buffer are different from each other unless all of the bits stored in the buffer by an AND operation and the OR operation of the bits stored in the buffer are not 1 or all 0s. The method as claimed in claim 1 characterized in that it has.