JPS61145945A - Digital signal receiver - Google Patents

Abstract

PURPOSE:To decrease remarkably code errors due to noise by generating plural clocks during one clock of a digital reproducing signal, using the clock to sample the digital reproducing signal and waveform-shape and using a binary value having the most value among n sets of sample values during one bit period as the value of the said one bit period. CONSTITUTION:A clock reproducing PLL2 reproduces a clock of a frequency n.fr phase-locked to a digital reproducing signal, where fr is a frequency of the basic clock of the digital reproducing signal and the clock is fed to a sift register 1. The shift register 4 uses the clock of frequency nfr, samples sequentially n values in one clock period of the signal and transmits the result sequentially. Then the sampled and stored values are transmitted to a majority decision circuit 3. The circuit 3 outputs 0 when 0s are more in the transmitted n-sample and outputs 1 when 1s are more. Thus, n-sample is obtained during one clock of the digital reproducing signal. When the noise width during one clock is [n/2]/n clock width or below, no code error takes place.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal receiving apparatus that receives a noisy digital signal sent through a communication channel, shapes the waveform, and sends it out again.

BACKGROUND OF THE INVENTION FIG. 4 is a block diagram showing the configuration of a recording/reproducing system generally used when performing high-density digital recording. Using this diagram, an outline of digital signal recording will first be explained.

Digital data generated in the recording system 7 in FIG. 4 is recorded onto a recording medium 9 through a recording head 8.

On the other hand, during reproduction, a reproduction signal obtained through the reproduction head 1o (which may be shared with the recording head 8) is sent to an equalizer 11 in order to suppress the influence of waveform interference.

The output from the equalizer 11 is sent to a quantizer 12, where the reproduced signal is converted into a binary digital reproduced signal.

The converted digital reproduction signal is then sent to the clock reproduction PLL 13. The clock regeneration PLL 13 regenerates a clock synchronized in phase and frequency with the input digital reproduction signal and sends this clock to the receiver 14.

The receiver 14 shapes the waveform of the digital reproduction signal from the quantizer 12 in units of clocks using the clock from the clock reproduction PLL 13, and then sends it to the subsequent reproduction thread 15.

The above is an overview of the digital signal recording/reproducing thread.

Incidentally, in the process of reproducing digital signals recorded at high density, code errors occur without exception due to added noise. Furthermore, as the recording density increases, the frequency with which code errors occur increases.

Therefore, in high-density digital recording systems, an error correction code is always added to correct code errors, but the rate is almost proportional to the high code error rate.
The circuit scale for error correction becomes large.

Conversely, if the code error rate can be lowered, the circuit size for error correction can be reduced, or if the circuit size is the same, the probability of uncorrectable code errors will be reduced, and the code error rate after error correction can be further reduced. Can be made smaller.

For this reason, various efforts have been made to improve the performance of recording media, heads, and equalizers and to keep the bit error rate low, but all of these efforts are ineffective in reducing the effective value of noise. .

Problems to be Solved by the Invention As shown above, code errors are caused by noise in the reproduction process. However, noise does not necessarily result in code errors. For example, if the noise level is sufficiently low or occurs in a location where it does not cause code errors.

The problem of noise level is excluded from the scope of the present invention, and
Limited to only the location where the error occurred.

By the way, the influence of noise in the reproduction process only appears as a clear code error in the output of the receiver shown in FIG. 4, which shapes the waveform of the digital reproduction signal in units of clocks and sends it out.

This is because the basic unit in digital signal processing is 1
It is the clock that distinguishes one bit from another. Therefore, a code error refers to a phenomenon in which the reproduced value of a given hit is not equal to the value when it was recorded. This is because it is not possible to tell whether a code error has occurred until after the bits have been distinguished.

As just shown, code errors occur after the digitally reproduced signal is processed in units of one clock.The width of the noise that causes these code errors is a major factor, but its location is also important. be.

For example, as shown in Figure 6, even if the width of the noise in the digital reproduction signal is constant (less than half of one clock period), the difference in (1) depends on the position (rising edge) of the clock from the clock reproduction PLL and the position of the noise. If the value is displayed, a code error may occur, or a normal value may be obtained as shown in (11).

Since the position of the noise can be anywhere, the same phenomenon will always occur even if the position of the recovered clock is shifted.

This means that the clock used for waveform shaping in the receiver is
This is a problem that cannot be solved with the conventional structure of a receiver or clock recovery PLL, which only has one per clock of the digital reproduction signal.

Means for Solving the Problems In order to solve the above problems, the present invention generates a plurality of clocks between one clock of the digital reproduction signal, samples the digital reproduction signal using these clocks, and calculates the sample value. It is equipped with a configuration that shapes the waveform of the digital reproduction signal in units of 1 bit using the
The present invention is characterized by a structure in which the larger binary value among the sample values is taken as the value for that 1-bit period, and the width of that value is made to be the width between clocks.

Effects According to the above configuration, if the width of the noise signal is less than half the width between clocks, correct values can be reproduced and code errors can be eliminated. Furthermore, since noise has a relatively narrow width, the above configuration can greatly reduce code errors.

Example The configuration of an embodiment of the present invention will be explained using FIG. 1.

This embodiment has an n-stage shift register 1, a clock recovery PLL 2, and a majority circuit 3, as shown in FIG.

In FIG. 1, if the frequency of the basic clock of the digital reproduction signal is fr, the clock reproduction PLL 2 has a frequency n − ff that is phase-locked to the digital reproduction signal.
, and transfer this clock to shift register 1.
send to However, the L, n)3° shift register 1 sequentially samples n values within an interval corresponding to one clock of the digital reproduction signal using a clock having a frequency of nfr, and sequentially sends them.

The sampled and held values are sent to the majority circuit 3. The majority circuit 3 selects 0 out of the n samples sent.
If there are many 0.1, the output is 1. Note that this output is sent from the clock recovery PLL2, nfr
is transmitted as a clock whose frequency is divided by n, that is, a clock with a frequency fr.

Note that n may be an even number, but considering the efficiency of majority voting,
It is better to choose an odd number for n.

By doing this, one chronograph error in the digital reproduction signal does not occur. However, [.] is a Gagara symbol and represents the largest integer that does not exceed the value in [].

Usually, the width of so-called random noise is relatively small, so
According to the present invention, code errors can be reduced.

Next, the present invention will be explained in more detail.

In this embodiment, the case where n=3 will be specifically explained. In this case, the shift register 1 in FIG. 1 has three stages, and the recovered clock frequency of the clock recovery PLL is 3f.
r, the majority circuit 3 outputs the output values (binary values) of each stage of the shift register 1 as A and B.

and C, it becomes a circuit that performs the logical operation M・B+B −C+C−A and sends out the result with the clock fr. However, "pa" represents a logical product, and "+" represents a logical sum.

For example, the shift register 1 and majority circuit 3 in FIG. 1 have a configuration as shown in FIG. 2 in this embodiment.

The shift register 1 in FIG. 2 is the same as the shift register 1 in FIG. 1, and has three stages.

The outputs A, B and C of are sent to three two-man AND gates,
Send the two together. As a result, “A-
B, B-C and ch are obtained. Furthermore, OR-gate 6 is operated by three people to calculate the logical sum of these 13 logical products.
It is. The output of the three-man OR gate includes the majority vote,
In other words, A −B+B −G+C−A appears.
However, since the output of the OR gate 5 is maintained for and '/sfr seconds, the D flip-flop 6 converts the value for Vs fr seconds to the value for '/fr seconds, that is, 1 bit length. Send it off with a beat. (Figure 3 is a time chart of the circuit operation just shown (and the third
Each symbol in the figure corresponds by one to that in Figure 2.

The noise width in FIG. 3 is exactly 115 clock widths, so no code error occurs no matter where this noise is present.

As shown above, this embodiment simply adds a three-stage shift register, three two-man powered AND gates, and one three-man powered OR gate, and triples the regenerated clock frequency of the clock regenerated PLL. This has a great practical effect in that it is possible to remove the noise engraving that would conventionally cause code errors, and therefore to reduce the number of code errors.

Effects of the Invention The present invention sets the frequency of the recovered clock of the clock recovery PLL to 1 times the fundamental frequency fr of the digital reproduction signal, that is, nfr, and uses this clock to generate a signal corresponding to one clock (fr) in the digital reproduction signal. By taking n samples within an interval and using the majority value in these samples to directly represent the entire interval, noise of less than (2) 'n clock width, which would conventionally result in code errors, can be eliminated. However, code error 9 can be prevented from occurring.

This shows that the code error rate can be lowered, and
The practical effects of the present invention are extremely large because the circuit scale for realizing the present invention can be extremely small.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, FIG. 2 is a circuit diagram of the majority circuit in the embodiment, FIG. 3 is a time chart of the shift register and majority circuit in the embodiment, and FIG. 4 is a conventional digital signal FIG. 6, a block diagram of a recording/reproducing thread, is a diagram showing whether or not a code error occurs due to the positional relationship between noise and clock in a conventional receiver. 1...Shift register, 2...Clock regeneration PLL, 3...Majority circuit, 4...
...AND gate, 5...OR gate, 6.
...D flip-flop. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure fr Figure 3

Claims (2)

[Claims] (1) In a digital signal receiving device that shapes the waveform of a digital reproduced signal sent through a communication path in units of the basic clock f_r of the digital reproduced signal and retransmits it, the digital reproduced signal a clock reproducing means for regenerating clocks of frequencies nf_r and f_r phase-locked to the nf_r clock; n samples are taken within one bit period of the digitally reproduced signal by the nf_r clock, and the larger of the n sample values is 2
1. A digital signal receiving apparatus comprising: majority deciding means for determining the decimal value as a value for this 1-bit period; and means for converting the value obtained by the majority deciding means into a width of 1/f_r. (2) The digital signal receiving device according to claim 1, wherein n is an odd number.