JP4358966B2 - Reference clock generation circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a reference clock generation circuit that generates a reference clock from input data subjected to biphase mark (referred to as biphase) modulation.
[0002]
[Prior art]
In digital audio data, biphase mark modulation is used to indicate values of “0” and “1”.
[0003]
In the biphase modulation, each bit is expressed by two symbols, the bit “0” is expressed by a combination of symbols (00) or (11), and the bit “1” is expressed by a combination of symbols (01) or (10). The rule is that the preceding symbol of the two symbols representing one bit is different from the subsequent symbol of the immediately preceding bit. Therefore, which of the two representations is selected for each bit depends on whether the symbol after the immediately preceding bit is 0 or 1.
[0004]
FIG. 5 shows an example of biphase modulation. Thus, the 1-bit “1” and “0” signals as shown in the upper row are converted into data representing 1 bit with two symbols as shown in the lower row.
[0005]
By using such bi-phase modulation, 0 and 1 exist equally, so that the DC component of the transmission line can be reduced. In addition, since there is always a rise and a fall for each bit, clock recovery from data is facilitated. Furthermore, since the data is independent of its polarity, the data can be maintained even if the signal is inverted.
[0006]
Here, in the digital audio interface, a reference clock is generated from the biphase modulation data, and this is supplied as a reference clock to a PLL (Phase Locked Loop).
[0007]
FIG. 6 shows a procedure for generating the PLL reference clock from the biphase modulation data. First, first half and second half symbol values are detected for 1-bit data of biphase modulation data. When the pattern (11) representing the bit “0” is detected, an inverted signal of the input data is transmitted to the subsequent stage thereafter. When the pattern (11) (original data is (00)) comes again, the inversion of the input data so far (actually the input data remains) is transmitted to the subsequent stage. Thus, by inverting in the middle of the subsequent symbol in the case of (11), a rising edge always comes between the bits of the signal waveform transmitted to the subsequent stage. Therefore, this signal is used as a PLL reference clock, and the rising edge is used as a trigger to reproduce the clock in the PLL.
[0008]
FIG. 7 is a diagram showing an example of a circuit for creating such a reference clock. Input data is supplied to the data inversion control circuit 1. When the data inversion control circuit 1 detects (11) of the input data, it inverts the outputs 1 and 0. The output of the data inversion control circuit 1 is input to the exclusive OR circuit 2 together with the input data. Therefore, the input data is output as it is when the output of the data inversion control circuit 1 is 0, and is inverted when it is 1. Therefore, every time the data inversion control circuit 1 detects (11), the input data is inverted after that time and output from the exclusive OR circuit 2.
[0009]
In this way, in the conventional circuit, the reference clock is regenerated from the input data subjected to biphase modulation.
[0010]
[Problems to be solved by the invention]
However, when data is damaged due to noise on the transmission path, an error is included in the input data. This is recognized as a parity error and can be corrected as long as it is within an allowable range in the specification of the logic circuit.
[0011]
On the other hand, if there is an error in the input data, the bi-phase modulation rules are broken, so that the reference clock that is faithfully generated from the input data is properly affected.
[0012]
That is, as shown in FIG. 8, when the portion of the input data that should originally be 0 becomes 1 due to damage, the bit that becomes (11) after inversion becomes (01), and the inversion does not occur. Since this is not performed, the portion of the inverted signal that should originally rise may change to a fall. Thereby, the phase of the reference clock remains shifted until the next (11) comes.
[0013]
For this reason, there is a possibility that a large phase shift occurs in the reference clock and the PLL is immediately unlocked. In this case, according to the specification of the logic circuit, the synchronization preamble that should exist periodically cannot be detected, and this is regarded as illegal input data, and data cannot actually be reproduced.
[0014]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a reference clock generation circuit that can stably generate a reference clock from biphase-modulated input data.
[0015]
[Means for Solving the Problems]
The present invention relates to a reference clock generation circuit that generates a reference clock from input data that has been subjected to biphase mark modulation, a synchronization detection circuit that performs synchronization detection on input data that has been biphase modulated and detects a bit boundary; A correction circuit that corrects the input data when the bi-phase rule is violated based on the values of the input data before and after the bit boundary detected by the synchronization detection circuit, and the data corrected by the correction circuit Based on this, a reference clock is generated.
[0016]
As described above, when an input including data deviating from the biphase modulation rule generated due to damage in the transmission path is made, the corresponding part is corrected and replaced with data according to the biphase modulation rule. Thereby, the disturbance of the reference clock generated from the input data can be suppressed.
[0017]
The correction circuit preferably corrects the input data with a value corresponding to inversion of the input data at that time when the values of the input data before and after the bit boundary are not different.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.
[0019]
FIG. 1 is a circuit block diagram of the present invention. First, input data is input to the synchronization detection circuit 10. The synchronization detection circuit 10 buffers the input data by a predetermined amount and checks the buffered input data pattern. Then, a synchronization preamble in the input data is detected, and a synchronization preamble detection flag is output. This synchronization preamble detection flag is output only once per subframe (each time a synchronization preamble is detected), and based on this, a bit boundary is specified.
[0020]
The output signal of the synchronization detection circuit 10 is supplied to the correction pseudo data generation circuit 12. Input data is also supplied to the correction pseudo data generation circuit 12, and the correction pseudo data generation circuit 12 checks symbols before and after the bit boundary of the input data. In this result, if the state of both symbols is different, it is normal data. On the other hand, if the two symbols are in the same state, the data violates the bi-phase data modulation rule and needs to be replaced with pseudo data.
[0021]
Therefore, the correction pseudo data generation circuit 12 generates and outputs data that is inverted with respect to the immediately preceding symbol.
[0022]
The pseudo data that is the output of the correction pseudo data generation circuit 12 is supplied to the multiplexer circuit 14. The multiplexer circuit 14 also receives input data, and selects and outputs either pseudo data or input data from the correction pseudo data generation circuit 12. The selection switching in the multiplexer circuit 14 is controlled so that pseudo data is selected in the case of the preceding symbol and input data is selected in the case of the subsequent symbol. Therefore, pseudo data that is inverted with respect to the subsequent symbol of the previous bit is generated in the period of the previous symbol of the bit at the bit boundary, and the bi-phase modulation rule is observed at the output of the multiplexer circuit 14. A signal is obtained.
[0023]
Here, the data obtained by the replacement with the pseudo data is not necessarily the same as the input data in the correct state without being damaged. However, in reproducing the reference clock, the data contents do not have to be correct, and data for reproducing the reference clock can be obtained by such replacement with pseudo data.
[0024]
The data corrected by the pseudo data is supplied to the data inversion control circuit 16. This data inversion control circuit is the same as that in FIG. 7 described above, and inverts the output signal in the middle of 1 of the symbol (at the time of 1/2 cycle) every time (11) which is data indicating 0 is received. Invert the output to The output of the data inversion control circuit 16 is supplied to the exclusive OR circuit 18. The exclusive OR circuit 18 is supplied with the corrected input data which is the output of the multiplexer circuit 14, so that every time the bit of (11) comes, the data is inverted from the time of 1/2 of the symbol thereafter. This is output from the exclusive OR circuit 18.
[0025]
Accordingly, when a symbol after a combination of symbols representing “0” is detected again, the signal inversion status changes after ½ cycle, and the exclusive OR circuit 18 inverts and transmits the corrected data each time.
[0026]
As described above, the generated signal has a clock waveform with a constant frequency that always has a rising edge at the bit boundary. This clock is used as a reference clock to the PLL.
[0027]
FIG. 2 is a diagram illustrating a configuration of the correction pseudo data generation circuit 12. The input data is input to the data input terminal of the flip-flop 22, and the clock input terminal of the flip-flop 22 is input with FS128 which is a clock having a period corresponding to one symbol as one cycle. The FS 128 is a clock that rises at a timing slightly delayed from the bit boundary of the input data. Therefore, the state of each symbol of the input data is taken into this flip-flop 22. The Q output of the flip-flop 22 is input to the data input terminal of the flip-flop 26. The FS128 is also input to the clock input terminal of the flip-flop 26, and the input data one symbol before that is taken into the flip-flop 22 is taken into the flip-flop 26. Therefore, the input data one symbol before is always kept. Retained. Then, QB which is the inverted output of the flip-flop 26 is input to the multiplexer circuit 14. Input data is input to the multiplexer circuit 14 as it is, and by selecting and switching the multiplexer circuit 14, the input data is input as it is, or the input data of the previous symbol is inverted.
[0028]
On the other hand, the synchronization preamble detection flag that is the output of the synchronization detection circuit 10 is input to the NOR circuit 28. The synchronization preamble detection flag is a signal that is set to 1 only once at the timing when the synchronization preamble is detected, and this also indicates a bit boundary at the same time. The output of the NOR circuit 28 is input to the data input terminal of the flip-flop 30 in which FS128 is input to the clock input terminal. The Q output of the flip-flop 30 is input to the other input terminal of the NOR circuit 28.
[0029]
Therefore, the NOR circuit 28 forcibly outputs 0 when the synchronization preamble detection flag is set to 1 once per frame. Then, the output 0 of the NOR circuit 28 is taken into the flip-flop 30 at the rise of the FS 128. Thereafter, since the synchronization preamble detection flag is 0, the NOR circuit 28 outputs the inversion of the Q output to the flip-flop 30. Therefore, a signal is obtained at the output of the flip-flop 30 that becomes 0 at the timing of detection of the synchronous preamble, and then 1 and 0 are inverted every time the FS 128 rises. The output of the flip-flop 30 is supplied to the multiplexer circuit 14 via the inverter 32, and the multiplexer circuit 14 selectively switches the input signal according to the signal from the inverter 32.
[0030]
Here, the signal from the inverter 32 is a signal having a cycle twice that of the FS 128 (a signal in which a 1-bit period is one cycle). The polarity is determined by the rising timing of the synchronization detection flag, and is a signal indicating by 1 or 0 whether the current input is a symbol before or after a bit.
[0031]
The multiplexer circuit 14 selects the correction pseudo data from the flip-flop 26 during the period of the previous symbol of one bit and selects and outputs the input data during the period of the subsequent symbol according to the signal from the inverter 32.
[0032]
This operation will be described with reference to FIG. Input data is input with one cycle of FS 128 as one symbol period. The rise of FS128 is slightly delayed with respect to the timing of the input data edge. In the figure, the delay is emphasized.
[0033]
A signal having an edge formed at the timing of FS 128 is obtained in the flip-flop 22, and an inverted signal of one symbol before is obtained in the flip-flop 26.
[0034]
On the other hand, the flip-flop 30 obtains a control signal which becomes 0 for one cycle of FS128 from the bit boundary, and this is inverted and supplied to the multiplexer circuit 14. The multiplexer circuit 14 selects the correction pseudo data from the flip-flop 26 when the control signal is 1, and selectively outputs the input data when the control signal is 0. Therefore, the correction data output from the multiplexer circuit 14 is a signal in which the previous symbol of the input data is replaced with the correction pseudo data. The pseudo data for correction is formed by inverting the symbol after the immediately preceding bit. In the correction data output from the multiplexer circuit 14, a signal that complies with the biphase modulation rule that is always inverted at the bit boundary. become.
[0035]
In FIG. 3, even when 1 of the input data in the portion indicated by the dotted line becomes 0 due to damage, 1 is restored in the correction data by the correction pseudo data.
[0036]
FIG. 4 shows the waveform of each signal in the circuit of this embodiment corresponding to the example of FIG. The input data DATAIN is a biphase modulated signal. In this example, the data “1 (10), 0 (11), 0 (00), 1 (10), 1 (10)” is the third “0 (00)”. It has become (10). If data inversion control is performed with this as it is, a rise due to damage occurs and a phase shift occurs.
[0037]
According to the present embodiment, the data error due to the damage can be eliminated by the replacement with the correction pseudo data, so that the phase shift in the reference clock can be made very small.
[0038]
Here, in the circuit for generating the reference clock as described above, a very short pulse may be formed due to a slight difference in internal delay time. However, such a very short pulse is often not recognized as a rising edge in the PLL circuit and can usually be ignored. Alternatively, this very short pulse may be removed by creating a slight delay signal and adding it.
[0039]
In this way, according to the circuit of the present embodiment, when input data is damaged, correction is performed so that the generation of the reference clock is not adversely affected. Therefore, a correct reference clock can always be generated. Here, the rising edge of the generated reference clock includes a mixture of input data and a clock used for correction. However, the influence is much smaller than the phase shift due to damage, and the influence on the reference clock becomes much smaller, and the damaged data can be substantially eliminated from having a fatal influence on the PLL.
[0040]
【The invention's effect】
As described above, according to the present invention, when an input including data deviating from the biphase modulation rule generated due to damage in the transmission path is input, the corresponding part is corrected and the biphase modulation rule is corrected. Replace with data according to Therefore, the disturbance of the reference clock generated from the input data can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a reference clock generation circuit according to the present invention.
FIG. 2 is a diagram showing a configuration of a correction pseudo data generation circuit.
FIG. 3 is a diagram illustrating signal waveforms of respective units in a correction pseudo data generation circuit;
FIG. 4 is a diagram showing a correction method (policy) and effects when receiving damage.
FIG. 5 is a diagram illustrating an example of a biphase modulated signal.
FIG. 6 is a diagram illustrating an example of a procedure for generating a reference clock from a normal biphase modulation signal.
FIG. 7 is a block diagram showing a configuration of a conventional reference clock generation circuit.
FIG. 8 is a diagram showing the influence on the reference clock when receiving damage.
[Explanation of symbols]
10 synchronization detection circuit, 12 correction pseudo data generation circuit, 14 multiplexer circuit, 16 data inversion control circuit, 18 exclusive OR circuit.

Claims (2)

A reference clock generation circuit that generates a reference clock from input data subjected to biphase modulation,
A synchronization detection circuit that performs synchronization detection on input data that has been bi-phase modulated and detects a bit boundary;
A correction pseudo-data generation circuit that generates and outputs correction pseudo-data based on values of input data before and after the bit boundary; and
A multiplexer that selects and outputs either one of the input data and the correction pseudo data;
The correction pseudo data generation circuit generates a control signal for controlling the multiplexer, and outputs the correction pseudo data instead of the input data at a bit boundary by the control signal. Clock generation circuit. The circuit of claim 1, wherein
  The reference clock generation circuit, wherein the multiplexer switches the input data and the correction pseudo data sequentially for each bit boundary regardless of whether the control signal violates a bi-phase modulation rule.

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