JP3210064B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is used for electronic circuits in various technical fields such as OA equipment such as copiers, facsimile machines, printers, video cameras, etc., home electric appliances, automobiles, power plants, space satellites, etc. Semiconductor device to be used.

In particular, the present invention relates to a semiconductor memory device for storing necessary information signals.

[0003]

2. Description of the Related Art FIG. 1 shows a configuration of a semiconductor memory which can be programmed only once. It is composed of a memory cell having a MOS field effect transistor (hereinafter referred to as "MOSFET") as an insulated gate field effect transistor and an insulating film.

[0004] Such a memory is, for example, "A Ne
w Programmable Cell Utili
Zing Insulator Breakdown ”
IEDM'85, pp639-642.

FIG. 2 shows another type of semiconductor memory.

FIG. 2 is a cross-sectional view of the device.
Mold substrate, 121 is p ⁺ train, 122 is p ⁺ source, 1
23 is a floating gate, 124 is an insulating layer, 125
Is a drain wiring, and 126 is a source wiring. This 12
The floating gate No. 3 is manufactured by embedding polycrystalline silicon in a silicon oxide film, for example.

In the normal state, the source and the drain are non-conductive. A high negative voltage is applied between the source and the drain of this transistor to cause avalanche breakdown of the pn junction on the drain side, and high-energy electrons generated at this time are injected into the floating gate to make the source-drain conductive state. Writing can be performed. When this element is used as a memory, whether or not to inject a charge into the floating gate corresponds to information 1 and 0. However, this type of memory has a problem that not only permanent information cannot be retained but also read characteristics change with time because charges stored in a floating state leak slightly.

In addition, the above-mentioned MOSFET is not suitable for miniaturization and has a problem in the characteristic (gm characteristic) that the transconductance is small.

In addition, the gate length is 0.5 μm for miniaturization.
The above MOSFET based on the scaling law when
No improvement can be expected.

[0010] Separately from these, SiO 2 is deposited on a Si substrate.
_There has been proposed an SOI MOSFET structure in which _two layers are provided, a Si mesa structure is further provided, and a gate oxide film is provided on a mesa side wall [Japanese Patent Laid-Open Publication No. Hei 2-14578].

This element structure is shown in perspective views in FIGS.
232 is an insulating film, 231 'is crystalline Si, 236 is a source region, and 237 is a drain region. Reference numeral 235 denotes a gate electrode having a structure that straddles the channel region of the crystalline Si portion. FIG. 3 is a sectional view taken along the line aa ′ in FIG.
As shown in FIG. 3, the upper portion of the crystalline Si 231 ′ is covered with the gate electrode 235 via the gate oxide film 234, and the lower surface 238 is the surface of the insulating film 232. Further, the dimension of the crystalline Si portion satisfies W _O <2W _H , so that the channel on the side wall becomes dominant and the channel conductance increases.

Further, a MOS which is structurally similar to the above conventional example
An FET has also been proposed.
73].

FIG. 5 is a plan view of this example, and AA 'in FIG.
6 is shown in FIG. 6, and a sectional view of BB 'in FIG. 5 is shown in FIG. 246 forms a source 243, a drain 242, and a channel. It is a crystalline Si layer. Gate electrode 24
5 is a channel region, which is formed by the substrate 240 and the opening 247.
, And the drain layer 242 passes through the crystalline Si layer 246 and is connected to the substrate 240 through the opening 248.

As a result of studying each of the conventional examples described in detail above, despite the above-described structure, the transistor has a large leak current, a large variation in each transistor, and furthermore, the OFF characteristics of the transistor are poor, and the operation is poor. It turned out to be stable. First, the OI of the SOI MOSFET
The cause of the deterioration of the FF characteristics will be described. According to the findings of the present inventors, the cause is that Si in which a channel is formed is formed.
This is because the region except for the interface with the source and drain regions is entirely covered with the insulating film of SiO ₂ . In other words, the Si region in the channel portion is in a completely floating state, the potential cannot be fixed, and the operation becomes unstable. Further, at the moment when the carriers (for example, electrons in the case of a p-type MOSFET) generated in the Si region in the ON state of the transistor are turned OFF, there is no place to go and S
OF to remain there until recombination and disappearance in the i-region
The F characteristic deteriorates.

The reason for the large leakage current in the above-described conventional transistor is that the channel region surrounded by the gate electrode is in direct contact with the underlying insulating layer. That is, when the transistor is turned on, this channel region is completely depleted, the depletion layer reaches the interface between the channel layer and the insulating layer, and a large amount of recombination current occurs due to defects existing there. It is because it occurs.

Conventionally, there is a bipolar PROM as one of read-only memories which can be programmed (written) by a user and which can be randomly accessed. This type of memory cell is shown in FIG. 101 is a bit line, 1
02 is a word line, 103 is a bipolar transistor arranged in a memory cell, each emitter 105 of the bipolar transistor is connected to a bit line 101, and each collector 1
At 06, each word line base 104 is in a floating state. Reference numeral 107 denotes a diode, and the word line is connected to the power supply Vcc 108 via the diode. FIG. 9 shows a cross-sectional structure of the bipolar transistor 103 of the present memory. 110 is a p-type Si substrate, 111 is n
^A buried layer, 112 is an n ⁻ epi layer, 113 is a field oxide film, 114 is a p-type base, 115 is an n ⁺ emitter layer, and 116 is an Al wiring. This memory corresponds to the binary information by destroying the diode between the emitter and the base. FIG. 9A shows a state before writing, and FIG.
Indicates the state after writing.

Before writing, the Al wiring on the n ⁺ emitter has a flat structure as shown at 117. However, when a large current pulse is applied to the word line and bit line during writing, aluminum and silicon Eutectic alloy 118 is base layer 1
14 to be in a conductive state.

However, it is difficult to achieve high integration because the cell size is limited due to the separation of bipolar transistors and the like.
Further, there is a problem that the eutectic alloy 118 formed by a large current varies from cell to cell and stable reading characteristics cannot be obtained. As a dynamic random access memory (DRAM), a surrounding gate transistor (SGT) is used as an address transistor.
And a vertically long memory cell in which a trench capacitor is formed in the substrate-side main electrode region has been proposed.

According to the findings of the present inventors, such D
It has been found that the RAM has the following problems. As the degree of integration and cell miniaturization of 16 megabits or more increase, the size of the capacitor is limited, the capacity becomes small, and large signal charges cannot be stored. On the other hand, the parasitic capacitance of the wiring increases with miniaturization. Then, when the stored signal is read out by the capacity division, the finally output signal becomes smaller and the SN ratio also becomes smaller. Therefore, a malfunction of the memory occurs.

In addition, the vertical structure makes the manufacturing process extremely complicated and does not increase the yield, making it difficult to achieve commercial success. That is, the inventors of the present invention have concluded that a fine transistor such as an SGT is not suitable for the initial purpose of application to a DRAM in the current technology.

[Purpose] The present invention has been made in view of the above technical problems, and has as its object to provide a semiconductor memory device which has a configuration suitable for fine processing and can operate at high speed with low power consumption. .

Another object of the present invention is to provide a semiconductor memory device having a memory function capable of stably obtaining an accurate write operation and performing a high-speed and accurate read operation.

An object of the present invention is to provide a plurality of main electrode regions provided along a main surface of a substrate, a channel region provided therebetween, and a gate provided to the channel region via a gate insulating film. An insulated gate transistor having at least two opposing portions, the gate electrode being opposed to each other; and an electrically destructible memory element provided in one of the main electrode regions. Wherein the gate electrode and the high impurity concentration semiconductor region provided adjacent to the channel region surround at least the entire surface of the channel region along the carrier moving direction, and the high impurity concentration of the channel region A second high-impurity-concentration semiconductor region having the same conductivity type as that of the channel region and having a higher impurity concentration than the channel region is provided on a side facing the high-concentration semiconductor region. It is to provide a semiconductor memory device characterized by being kicked. Another object of the present invention is to provide a plurality of main electrode regions provided along a main surface of a substrate, a channel region provided therebetween, and a gate electrode provided to the channel region via a gate insulating film. Wherein the gate electrode has at least two opposing portions opposing each other, and an electrically destructible memory element provided on one of the main electrode regions. Wherein a semiconductor region having the same conductivity type as the main electrode region and having a lower impurity concentration than the main electrode region is provided between the main electrode region and the channel region. To provide. Further, an object of the present invention is to provide a plurality of main electrode regions and a channel region provided therebetween, a gate electrode provided for the channel region via a gate insulating film, and a gate electrode provided in contact with the channel region. An insulated gate transistor having a semiconductor region having the same conductivity type as the channel region and having a higher impurity concentration than the channel region, wherein the gate electrode includes at least two portions facing each other; And an electrically destructible memory element provided in one of the regions.

[0024]

According to the present invention, a semiconductor device having a high mobility and a high gm characteristic can be obtained because the electric field intensity in the direction perpendicular to the carrier movement direction is small due to the two gate electrodes opposed to each other. Can be prevented, and the reliability of the device can be improved over the life of the device.

Since the capacitance of the Si portion under the gate oxide film decreases, the S factor (Subthreshold
d swing) characteristics are improved and the leakage current is extremely reduced.

Further, the area occupied by the elements is reduced, and high integration can be realized.

The present invention is further improved, and a region having a conductivity type different from the conductivity type of the source / drain portion and a higher impurity concentration than the channel region is provided in a portion other than the portion where the two opposing gate electrodes are provided in the channel region. By adopting a structure in which the impurity concentration is not inverted by the driving voltage applied to the gate when the transistor is driven, the transistor O
At the time of N / OFF, minority carriers (holes in the case of N-channel MOS and electrons in the case of P-channel MOS) enter and exit the semiconductor layer surrounded by the two gate electrodes facing each other, and the switching characteristics are improved. .

In addition, even if the channel region is completely depleted when the transistor is turned on, the depletion layer does not reach the underlying insulating layer due to the high concentration layer, and the generation of dark current is suppressed.

In the case where the microfabrication at the level of 0.1 μm is advanced, it is necessary to adapt to the low temperature operation at the liquid nitrogen temperature level. The increase in parasitic resistance and the decrease in drain current are extremely small.

(Description of Preferred Embodiment) As one preferred embodiment of the present invention, a gate electrode has at least a facing portion sandwiching a channel region, and a junction between the channel region and a source region or a drain region is formed. Except for a semiconductor memory in which a part of other parts except for the transistor includes a transistor provided in contact with the channel region and a doped region capable of transmitting and receiving minority carriers, and uses a destructible insulating layer as a memory element, as an example. I do.

In the channel region of the semiconductor device according to the present invention, the width (d ₃ ) in the direction of the facing portion of the channel region sandwiching the facing portion of the gate electrode and the impurity concentration of the semiconductor in the channel region are determined as follows. Is done. In other words, even when the gate voltage is OFF, it is appropriately selected such that the depletion layers extending from both sides of the opposing portion are connected and depleted. Specifically, if the width of the channel region in the direction of the opposing portion of the gate electrode is d ₃ , and the width of the depletion layer extending from both sides in the same direction is W, the relationship of d ₃ ≦ W is satisfied. This is because if the channel region between the two opposing electrodes is completely depleted, the electric field applied to the inside of the channel region is reduced even if the gate voltage is increased to the level at which the inversion layer is formed, thereby improving the characteristics of the device. I do.

The doped region may be a semiconductor region having a conductivity type different from the conductivity type of the source and drain regions and having a higher impurity concentration than the channel region, and the type and conductivity type of the impurities are limited. is not. Specifically, the impurity concentration in the doped region is set to a concentration such that the doped region is not inverted by a driving voltage applied to the gate when driving the transistor. Functionally, any configuration may be used as long as it can receive carriers from a channel region sandwiched between opposing portions of the gate electrode.

The material used for the gate electrode of the present invention includes metal, polycrystalline silicon, silicide, polycide, etc. Specifically, Al, W, Mo, Ni, C
o, Rh, Pt, and Pd themselves, or silicide and polycide thereof, and are appropriately selected in consideration of the structure, driving conditions, and the like and the work function of the MOSFET.

The shape of the gate electrode and the doped region may be a structure having no gate electrode in a portion facing the doped region, or having the same doped region, or a doped region as described later in the embodiments. In this configuration, a part of the gate electrode is also arranged in a portion facing the region. Further, the cross-sectional shape of the channel region when cut in a direction perpendicular to the carrier moving direction is a square shape such as a square so that the three surfaces are surrounded by the gate electrode and the remaining portion is in contact with the doped region. It is preferred that it is. The side may be a side having a curvature instead of an accurate straight line, and each edge portion at that time may have a shape chamfered in consideration of the coverage of the gate insulating film.

As a transistor suitable for the special memory device of the present invention, a MOSF
It is preferable that the ET element is placed on the substrate side and is in contact with the doped region on the substrate side, and the opposing portion of the gate electrode is arranged so as to have a surface crossing the substrate surface.
Alternatively, a configuration in which the opposing portion of the gate electrode is disposed substantially parallel to the substrate surface and a doped region is provided on the side surface may be adopted. Is preferred.

For example, H. tadato, K .; sunou
shi, N .; Okabe, A .; Nitayama, K .;
Hieda, F.S. Horiguchi, and F.S. M
asuka IEDM (International
Electron Device Meeting)
(1988) A source and a drain are provided above and below via a channel as proposed in PP222-225.
Surroudin with two gate electrodes facing each other
The g Gate transistor (SGT) is known.

On the other hand, in the transistor of the present invention, the source and the source are located before and after the two gate electrodes facing each other.
A drain is provided.

By employing this structure, the source and drain electrodes can be easily formed on the same plane as in the conventional MOSFET. The channel length is the same as that of the conventional MO.
The channel length processing accuracy is high because it is determined by the gate electrode width as in the case of the SFET. Then, patterning of a semiconductor for forming two gate electrode structures which are placed side by side and facing each other can be performed by lithography without a mask, and the structure is suitable for miniaturization. As a result, the distance between the two gate electrodes can be narrowed, and punch-through can be prevented without increasing the impurity concentration, so that a high gm characteristic can be obtained even with higher integration.

Next, a transistor suitable for the present invention is a type in which a MOSFET element is laid on a substrate side, in contact with a doped region on the substrate side, and a facing portion of the gate electrode crosses the substrate surface. The reason why the configuration in which the surface is arranged so as to have
A description will be given in comparison with the SFET.

In both of the conventional MOSFETs, at least a part of the channel region is formed in contact with the underlying insulating layer. This has the following problems.

First, a large amount of leakage current is generated due to generation of dark current. In the structure shown in FIG. 13, a channel region 231 'made of silicon is surrounded by a surface 238 of insulating film 232 and a gate oxide film. When the transistor is turned on, the entire channel region is depleted by the voltage applied to the gate. Thus, the transistor has a large current driving capability as compared with other transistors. However, the interface between the gate oxide film and the silicon in the channel portion has good characteristics due to recent process technology (such as cleaning), but the interface with the insulating film has many defects and a high interface state density. Since the gate electrode is also provided adjacent to the insulating layer shown at 250, depletion of the entire channel portion means that the surface 238 on the insulating layer also comes into contact with the depletion layer. Therefore, when the transistor is in the ON state, holes are accumulated in this channel region if it is an n-type MOSFET. Next, even if the voltage applied to the gate is changed to turn off the transistor, as long as the hole generated from the interface continues to exist in the channel portion, electrons are injected from the source side by the hole, and it is quite difficult. The state that cannot be turned off continues. That is, in a MOSFET operated by depletion, unnecessary carriers must not be generated as compared with a conventional MOSFET.

The same phenomenon occurs in other conventional examples. This will be described with reference to FIG. In this case, Si single crystal portion 246 serving as a channel region
Is connected to the substrate through the opening 247,
The channel is in a floating state, and the problem that there is no escape route for unnecessary carriers (holes for an n-type MOSFET and electrons for a p-type MOSFET) is eliminated. However, as shown by 251 in FIG. 6, since the channel region is in contact with the surface of the underlying insulating layer 241 ', there are places where unnecessary carriers are generated. Therefore, to a greater or lesser extent, the leakage current generated from defects at the interface between the insulating layer and the Si in the channel region deteriorates the device characteristics.

Next, the second problem will be described. The second problem is that the effective channel width tends to vary for each transistor.

The channel width of the conventional transistor is shown in FIG.
And the height and width of the single crystal Si 231 'shown in FIG. Usually, this height is determined by the etching depth of Si. In the case of fabricating a MOSFET having a gate length of 0.1 μm and a gate width of 0.5 μm, this height is about 0.2 μm, and it is necessary to keep the height within 200 °. It is extremely difficult to keep this variation range within the wafer surface or between wafers by the current dry etching method. Further, in FIG.
As described above, the etching shape on the underlying insulating layer has more variation than the upper Si portion, and also has a problem that the thickness of the Si portion changes between the upper portion of Si and the lower portion of Si.

On the other hand, in the transistor used in the device of the present invention, the channel length is
As described above, the channel length is determined with the gate electrode width, so that channel length processing accuracy is high. Since the channel region is defined by the gate electrode portion and the high-concentration layer immediately below or above the channel, the variation is extremely small. Even if the channel portion is depleted when the transistor is turned on, the depletion layer does not spread at the boundary with the high concentration layer. Therefore, since no depletion layer is in contact with the surface of the insulating layer other than the gate oxide film (insulating film), there is no unnecessary carrier generation source.

As described above, a transistor that is finely suited and has a high current driving capability is a memory cell transistor, and the gate of the transistor is a word line.
A memory connected to a bit line is formed on a source region of the transistor via a pn junction. This realizes a once-permanently writable memory having a low error rate, high density, and high-speed read / write characteristics.

[0047]

(Embodiment 1) A first embodiment of the present invention will be described in detail with reference to FIG. FIG. 10 is a top view of the memory cell according to the first embodiment of the present invention. 1001,
1001 'is a word line, 1002 and 1002' are bit lines, 1003 and 1003 'are power supply lines, 1004 is a Si single crystal as a semiconductor active region which operates as a switching transistor in a memory cell, 1005 is a power supply line and a drain layer 1006, a drain layer of the transistor; 1007, a gate portion of the transistor; 1008, a source layer of the transistor;
Reference numeral 9 denotes an electrically destructible insulating layer provided between the source layer and the bit line. X ₁ , X ₁ ′, X ₂ ,
X ₂ ′, X ₃ , X ₃ ′, Y, Y ′ sectional views are shown in FIG.
To 14 are shown. In FIG. 11, reference numeral 1012 denotes p-type Si.
For example, a substrate having a resistivity of several Ωcm is used.
Reference numeral 1013 denotes ap ⁺ type buried layer, 1014 denotes a field oxide film, 1015 denotes an interlayer insulating film, and PSG, BPSG, S
iN, SON, etc. can be used. Reference numeral 1016 denotes a p-type layer provided immediately below the drain, 1017 denotes a drain n ⁺ high-concentration layer, and 1018 denotes a wiring for drain power supply, which is connected to the drain layer 1017 via a contact portion 1019 in the figure. 10 and FIG. 11 correspond to the drain layer 1 of FIG.
006 corresponds to 1017 in FIG. 11, and the contact portion 1005 in FIG. 10 corresponds to 1019 in FIG. In FIG. 11, the passivation film is omitted.

FIG. 12 is a sectional view of a gate portion of a transistor in a memory cell portion. In FIG. 12, reference numeral 1021 denotes
In the channel region, for example, an impurity concentration of 5 × 10 ¹⁴
It is made of a semiconductor of about 5 × 10 ¹⁶ cm ⁻³ . Reference numeral 1022 denotes a gate insulating film whose oxide film thickness needs to be changed depending on the gate length, but is about 60 ° to 250 °.

This is because not only the Si oxide film but also the SiO
N or a laminated film of SiO ₂ and SiON may be used. 10
23 is a gate electrode. For example, a material having a low resistance such as a polycide structure in which the underlayer is p ⁺ -type polysilicon and the upper layer is W _x Si ₁ -x and which has a work function that allows the transistor to have a desired threshold value is selected. Reference numeral 1024 denotes a cross section of the drain power supply wiring.
Is a cross section of the bit line wiring and corresponds to 1002 in FIG. As can be seen from FIG. 12, the channel region 1021
Are defined in the gate insulating film 1022 and the p-layer 1016. Therefore, the channel width of this transistor is the sum of d ₁ and d ₃ , that is, 2d ₁ + d ₃ . Due to the field oxidation process, the thickness of the gate insulating film below the channel region 1021 changes as shown by 1026 in FIG. 12, and it is relatively difficult to control the value. However, in the present transistor, the channel region that actually operates is defined by the underlying p region, so that it is not affected by the fluctuation of the film thickness, and the variation of each transistor is extremely small.

FIG. 13 is a sectional view of the source region of the transistor in the memory cell portion. In FIG. 13, 1030
Is an n ⁺ -Si region serving as a source layer; 1031 'is an insulating film provided on the source;
Non-destruction defines the conduction and non-conduction state of the memory.
The insulating layer is connected to a bit line wiring 1032 via a contact region 1033. As the insulating layer, for example, SiO ₂ , SiON, a laminated structure of SiO ₂ and SiN, or the like can be used. Alternatively, aluminum oxide, tantalum oxide, or the like can be used.

Next, FIG. 14, which is a cross section taken along line YY 'of FIG. 10, will be described.

As shown at 1035 and 1035 'in FIG. 14, the transistors are separated from each other by a vertical plane, and an interlayer insulating film is embedded between the transistors so that the separation width can be reduced. It can be said that this is an excellent structure for high integration. The gate electrode structure in this cross section is a normal MOSF
Although the structure is equivalent to that of the ET, as shown in FIG. 12, the gate electrode is arranged so as to face the side wall when this cross section is viewed in a cross section orthogonal to the ET. Although a gate electrode is also provided on the upper part, d ₁ ,
If the function of the d ₃ d ₃ <d ₁ ... formula (1), be raised gate voltage, since the potential is lift from both sides, the electric field of the channel region is relaxed as compared with the conventional MOSFET . Further, since the manner of changing the potential changes throughout the channel region, a large current can be passed through the transistor ON by these two effects, and good characteristics with high driving capability can be obtained.

FIG. 15 is a circuit diagram showing a 3 × 3 cell semiconductor memory according to the first embodiment.

One cell is an address transistor 10
40 and a memory element 1041. Of course 1
Reference numeral 041 denotes a capacitor before the breakdown of the insulating film and does not become a capacitor after the breakdown.

1001, 1001 ', 1001'', 1
001 "" is a word line connected to each gate of the FET.

Reference numerals 1002, 1002 ', and 1002''denote bit lines connected to one of the memory elements.

Reference numerals 1003, 1003 ', and 1003''denote power supply lines.

As a peripheral circuit of the memory, a bit line voltage setting circuit 1 for setting a bit line voltage to a reference voltage
042, a word line voltage setting circuit 1043, a selection signal generation circuit 104 for generating a signal for sequentially selecting a bit line
4. Bit line selection switches 1045, 1045 ', 10
45 '', a switch 1046 for resetting the bit line read line 1048, and an amplifier 1047.

Hereinafter, the operation of the above-described semiconductor memory will be described.

First, the write operation will be described. This operation includes the following four main operations.

(1) Write Operation No. 1: (Bit Line Precharge) The bit line is set to the reference voltage V _DD by the voltage setting circuit 1042. As a result, there is no potential difference between the power supply line and the bit line, no matter what voltage is applied to the word line, no potential is generated or current flows between the source and drain of the FET. Not destroyed. The precharge voltage of the bit line may or may not be equal to the power supply voltage. At this time, the insulating film region is broken so as not to be in a conductive state. The value of V _DD can be, for example, about 1 to 5 V.

(2) Write Operation No. 2: (Word Line Discharge) The voltages of all the word lines are fixed to the first ground potential V _GND1 . For example, it may be OV. This is performed to prevent a signal from being mixed into a word line adjacent to a word line on which a write operation is performed due to crosstalk.

(3) Write Operation No. 3: (Selection of Word Line to Write) If the current write bit is the cell in the second row and second column with the upper left cell in FIG. 3 as the origin, the word with the write bit The line becomes 1001 'in FIG. Therefore, the potential of the word line and V _G. However, at this time, V _G is V _GND1 <V _G <V _GB ... V _GB is a gate insulating film breakdown voltage.

(4) Write Operation No. 4: (Bit Line Selection) The bit line potential corresponding to the cell to be written existing on the selected line is set to the ground potential. Then, since all the FETs on the selected line are in the ON state, a high voltage is applied to the insulating film by setting the bit line potential to the ground potential, and the insulating film is broken and becomes conductive. In this writing operation, a current flows between the bit line and the word line upon completion of the writing. Therefore, it is desirable to sequentially select the bit lines, but it is also possible to simultaneously write a plurality of bit lines.

Next, the read operation will be described. This operation includes the following four main operations.

(1) Read Operation No. 1 (Bit Line Precharge) The read operation is performed by the same operation as in the write operation. This is because a bit that has not been written is not written by a read operation. The voltage at that time may be the same level as the power supply voltage V _DD .

(2) Read Operation No. 2 (Word Line Discharge) The voltages of all the word lines are fixed to the second ground potential V _GND2 . However, the second ground potential V _GND2 and the first ground potential V _GND1 have a relation of V _GND1 <V _GND2 ...

[0068] (3) to fix the potential of the read operation part 3 (selection of reading line) the word line of the line to be read to V _G range defined by equation (2). As a result, the FETs in the line are turned on.

(4) Read Operation No. 4 (Reset of Bit Line Read Line) The read line 1048 of the bit line is reset by the switch 1046. The reset potential is determined by the power supply connected to the switch 1046, and the potential is set to V _GND2 . After that, 1046 switches are set to O
FF is performed to bring the bit line read line into a floating state.

(5) Read Operation No. 5 (Selection of Bit Line) The bit line sequential selection signal generation circuit 1044 sets the gate of the selected bit selection switch to high level and sets the switch to O.
Set to N state and connect to bit line read line. If the selected cell has not been written, the bit line capacitance is set to C
_Assuming that _BIT and the capacity of the read line are C _OUT , the voltage of the read line is

[0071]

[Outside 1] Converges to

On the other hand, when the selected cell is written and the insulating film is conductive, this read line is in a state of being connected to the power supply V _DD via the transistor. Therefore, the voltage on the read line converges to V _DD . From this difference, it is determined whether the written cell (bit) has been written. This voltage is
047. Reading is performed by the above operation. In the writing state, the time required for the potential of the reading line to converge to V _DD determines the reading speed. As the capacity of the memory increases, the capacity of the bit line and the bit line read line increases. Therefore, how to drive this large capacity is key, and the above-described transistor structure having a fine and high driving capability is extremely effective.

In this embodiment, two types of ground potentials are provided,
The operation was performed because the insulating film was not broken during the read operation. That is, the potential difference applied to both ends of the insulating film during the read operation is set smaller than that during the write operation.

(Description of Manufacturing Method) Next, a manufacturing method according to the first embodiment of the present invention will be described with reference to FIGS. 16 to 19 are sectional views corresponding to FIG.
Corresponds to FIG. First, boron ions are implanted into the surface of the prepared p-type silicon substrate 1012, and about 900
The impurities in the ion-implanted layer are activated at a temperature of ° C. After the formation of the p ⁺ high-concentration layer 1013, the wafer is washed, put into an epitaxial growth apparatus, a natural oxide film formed on the surface is removed by reduction of silane, and the p layer is reduced to 2 μm and p at a temperature of 850 ° C. ^- layer 1021 is continuously grown to be 0.5 [mu] m. Aside up of impurities by low temperature epitaxial is ^{suppressed, p + -p, p-p} - is steep junction is obtained, p ⁺ layer of the concentration of 10 ¹⁹ cm ^-3, the concentration of the p layer 1
The concentration of the 0 ¹⁷ cm ⁻³ and p ⁻ layers is about 10 ¹⁶ cm ⁻³ . The wafer is thermally oxidized to a silicon oxide film 106 of about 250 A.
0, and a chemical vapor deposition (CV)
By D), a silicon nitride film 1061 of 250 ° was deposited (FIG. 16).

Next, the wafer leaving a transistor forming region, using a resist as a mask, the silicon nitride film 1061, even the silicon oxide film 1060 p ^- to each Si epilayer of layer 1021, p layer 1016, the reaction The film is vertically removed by anisotropic etching. The end of the groove by etching may be in the p layer or the p ⁺ layer, and its control is not strictly required due to device special pressure. This is also one of the advantages of the present structure. Next, the resist used for patterning is removed, and after cleaning, a silicon oxide film 1062 of about 250 ° is formed again on the surface where Si is exposed. Thereafter, a silicon nitride film is deposited on the entire surface by CVD, and only the silicon nitride film on the bottom surface 1063 is removed by anisotropic silicon nitride film etching as shown in FIG. 4B. In this case, the silicon nitride film 1064 on the columnar Si remains because it is formed from two layers (FIG. 17).

Next, pyrogeneric oxidation is performed at about 900 ° C. to selectively oxidize only the surface where the silicon nitride film is not formed. By this process, a field oxide film 1014 is formed as shown in FIG. 4C. In this field oxidation step, the silicon pillar I is deformed as shown by 1065, but the deformed region is made of the p layer 1016 or the p ⁺ layer 1013, and is not affected by this deformation. (FIG. 18).

Next, the silicon nitride film 1 used for selective oxidation
066 and the underlying pad oxide film 1067 are removed,
After cleaning the exposed Si surface, a gate oxide film 1022 is formed by thermal oxidation. Further, continuously depositing PolysiW (tungsten), then from the W surface, to form a gate electrode composed of the p ⁺ -type polysilicon and W _1-X Si _X and W by ion implantation and Anfure boron. In this type of transistor operation, since the corresponding distance between the gates is 0.1 μm, the potential of the channel portion is entirely controlled by the gate potential, and ON-
It is turned off. Therefore, the conventional MOSF
Although the threshold value is lower than that of ET, the threshold value is increased by the p ⁺ layer 1068. The upper part of the gate electrode is W
It is made of metal 1069 and realizes low resistance of the word line.

After patterning the gate electrode, the n ⁺ layer is diffused using the gate as a mask to form the source layer 1030,
A drain layer 1017 is formed.

Next, as shown in FIG.
15 are flattened and formed. This planarization can be realized, for example, by combining the deposition of tetraethylorthosilicate (TEOS) and the etch back. After this,
The density of the thin film SiO ₂ is increased in a N ₂ atmosphere at 550 ° C. Further, as a method of forming the thin film SiO ₂ , a method of forming an oxide film in a platinum peroxide solution after cleaning and increasing the density in an N ₂ atmosphere at 500 to 600 ° C. is also effective.

Next, a contact hole 1070 is formed only in the source region 1030. Only the contact hole has an exposed Si surface, and a silicon oxide film 1033 of about 50 ° is formed only in the region of the contact hole by CVD. After this,
The density of the silicon oxide film is increased at 550 ° C. in an N ₂ atmosphere. Further, as a method of forming the thin film SiO ₂ , a method of forming an oxide film in a platinum peroxide solution after cleaning and increasing the density in an N ₂ atmosphere at 500 to 600 ° C. is also effective. Thereafter, a power supply and a bit line wiring are formed, a patterning and a passivation film are formed, and the present cell structure is formed. In this description, an n-channel MOSFET has been described. However, if the conductivity type is reversed, the p-channel MOSFET can be manufactured in a similar process, and the description is omitted. Therefore, the peripheral circuit is an n-type channel MOSFE
It can be manufactured as a CMOS configuration composed of T and p-type channel MOSFET.

As described above, the first embodiment of the present invention
Is a method of forming a conductive state and a non-conductive state depending on the destruction and non-destruction state of the insulating film, and is not a method of reading out a slight accumulated charge unlike conventional DRAM and EPROM,
Even when the miniaturization has advanced, reading with a high S / N can be performed. Further, for this reading, a transistor having a new structure is adopted, and it has fine and high driving capability characteristics, so that high integration and high speed reading can be realized.

(Embodiment 2) Next, Embodiment 2 of the present invention will be described with reference to FIGS. The same parts as those in FIGS. 11 to 14 are denoted by the same reference numerals, and description thereof is omitted.

[0083] The configuration is different from the first embodiment, p as a channel region ^- this p the same conductivity type on the layer 1017 ^-
The point is that a p-layer 1080 having a higher impurity concentration than the layer is formed.

This structure has a p-well layer 1016, a p ^- layer 1
017, the p-layer 1080 may be formed by epitaxial growth while changing the impurity concentration, and can be manufactured in the same process as in the first embodiment.

When a contact is made between the drain layer 1017 and the power supply, the Si layer on the upper surface of the drain is replaced with the one shown in FIG.
It may be performed after slightly etching as shown in 081.

Next, the operation of the transistor used in this embodiment will be described.

The impurity concentration of the p-layer 1016 and the p-layer 1080 is such that no inversion layer is formed on the interface side with the upper gate insulating film 1022 even when the gate voltage during operation becomes the maximum value. I have. Therefore, p ^- layer 10
A channel is formed only on the side wall portion between the gate insulating film 21 and the gate insulating film 1022. Therefore, this configuration is equivalent to a configuration consisting of purely two opposed gates, and the operation is stable.

In general, the insulating film thickness at the edge portion of Si is thinner than the plane portion and the breakdown voltage is reduced. However, according to the present embodiment, as shown in the edge portion 1082, the concentration of the inner p-layer is higher. Since it shows a sufficient withstand voltage, it can be used even if the film thickness is smaller than that of the first embodiment. Thereby, high gm characteristics can be obtained.

With the good transistor characteristics, high-speed reading as a memory can be realized.

(Embodiment 3) Next, Embodiment 3 of the present invention will be described with reference to FIG. The third embodiment, like the second embodiment, relates to the method of improving the memory cell transistor shown in the first embodiment. The cross-sectional views of portions corresponding to the first embodiment other than the cross section shown in FIG. Is the same. The same portions are denoted by the same reference numerals, and description thereof is omitted. A feature of the third embodiment is that an n ⁻ layer 1085 is provided near the source and drain gate electrodes. The structure of this embodiment can be easily formed in a self-aligned manner by using an insulating layer provided on the side wall of the gate electrode, as in the case of manufacturing a configuration such as an LDD or a GOLD. According to the present embodiment, the electric field at the source and drain ends of the gate electrode can be reduced, and it is possible to prevent unnecessary carriers from entering the channel region. As a result, in the memory, not only quick read characteristics can be realized, but also generation of hot carriers and the like can be prevented, and higher reliability can be obtained.

Further, in this embodiment, the n ^- layers are provided symmetrically for the source and the drain, but the high electric field is actually applied to the drain end, and the source side increases the driving capability. An n ⁻ layer may be provided only on the drain side because it is not desired to add a resistance component.

(Embodiment 4) In this embodiment, wirings connected to the source and drain of a transistor are arranged so as to cross each other.

Embodiment 4 of the present invention will be described. FIG.
6 is a plan view, FIG. 27 is a sectional view taken along the line X ₁ X ₁ ′ of FIG.
Indicates a YY 'cross section of FIG. In the first embodiment, the word line runs in the horizontal direction, and the bit line and the power supply line are provided in the vertical direction. On the other hand, this embodiment has a layout in which word lines 1001 and 1001 'and power supply lines 1096 and 1096' run in the horizontal direction, while only bit lines 1002 and 1002 'run in the vertical direction. Since this transistor has a vertical shape,
By running the power line in the horizontal direction in this way,
There is an advantage that the area per two cells is reduced as compared with the first embodiment, and higher integration can be achieved.

One configuration enabling the layout of FIG. 26 will be described with reference to FIGS. In FIG.
Reference numeral 1100 denotes an n ⁺ type polysilicon-W as a power supply line.
_1-X Si X -W wiring 1101 is a direct contact portion to the n ⁺ -type polysilicon is in contact with the drain layer 1017. This is made long in the horizontal direction as shown in FIG.
It can be seen that two polysilicon-polycide W wirings 023 and 1100 are arranged. 27 and 28, a two-layer metal wiring may be used, and the first metal may be a bit line and the second metal may be a power supply line.

(Embodiment 5) Next, in Embodiment 5 of the present invention, FIG. 29 which is a layout diagram of a memory cell, FIG. 30 which is a cross section taken along the line X ₁ X ₁ ′ of FIG. 29, and X ₃ X ₃ ′ of FIG. This will be described with reference to FIG. 1105 and 110 in FIG.
As shown in FIG. 6, the present embodiment differs from the first embodiment in that the source and drain layer contact sizes of the transistor are widened. Since the long contact is widened in the direction perpendicular to the direction in which the current flows in the transistor (YY 'direction), it is possible to make contact with the side walls of the source layer and the drain layer.
The contact resistance is reduced. In particular, as miniaturization progresses,
Parasitic resistance and capacitance have a significant effect on circuit characteristics as well as transistor drive capability. The above structure is excellent in reducing the parasitic resistance in this regard. Therefore, in order to clarify the structure of the contact, a detailed description will be given with reference to FIGS.

In FIG. 30, reference numeral 1105 denotes a drain layer contact hole; 1107, a first interlayer insulating layer for stopping the contact etching; 1109, a second interlayer insulating layer; In this case, a material that can obtain the selectivity is used. For example, a silicon nitride film may be used as the first interlayer insulating layer, and a silicon oxide film may be used as the second interlayer insulating layer. This makes it possible to come into contact with the wiring metal over a wide area as indicated by reference numeral 1108 in FIG.

[0097] On the other hand, the source region contacts the memory thin film insulating layer 1111 is attached to the surface of the n ⁺ layer 1110 exposed as shown in FIG. 31, the p ⁺ metal wire through the layer 1
032. As described above, by using the structure of this embodiment, the resistance of the contact portion is further reduced, and high-speed reading can be realized.

(Embodiment 6) Referring to FIG.
33 will be described. In the sixth embodiment, the structure of the first embodiment is manufactured by a method different from the manufacturing method described in the first embodiment. FIG. 1 showing a manufacturing method of Example 1.
The description of the same parts as those in FIGS. 6 to 20 is omitted, and the same parts are denoted by the same reference numerals.

As shown in FIG. 32, the greatest feature is that a field oxide film is formed by film formation and etching, not by selective oxidation. The processes up to the formation of the pad oxide film surrounding the columnar semiconductor region and the process of forming the silicon nitride film are the same as those in the first embodiment. Thereafter, the silicon oxide film on the surface obtained by anisotropically etching the silicon nitride film is peeled off, and a thermal oxide film 1092 is formed again. Then, an interlayer insulating film is formed using TEOS, and SiO _{2 is} etched back.
A layer 1091 is formed. It suffices that the etching selectivity between the silicon nitride film and the silicon oxide film is sufficient at the time of this etch back.

By this etch back, the surface of the field oxide film is set to be higher than the interface between p layer 1016 and p ⁺ buried layer 1013 and lower than the interface between p layer 1016 and p ⁻ layer 1021. Next, the silicon nitride film is removed by etching, the pad oxide film is removed, and after cleaning, the gate is oxidized.
The shape of the field oxide film as shown in FIG. Thereafter, similarly to the first embodiment, the gate electrode layers 1068, 1068
69 may be formed. By using the manufacturing method described above, unnecessary diffusion of impurities is reduced without including a high heat process,
The size of the channel region is stabilized. Furthermore, there is an advantage that there is no distortion generated by field oxidation or the like. As a semiconductor memory, there is also an advantage that the present device can be realized with a high yield since the variation of each memory cell is reduced.

As a result of manufacturing and writing / reading a semiconductor memory based on each of the above-described embodiments, it was confirmed that each of the embodiments performed a better operation than expected.

Next, a PN junction destruction type memory will be described as a memory element.

(Embodiment 7) FIGS. 34 and 35 are sectional views of a memory cell according to Embodiment 7 of the present invention, and correspond to FIG. 13 described above. 13 is different from FIG. 13 in that an insulating layer 1031 ′ (FIG. 13) forming a memory element is a p ⁺ type semiconductor layer 103.
1 (FIG. 34) to form a PN junction breakdown type memory. Other configurations of the semiconductor memory are the same as those of the first embodiment.

Here, reference numeral 1030 denotes n ⁺ − which is a source layer.
The Si region 1031 is formed by p ⁺ provided on its source.
In the region, the conduction and non-conduction state of the memory are defined by the pn junction. A contact region 1033 is formed on the p ⁺ layer.
Is connected to the bit line wiring 1032.

Next, an operation method and a storage method of the memory device according to the present invention will be described. FIG. 36 shows the layout of the memory cell of this example as an equivalent circuit.
010 to 1001 "" are word lines, 1002 to 100
2 ″ indicates a bit line, and 1003 to 1003 ″ indicate a power supply line. Each cell includes a transistor 1040 which is fine and has high current driving capability, and a pn junction 1041 is provided in a source layer of the transistor to constitute a memory cell.
Also, as peripheral circuits of the memory, a bit line voltage setting circuit 1042, a word line voltage setting circuit 1043, a bit line sequential selection signal generation circuit 1044, bit line selection switches 1045 to 1045 '', a bit line read line 104
8 is comprised of a switch 1046 for resetting 8 and an amplifier 1047.

Next, the write operation will be described.

(1) Write Operation 1: (Precharge Bit Line) The bit line is set to the voltage V _DD by the voltage setting circuit 1042.
Set to. Thus, there is no potential difference between the power supply line and the bit line, no matter what voltage is applied to the word line, no potential is generated or current flows between the source and drain, and the pn junction shown in 1041 is destroyed. Not done. The precharge voltage of this bit line may be other than the same as the power supply voltage V _{DD as long as the} pn junction region is broken and does not become conductive. The value of V _DD can be, for example, about 1 to 5 V.

(2) Write Operation 2: Word Line Discharge The voltages of all the word lines are fixed to the first ground potential V _GND1 . For example, the voltage may be set to 0V. This is performed to prevent a signal from being mixed into a word line adjacent to a word line on which a write operation is performed due to crosstalk.

(3) Write Operation No. 3 (Selection of Write Word Line) It is assumed that the current write bit is a cell in the second row and the second column with the upper left cell as the origin. The word line with the write bit is denoted by 1001 'in FIG. Therefore, the potential of the word line and V _G. Here, V _G is V _GND1 <V _G <V _GB formula (2). V _GB is a gate insulating film breakdown voltage.

(4) Write Operation 4 (Bit Line Selection) The bit line potential corresponding to the write cell existing on the selected line is set to the ground potential. Then, since all the transistors on the selected line are in the ON state, by setting the bit line potential to the ground potential, a high voltage is applied to the pn junction, and the pn junction is broken and becomes conductive. In this writing operation, a current flows between the bit line and the word line upon completion of the writing. Therefore, it is desirable to sequentially select the bit lines, but it is also possible to simultaneously write a plurality of bit lines.

Next, the read operation will be described.

(1) Read Operation No. 1 (Bit Line Precharge) The read operation is performed by the same operation as in the write operation. This is because a bit that has not been written by the read operation is not written. The voltage at that time may be the same level as the power supply voltage V _DD .

(2) Read Operation No. 2 (Word Line Discharge) The voltages of all the word lines are fixed to the second ground potential V _GND2 . However, the second ground potential V _GND2 and the first ground potential V _GND1 have a relationship of V _GND1 <V _GND2 Equation (3).

[0114] (3) to fix the potential of the read operation part 3 (selection of reading line) the word line of the line to be read (2) the V _G range defined by the formula. As a result, the transistors on the line are turned on.

(4) Read Operation No. 4 (Reset of Bit Line Read Line) The bit line read line 1048 is reset by the switch 1046. The reset potential is determined by the switch 1
The potential is determined based on the power supply connected to 046, and its potential is set to V _GND2 . After that, set 1046 switches to OF
F to bring the bit line read line into a floating state.

(5) Read Operation No. 5 (Selection of Bit Line) The bit line sequential selection signal generation circuit 1044 sets the gate of the selected bit selection switch to high level, turns on the switch, and connects to the bit line read line. . now,
If the selected cell has not been written, the bit line capacitance is C _BIT and the read line capacitance is C _OUT , the read line voltage is:

[0117]

[Outside 2] Converges to

On the other hand, the selected cell has been written and pn
When the junction is conductive, the read line is connected to the power supply V _DD via the transistor. Therefore, the voltage on the read line converges to V _DD . From the difference, it is determined whether the written cell (bit) is written or not. This voltage is
7 to detect. Reading is performed by the above operation. In the writing state, the time required for the potential of the read line to converge to _VDD determines the reading speed. As the capacity of the memory increases, the capacity of the bit line and the bit line read line increases. Therefore, how to drive this large capacity is key, and the transistor structure described in this embodiment, which is fine and has high driving capability, is extremely effective.

In this embodiment, two types of ground potentials are provided.
The operation was performed because the pn junction was not destroyed during the read operation. That is, the potential difference applied to both ends of the pn junction during the read operation is set smaller than that during the write.

Next, the manufacturing method of the seventh embodiment will be described. The process is basically the same as the process shown in FIG. 16 through FIG. 20 except that a p-type semiconductor layer is formed instead of the insulating layer. Become like

That is, the MOSFET shown in FIG.
After the formation, only the source region 1030 has the contact hole 107.
Open 0. The Si surface is exposed only in this contact hole, and p ⁺ layers 400 # to 800 # shown in 1033 in FIG. 4 are formed by LPCVD only in the region of this contact hole.
After that, wirings for power supply and bit lines are formed and patterned, and a passivation film is formed to form the present cell structure.

As described above, according to the embodiment of the present invention, the conduction and non-conduction states are formed by the destruction / non-destruction state of the pn junction, and unlike the conventional DRAM and E ² PROM, the slightly accumulated charge Is not read, it is possible to read at a high S / N even when the miniaturization is advanced.
For this read, a transistor with a new structure is adopted.
Since it is fine and has high driving capability characteristics, high integration and high-speed reading can be realized.

(Eighth Embodiment) Next, an eighth embodiment of the present invention will be described with reference to FIGS. FIG.
Portions equivalent to 24 are denoted by the same reference numerals, and description thereof is the same as that of the second embodiment, and will not be repeated here. In this example, the memory element is formed of a p ⁺ pn ⁺ junction and has a small junction capacitance.

(Embodiment 9) The present embodiment shown in FIG. 39 is the same as FIG. 25 of Embodiment 3 described above. The only difference is that ap ⁺ -type semiconductor layer 1031 is formed instead of the insulating layer to form a pn junction.

(Embodiment 10) Embodiment 10 shown in FIG. 40 is the same as FIG. 28 of Embodiment 4. The only difference is that p ⁺ semiconductor layer 1031 is formed instead of an insulating layer.

(Eleventh Embodiment) Next, an eleventh embodiment of the present invention will be described with reference to FIG. This drawing is a sectional view equivalent to that of FIG. 34 and differs only in this portion, so the difference will be described only with reference to this drawing. As in the previous case, the same parts are denoted by the same reference numerals, and the description is omitted. Example 11 is Example 1
This is different from the first embodiment in that the p ⁺ layer is selectively formed on the Si layer, whereas the second embodiment is different from the n ⁺ source layer 1030 in the first embodiment.
The point is that ap ⁺ layer 1088 is formed in the n ⁺ layer by implanting and annealing p-type ions, for example, boron using the upper contact hole as a mask. When the structure of this embodiment is used, the leakage current of the pn junction is reduced, the conduction and non-conduction modes become more remarkable, and a high S / N is obtained. Further, after the ion implantation, a high-resistance layer provided by forming a p ⁺ layer of amorphous to the n ⁺ layer in, it is possible to achieve non-conduction of.

(Embodiment 12) This embodiment is the same as the embodiment 5 shown in FIG. 31, except that the memory element of the source portion is exposed.
^The structure covers the protruding surface 1110 of the ⁺ layer 1030. This memory element can be formed as ap ⁺ type semiconductor layer by selective deposition by LPCVD. In this example, the source contact resistance is further reduced, and high-speed reading is possible.

According to the embodiment described above, a conductive or non-conductive state is formed by the destruction or non-destruction of the pn junction as a semiconductor junction, and a signal written with a high S / N can be read. In memory, low error rate,
A highly reliable memory can be realized. Further, since a new type of transistor having a high driving capability is used for a memory cell, there is an effect that a high-speed and highly integrated memory can be realized.

That is, when a semiconductor layer is used as a memory element and PN
By recording information by either the destruction of the junction or the non-destruction state, the variation in the destruction state of each cell is smaller than in the case of the insulating film, so that the reliability is high.

In any case, in the present invention, pn junction, insulating film / semiconductor junction, metal / insulating film / semiconductor junction, PIN junction, semiconductor / insulating film / semiconductor junction PI are used as memory elements.
Any electrically destructible junction such as a junction, an IN junction, a Schottky junction, or a hetero junction is used.

The present invention has been described with reference to the embodiments. However, the present invention is not limited to these embodiments, and includes various modifications due to combinations and exchanges of the respective element technologies.

According to the embodiment described above, the conduction and non-conduction state is formed by the destruction and non-destruction state of the memory element.
A signal written with a high S / N can be read,
A low error rate and highly reliable memory can be realized. Further, by using a new type of transistor having a high driving capability for a memory cell, there is an effect that a high-speed and highly integrated memory can be realized.

[Description of Another Preferred Embodiment] A more preferred embodiment of the present invention comprises a source region, a drain region, a channel region provided therebetween, and a gate insulating film for the channel region. And a gate electrode provided through the semiconductor device, comprising a semiconductor region provided in contact with the channel region and having the same conductivity type as the channel region and having a higher impurity concentration than the channel region. A plurality of semiconductor structures each having at least two opposing portions opposing each other, wherein the opposing portions are arranged so as to have a surface intersecting a junction surface between the channel region and the semiconductor region; A first wiring having a common gate electrode of a plurality of semiconductor structures is different from a source region serving as a memory element in a source region of the plurality of semiconductor structures. A semiconductor device comprising a second wiring for forming a PN junction through an electric material and connecting the plurality of semiconductor structures, wherein a power supply line is provided between the second wirings. It is.

Alternatively, the source region, the drain region,
In a semiconductor device having a channel region provided therebetween and a gate electrode provided on the channel region with a gate insulating film interposed therebetween, a semiconductor device provided in contact with the channel region and having the same conductivity as the channel region. A semiconductor region having a higher impurity concentration than the channel region.
The gate electrode has at least two opposing portions opposing each other, and a plurality of semiconductor structures are arranged such that the opposing portions have a surface intersecting a junction surface between the channel region and the semiconductor region. A first wiring which is unique and has a common gate electrode for the plurality of semiconductor structures, and a second wiring for connecting the plurality of semiconductor structures via an insulating film as a memory element on a source region of the plurality of semiconductor structures. In a semiconductor device including two wirings, a power supply line is provided between the second wirings.

As a memory that can be programmed and randomly accessed by a user, a dynamic RAM (DRA)
M). FIG. 43 shows a memory cell of this type.
Reference numeral 501 denotes a bit line, 502 denotes a word line, and 503 denotes a MOS transistor disposed in a memory cell. Each MOS transistor 504 is connected to a bit line 501, each gate is connected to a word line 502, and each drain is connected to a capacitor 507. It is. 508 is a field plate of the capacitor held at the ground potential.

A memory cell is selected by selecting and driving a word line, and cell information is exposed to a bit line. This small signal is received by a sense amplifier, amplified, sent to an output buffer amplifier, and output.

However, a small signal charge is converted into a large b
Since the data is read out to the it line capacitance and a slight change thereof is amplified and read by the sense amplifier, there is a problem that a noise margin is narrow and a malfunction occurs due to a slight noise. To improve this problem, a structure in which dummy bit lines are provided as shown in FIG. 43 has also been proposed. Memory cell 503 is bit
The dummy memory cell 513 is connected to the dummy bit line 512.

When the sense amplifier 511 differentially amplifies the information of the memory cell 503 and the signal level of the dummy cell 513 by selecting the word line 502, the noise generated at the intersection of the word line 502 and the bit line is mutually canceled. There is an advantage.

In order to achieve high integration and high speed in a memory, a transistor which is fine and has a high current driving capability is required.

As described above, although the noise is reduced by providing the dummy cells, the method of detecting a very small voltage read from a small capacitance to a large capacitance is not changed. Therefore, further miniaturization will be promoted in the future,
As the number increases and the cell size decreases, the bit line capacity further increases, and the memory cell capacity further decreases. In order to increase the capacity of the memory cell, the insulating film thickness of the capacitor may be reduced.
It is thinned to the following, and if the film is thinned any more,
Problems of tunnel current and dielectric strength cannot be ignored, and it becomes difficult to ensure reliability. In order to reduce noise, there is a means for arranging a shield line for preventing crosstalk. However, this leads to an increase in bit line capacity and a reduction in signal level. It is not a real improvement.

As described above, the conventional dynamic R
In the case of the AM type memory, if the miniaturization and the increase of the number of bits are advanced in the future, a sufficient noise margin cannot be secured.

Further, as a result of a study of the structure of the transistor in each of the conventional examples, it was found that the transistor has a large leak current, a large variation among the transistors, and that the OFF characteristics of the transistor are poor and the operation becomes unstable. did.

Therefore, the following embodiments have in common a source region, a drain region, a channel region provided therebetween, and a gate electrode provided via a gate insulating film with respect to the channel region. And a semiconductor region provided in contact with the channel region and having the same conductivity type as the channel region and having a higher impurity concentration than the channel region, and the gate electrode has two opposing portions opposing each other. Using at least a transistor, wherein the opposing portion is disposed so as to have a surface that intersects a junction surface between the channel region and the semiconductor region. In a memory cell in which a memory element is formed between a bit line and a source layer of the transistor as a word line, adjacent b By disposing the power wiring between t line is to provide a semiconductor memory device adapted for miniaturization.

According to the embodiment described below, the power supply wiring arranged between the bit lines can realize a semiconductor memory device in which noise is greatly reduced and a noise margin is large.

Basically, the dummy bits described with reference to FIG. 43 can be eliminated, and the driving method can be simplified.

(Thirteenth Embodiment) A thirteenth embodiment will be described. Since the configuration of the memory cell of this example is the same as in FIGS. 11 to 14, a detailed description is omitted here. The differences from the configuration of the embodiment are characteristically shown in FIG.

This embodiment is an example in which the present invention is applied to a memory cell in which writing to a bit is performed by destruction or non-destruction of an insulating film.

FIG. 33 is a circuit diagram showing the layout of the memory cell of this embodiment. FIG.
The same parts as those of No. 5 are denoted by the same reference numerals, and description thereof is omitted. Reference numeral 1081 denotes an insulating thin film as a memory element provided in each memory cell.

Next, an operation method and a storage method of the memory device according to the present invention will be described. 1001-100
1 "" indicates a wort line, 1002 to 1002 "indicates a bit line, and 1003 to 1003" indicate a power supply line. Each cell is a transistor 1040 which is fine and has a high current driving capability.
In addition, a capacitor 1081 including an insulating layer as a memory element is provided in a source layer of the transistor to form a memory cell. Further, as a peripheral circuit of the memory, a switch 1042 for precharging a bit line, a word line voltage setting circuit 1043, a bit line sequential selection signal generation circuit 1
044, bit line selection switches 1045 to 104
5 '', a switch 1046 for resetting the bit line read line 1048, and an amplifier 1047.

Next, the write operation will be described.

(1) Write Operation 1: (Precharge Bit Line) The bit line is turned on by the 1042 switch MOS, and the voltage V
Precharge to _DD . Thus, there is no potential difference between the power supply line and the bit line, no matter what voltage is applied to the wort line, no potential is generated or current flows between the source and drain, and the memory element 1081 shown in 1041 is destroyed. Not done. The precharge voltage of this bit line may be other than the same as the power supply voltage V _{PD as long} as the pn junction region is broken and does not become conductive. V _DD
Can be, for example, about 1 to 5 V.

(2) Write Operation No. 2: (Word Line Discharge) The voltages of all the word lines are fixed to the first ground potential V _GND1 . For example, the voltage may be set to 0V. This is performed to prevent a signal from being mixed into a word line adjacent to a word line on which a write operation is performed due to crosstalk.

(3) Write Operation 3 (Selection of Word Line to Write)
Assume the cell in the row and the second column. The word line with the write bit is denoted by 1001 'in FIG. Therefore, the potential of the word line and V _G. Here, V _G is V _GND1 <V _G <V _GB formula (2). V _GB is a gate insulating film breakdown voltage.

(4) Write Operation No. 4 (Bit Line Selection) The bit line potential corresponding to the write cell existing on the selected line is set to the ground potential 1. Then, since all the transistors on the selected line are in the ON state, by setting the bit line potential to the ground potential, a high voltage is applied to the pn junction, the pn junction is destroyed, and the pn junction is turned on. At this time, since the power supply wiring is arranged between the bit lines, the adjacent bit is
Since there is no risk of line cells being destroyed, peripheral circuits necessary for fixing the potential of the adjacent bit line are not necessary. In this write operation, a current flows between the bit line and the word line upon completion of the write,
It is desirable to select bit lines sequentially, but it is also possible to write a plurality of bit lines simultaneously.

Next, the read operation will be described.

(1) Read Operation 1 (Bit Line Precharge) The read operation is performed by the same operation as in the write operation. This is because a bit that has not been written is not written by a read operation. The voltage at that time may be the same level as the power supply voltage V _DD . (2) Read operation 2 (word line discharge) The voltages of all the word lines are fixed to the second ground potential V _GND2 . However, the second ground potential V _GND2 and the first ground potential V _GND1 have a relation of V _GND1 <V _GND2 ...

[0157] (3) to fix the potential of the read operation part 3 (selection of reading line) the word line of the line to be read (2) the V _G range defined by the formula. As a result, the transistors on the line are turned on.

(4) Read Operation No. 4 (Bit Line Read Line Reset) The bit line read line 1048 is reset by the switch 1046. The reset potential is determined by the switch 1
The potential is determined based on the power supply connected to 046, and its potential is set to V _GND2 . After that, set 1046 switches to OF
F to bring the bit line read line into a floating state.

(5) Read Operation No. 5 (Selection of Bit Line) The bit line sequential selection signal generation circuit 1044 sets the gate of the selected bit selection switch to high level, turns on the switch, and connects to the bit line read line. . now,
When the selected cell is not written, the bit line capacitance is set to C
_Assuming that _BIT and the capacity of the read line are C _OUT , the voltage of the read line is

[0160]

[Outside 3] Converges to

On the other hand, when the selected cell is written and the memory element is conductive, this read line is in a state of being connected to the power supply V _DD via the transistor. Therefore, the voltage on the read line converges to V _DD . From this difference, it is determined whether the cell (bit) has been written or not. This voltage is detected by the amplifier 1047. Reading is performed by the above operation. In the writing state, the time required for the potential of the reading line to converge to V _DD determines the reading speed. As the capacity of the memory increases, the capacity of the bit line and the bit line read line increases. Therefore, how to drive this large capacity is key,
The transistor structure described in this embodiment, which is fine and has high driving capability, is extremely effective.

In this embodiment, two types of ground potentials are provided.
The operation was performed because the memory element was not destroyed during the read operation. That is, the potential difference applied to both ends of the memory element during the read operation is set smaller than that during the write operation.

The method of manufacturing the memory cell of this embodiment is similar to that of FIG.
Since the method is the same as that described in 4 to 18, detailed description is omitted here.

A capacitor provided in each memory cell and having an electrically destructible insulating film as a memory element is a PN junction using a semiconductor film of the opposite conductivity type to the main electrode region instead of the insulating film. Can be replaced by

In this case, the configuration of the memory cell is only changed from the insulating film to the semiconductor film, and the other basic configuration is not changed. FIG. 45 shows a circuit configuration of a semiconductor memory when a PN junction is used as a memory element. Also, the operation method is basically the same.

(Embodiment 14) Next, Embodiment 14 of the present invention will be described.
FIG. 46 shows a top view, FIG. 47 shows an X ₃ X ₃ ′ cross-sectional view of FIG. 46, and FIG. 48 shows a YY ′ cross-sectional view of FIG.

In this embodiment, the power supply lines 1003, 100
3 'is a first wiring layer 1018, which is a bit line 100
2, 1002 'is formed of the second wiring layer 1082. 1083 and 1083 'are passivation films. By separately providing the power supply line and the bit line wiring layers in this manner, the area per cell is reduced as compared with the above embodiment, and there is an advantage that high integration can be achieved.

In this embodiment, the same effect can be obtained by using the bit line as the first layer and the power supply line as the second layer. Also,
The same effect can be obtained by using a P-type semiconductor film instead of the insulating film for the structure of the memory element.

(Embodiment 15) Next, Embodiment 15 of the present invention will be described.
FIG. 49 shows a plan view of FIG. FIG. 50 is a cross-sectional view taken along the line YY ′ of FIG.

In this embodiment, the power supply lines 1003, 103
03 'is a first wiring layer 1018, bit line 1
002 and 1002 'are the second wiring layers 1082, which are formed immediately above the memory cells. With such a structure, higher integration can be achieved.

In this embodiment, the same effect can be obtained by using the bit line as the first layer and the power supply line as the second layer. Also,
The same effect can be obtained by using a P-type semiconductor layer instead of the insulating film for the structure of the memory element.

(Embodiment 16) Next, Embodiment 16 of the present invention will be described.
51 is shown in a plan view in FIG. FIG. 41 is a sectional view taken along the line X ₃ X ₃ ′ of FIG. 40, and the description will be made with reference to these figures.

In this embodiment, the power supply lines 1003, 100
3 'is formed using both the first and second wiring layers 1032' and 1082, and the first and second wiring layers are opened in parallel with the wiring. Connected by a contact hole. By forming the power supply line using two-layer wiring, crosstalk between bit lines can be more reliably prevented.

In this embodiment, the same effect can be obtained by using a P-type semiconductor film instead of an insulating film for the structure of the memory element.

(Embodiment 17) FIG. 53 is a plan view showing Embodiment 17 of the present invention. FIG. 54 is a sectional view taken along the line X ₃ X ₃ ′ of FIG. 53, and the description will be made with reference to these figures.

In this embodiment, the adjacent power supply line 100
3, 1003 'are connected to each other by a second wiring layer 1082, and the bit lines 1002, 1002' are covered with a power supply line. By adopting such a structure, crosstalk between bit lines can be more reliably prevented.

In this embodiment, a similar effect can be obtained by using a P-type semiconductor in place of the insulating film for the structure of the memory element.

According to the above-described embodiment, in a semiconductor memory device in which conduction or non-conduction is formed by destruction or non-destruction of a memory element, crosstalk between bits can be more reliably prevented, and a low error rate, A highly reliable memory can be realized.

(Embodiment 18) In the embodiment described below, a barrier layer is provided between an insulating film for constituting a memory element and a main electrode region provided thereunder.

As the barrier layer, any material can be used as long as it can prevent the reaction between the electrode provided on the insulating film and the main electrode region. Specifically, TiN, Ti,
A material selected from W and the like is preferably used.

With such a configuration, it is possible to prevent the occurrence of a short circuit between the main electrode region and the channel region due to the reaction between the electrode and the main electrode region and the occurrence of a leak current after the breakdown of the insulating layer (writing operation).

Specifically, the configuration shown in FIGS. 13 and 14 is improved as shown in FIGS. 55 and 56, the configuration shown in FIG. 20 is improved as shown in FIG. 57, and the configuration shown in FIGS. 23 and 24 is improved. Similarly to the configuration shown in FIGS. 58 and 59, the configuration shown in FIG. 60, which is an improvement of FIG. 25, the configuration shown in FIG. 61, which is an improvement of FIG. 28, and FIG. 62, which is an improvement of FIG.

In FIG. 55 to FIG.
010 is a barrier layer.

(Embodiment 19) This embodiment shown in FIG. 63 is an example in which the barrier layer technology is applied to a PN junction breakdown type memory.

2010 is a barrier layer, 2011 is a semiconductor thin film made of the same conductivity type semiconductor as the main electrode region 1030,
2012 is a thin film made of a semiconductor of a conductivity type different from that of the semiconductor thin film 2011.

For the thin films 2011 and 2012, phosphorus-doped polycrystalline Si, boron-doped polycrystalline Si and the like are used, respectively.

As described above, by forming the memory element separately from the transistor, it is possible to prevent the influence of the junction breakdown from affecting the transistor.

[0188]

According to the present invention, a fine memory cell can be provided and a semiconductor memory device which can operate at high speed with low power consumption can be provided. In addition, the layout of the memory cells is simple, and the entire occupied area can be reduced. Further, it is possible to provide a memory cell having high driving capability and good switching characteristics.

[Brief description of the drawings]

FIG. 1 is a schematic diagram for explaining a conventional semiconductor memory device.

FIG. 2 is a schematic cross-sectional view for explaining a conventional semiconductor memory device.

FIG. 3 is a schematic cross-sectional view illustrating a conventional transistor.

FIG. 4 is a schematic perspective view for explaining a conventional transistor.

FIG. 5 is a schematic top view for explaining a conventional semiconductor device.

FIG. 6 is a schematic sectional view showing a conventional semiconductor device.

FIG. 7 is a schematic sectional view showing a conventional semiconductor device.

FIG. 8 is a circuit diagram showing a conventional bipolar transistor memory.

FIG. 9 is a schematic sectional view for explaining a conventional bipolar transistor memory.

FIG. 10 is a schematic top view of the semiconductor device according to the first embodiment of the present invention.

11 is a schematic cross-sectional view taken along line X ₁ X ₁ ′ in FIG.

FIG. 12 is a schematic cross section taken along line X ₂ X ₂ ′ in FIG.

FIG. 13 is a schematic cross section taken along line X ₃ X ₃ ′ in FIG.

FIG. 14 is a schematic cross section taken along line YY ′ in FIG.

FIG. 15 is a circuit configuration diagram of the semiconductor device according to the first embodiment.

FIG. 16 is a schematic diagram for explaining the manufacturing method according to the first embodiment.

FIG. 17 is a schematic diagram for explaining the manufacturing method according to the first embodiment.

FIG. 18 is a schematic diagram for explaining the manufacturing method according to the first embodiment.

FIG. 19 is a schematic view for explaining the manufacturing method according to the first embodiment.

FIG. 20 is a schematic diagram for explaining the manufacturing method according to the first embodiment.

FIG. 21 is a schematic sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 22 is a schematic sectional view of a semiconductor device according to a second embodiment.

FIG. 23 is a schematic sectional view of a semiconductor device according to a second embodiment.

FIG. 24 is a schematic sectional view of a semiconductor device according to a second embodiment.

FIG. 25 is a schematic sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 26 is a schematic top view of a semiconductor device according to Embodiment 4 of the present invention.

FIG. 27 is a schematic cross section taken along line X ₁ X ₁ ′ in FIG. 26;

FIG. 28 is a schematic cross section taken along line YY ′ in FIG. 26;

FIG. 29 is a schematic top view of a semiconductor device according to Embodiment 5 of the present invention.

30 is a schematic cross section taken along line X ₁ X ₁ ′ in FIG. 29.

FIG. 31 is a schematic cross section taken along line X ₃ X ₃ ′ in FIG. 29.

FIG. 32 is a schematic diagram for explaining a manufacturing step of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 33 is a schematic diagram for explaining the manufacturing process of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 34 is a schematic sectional view of a semiconductor device according to a seventh embodiment.

FIG. 35 is a schematic sectional view of a semiconductor device according to a seventh embodiment.

FIG. 36 is a circuit configuration diagram of a semiconductor device according to a seventh embodiment.

FIG. 37 is a schematic diagram for explaining the method for manufacturing the semiconductor device according to the seventh embodiment.

FIG. 38 is a schematic sectional view of a semiconductor device according to an eighth embodiment.

FIG. 39 is a schematic sectional view of a semiconductor device according to a ninth embodiment.

FIG. 40 is a schematic sectional view of a semiconductor device according to Example 10.

FIG. 41 is a schematic sectional view of a semiconductor device according to Example 11;

FIG. 42 is a schematic sectional view of a semiconductor device according to Example 12.

FIG. 43 is a circuit configuration diagram for describing a semiconductor memory device.

FIG. 44 is a circuit configuration diagram of the semiconductor memory device according to Embodiment 13.

FIG. 45 is a circuit configuration diagram of a semiconductor memory device according to another embodiment.

FIG. 46 is a schematic top view of a semiconductor memory device according to Embodiment 14 of the present invention.

FIG. 47 is a schematic sectional view of a semiconductor memory device according to Embodiment 14;

FIG. 48 is a schematic sectional view of a semiconductor memory device according to Example 14;

FIG. 49 is a schematic top view of a semiconductor memory device according to Embodiment 15.

FIG. 50 is a schematic sectional view of a semiconductor memory device according to Embodiment 15 of the present invention.

FIG. 51 is a schematic top view of a semiconductor memory device according to Embodiment 16 of the present invention.

FIG. 52 is a schematic cross section taken along line X ₃ X ₃ ′ in FIG. 51.

FIG. 53 is a schematic top view of a semiconductor memory device according to Embodiment 17 of the present invention;

FIG. 54 is a schematic sectional view taken along line X ₃ X ₃ ′ in FIG. 53.

FIG. 55 is a schematic sectional view for explaining an example of a semiconductor memory device according to Example 18;

FIG. 56 is a schematic sectional view for explaining an example of a semiconductor memory device according to Example 18;

FIG. 57 is a schematic sectional view for explaining an example of a semiconductor memory device according to Example 18;

FIG. 58 is a schematic sectional view for explaining an example of a semiconductor memory device according to Example 18;

FIG. 59 is a schematic sectional view showing an example of a semiconductor memory device according to Example 18;

FIG. 60 is a schematic sectional view showing an example of a semiconductor memory device according to Example 18;

FIG. 61 is a schematic sectional view showing an example of a semiconductor memory device according to Example 18;

FIG. 62 is a schematic sectional view showing an example of a semiconductor memory device according to Example 18;

FIG. 63 is a schematic sectional view of a semiconductor memory device according to Embodiment 19 of the present invention;

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Genzo Monma 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Ishi ▲ saki ▼ Akira 3-30 Shimomaruko, Ota-ku, Tokyo JP-A-2-125667 (JP, A) JP-A-2-263473 (JP, A) JP-A-57-130464 (JP, A) JP-A-63-125 306653 (JP, A) JP-A-1-253959 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8246 H01L 27/112 H01L 29/78

Claims (7)

(57) [Claims] 1. A semiconductor device comprising: a plurality of main electrode regions provided along a main surface of a substrate; a channel region provided therebetween; and a gate electrode provided to the channel region via a gate insulating film. An insulated gate transistor having at least two opposing portions where the gate electrode opposes each other; and an electrically destructible memory element provided on one of the main electrode regions. The gate electrode and a high impurity concentration semiconductor region provided adjacent to the channel region surround at least the entire surface of the channel region along a carrier moving direction, and the high impurity concentration semiconductor region of the channel region and On the opposite side, a second high impurity concentration semiconductor region having the same conductivity type as that of the channel region and having a higher impurity concentration than the channel region is provided. The semiconductor memory device, characterized in that. 2. The semiconductor memory device according to claim 1, wherein the memory element has a semiconductor layer, and performs writing by breaking a junction between the semiconductor layer and another adjacent layer. 3. A semiconductor device comprising: a plurality of main electrode regions provided along a main surface of a substrate, a channel region provided therebetween, and a gate electrode provided to the channel region via a gate insulating film. An insulated gate transistor having at least two opposing portions where the gate electrode opposes each other; and an electrically destructible memory element provided on one of the main electrode regions. A semiconductor memory device, wherein a semiconductor region having the same conductivity type as the main electrode region and having a lower impurity concentration than the main electrode region is provided between the main electrode region and the channel region. 4. The semiconductor memory device according to claim 3, wherein the memory element has a semiconductor layer, and performs writing by breaking a junction between the semiconductor layer and an adjacent layer. 5. A plurality of main electrode regions and a channel region provided therebetween, a gate electrode provided on the channel region via a gate insulating film, and a channel region provided in contact with the channel region. A semiconductor region having the same conductivity type as above and having a higher impurity concentration than the channel region;
Comprising: an insulated gate transistor including at least two portions where the gate electrode faces each other; and an electrically destructible memory element provided in one of the main electrode regions. A semiconductor memory device characterized by the following. 6. The semiconductor memory device according to claim 5, wherein said memory element has a semiconductor layer, and performs writing by breaking a junction between said semiconductor layer and another adjacent layer. 7. A plurality of memory cells each including the transistor and the memory element are provided, the plurality of first wirings commonly connecting gate electrodes of the plurality of memory cells, and the memory element of the plurality of memory cells. Are connected in a matrix with a plurality of second wirings that commonly connect
6. The semiconductor memory device according to claim 5, wherein a power supply line is provided between said second wirings.