JPH027572A - Manufacture of non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable a large-scale EPROM cell array with a short access time to be manufactured by driving an n-type impurities into an area directly below a drain diffusion layer and a source diffusion layer except the area near a double-gated channel area by the ion implantation method with a double-gate electrode and a side wall as a mask. CONSTITUTION:A photoresist is eliminated, arsenic ions are implanted into an oxide film 30 by a thermal oxidation method, and a drain diffusion layer 31 and a source diffusion layer 32 are formed in self-alignment with a gate electrode. Then, an oxide film is accumulated over the entire surface of substrate by the gaseous phase growth method and a proper anisotropic etching is performed to allow a side wall to be formed on the side surface of the gate electrode. Then, an n-type impurities, for example phosphor, is driven into an area directly below the drain diffusion layer and the source diffusion layer excluding the area near a channel area by the ion implantation method with the gate electrode and the side wall as a mask. Then, without changing the conduction type of this area and by making low the concentration of impurities of the area, a low-concentration P-type area 34 is formed (This low-concentration P-type area will not be formed near the channel area of a transistor).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a nonvolatile semiconductor device, and in particular to a method for manufacturing a nonvolatile semiconductor device.
EFROM (Erasab 1e Prog) is composed of GMOS (Stacked Gate MOS) memory.
ramrnable Read 0nIy Me
(more) relates to a method of manufacturing an integrated circuit device.

[Prior Art] Recently, the degree of integration of this type of EPROM integrated circuit device has been improved at a remarkable rate, and devices of up to 1 Mbit are now available on the market. In addition to such an improvement in the degree of integration, there is a demand for high-speed operating products (eg, products with a short access time, that is, the time from when the address changes to when the output data is determined, for example, about 150 ns). For this reason, efforts have been made to increase the performance of peripheral transistors and reduce the resistance of word lines, and as will be described later, reducing the capacitance attached to bit lines is an effective method.

Conventionally, this type of EPROM cell array is shown in Fig. 4(a), (
b). FIG. 4(a) is a plan view of a cell array manufactured by the conventional method, and FIG. 4(b) is A of FIG. 4(a).
-A' sectional view. Further, FIGS. 5(a) to 5(e) are process cross-sectional views for explaining the conventional method of manufacturing an EPROM cell array, and the final process corresponds to FIG. 4(b). In FIG. 4(a), 101 is a field region, 102 is a control gate electrode (word line), and 2
A contact hole 104 is provided in the bit-sharing drain diffusion layer 103, and the aluminum wiring (bit line) 5
is connected to. Reference numeral 106 denotes a source region, which is not shown in the figure, but is connected to a ground wiring via a contact at a predetermined position within the array. A large number of cells as shown here are arranged to constitute the entire cell array.

Further, in FIG. 4(b), a P-type well 108 is formed on the surface of a P-type semiconductor substrate 1070, and a first polycrystalline silicon layer is formed at a predetermined position on the substrate with a first gate oxide film 109 interposed therebetween. A floating gate electrode 110 is provided,
Furthermore, on top of that, a second gate oxide film 111 is provided.
Control gate electrode 1 formed of second polycrystalline silicon layer
12 (word lines) are provided. N-type diffusion layer regions 103 and 104 are formed on the substrate surface between the gate electrodes (drain diffusion layer region, source diffusion layer region).

Furthermore, there is a correlation insulating film 113 on top of it, and a contact hole 104 is provided in a part of the drain region 103, through which the drain region and the aluminum wiring (bit line) 114 are connected. ing.

The reason why a P-type well is formed on the substrate surface with the cross-sectional structure described above is to prevent punch-through of the cell transistor, control on-current, improve write characteristics, and so on.

Next, the conventional method of manufacturing an EPROM cell array is shown in Figure 5 (
This will be explained using a) to (e). First, a P-type well 152 is formed on the surface of a P-type semiconductor substrate 151. Next, a field oxide film is formed by the usual LOCO3 method (
(not shown). Then, after forming a first gate oxide film 153 on the active region of the substrate, a first polycrystalline silicon layer 154 is formed at a predetermined position. Next, after forming a second gate oxide film 155, a second polycrystalline silicon layer 156 is formed by vapor phase growth (FIG. 5(a)). Next, after forming a photoresist 157 in a predetermined position, using this as a mask, the second polycrystalline silicon layer is etched away to form a control gate electrode (word line), and then a second gate electrode (word line) is formed. The silicon oxide film is etched away, and the first polycrystalline silicon layer is also etched away to form a floating gate electrode 159 (FIG. 5(b)).

Next, after removing the photoresist and forming an oxide film by thermal oxidation, arsenic ions are implanted, and drain diffusion N160 and source diffusion layer 16 are formed on the gate electrode and self-alignment line.
1 (FIG. 5(C)).

Next, after forming a correlation insulating film 162, a contact hole 163 is formed on the drain diffusion layer.

Next, aluminum is formed by sputtering or the like and patterned to form aluminum wiring (bit line) 164.

[Problems to be Solved by the Invention] In the conventional EPROM cell array manufacturing method described above,
As cell arrays become more integrated, the number of transistors connected to a single bit line increases, which increases the junction capacitance of the train diffusion layer that loads the bit line, resulting in an increase in access time during readout. be.

This will be explained in detail using FIGS. 6 and 7.

FIG. 6 is a circuit diagram of the cell array. A plurality of transistors, for example N transistors, are connected to the 1-bit line connected to the sense amplifier. On the drain side of the transistor here, there is inevitably a junction capacitance C between the drain diffusion layer and the P-well.
adds. Therefore, the total capacitance of NXC is attached to this bit line. As cell arrays become more highly integrated, the number of transistors connected to one bit line increases, and therefore the capacitance attached to the bit line also increases. Next, the influence of this capacity on access time will be explained using FIG. 7. Consider a case where the Y address switches at a certain time and selects the off bit ('O').

After the address is switched, the potential of the bit line increases, and the sense amplifier starts operating after reaching a certain predetermined voltage Vread, but until then, current flows transiently to the bit line. Therefore, it takes time tl to reach Vread. This tl increases as the capacitance added to the bit line increases. Next, after t1 has elapsed, it is assumed that a time t2 is required from the start of the sense amplifier operation until the output data is switched (t2 is determined by the capabilities of the peripheral circuits, etc.). That is, the access time is determined by tl+t2. From the above, the cell array becomes highly integrated. That is, it can be seen that as the number of transistors connected to one bit line increases, the additional capacitance also increases, and tl increases, so that the access time (tl+t2) becomes longer. In order to shorten the access time of a large-scale integrated EPROM cell array, it is sufficient to reduce the junction capacitance ilC between the transistor drain diffusion layer and the P-well. For this purpose, the concentration of the P-well may be reduced, but this will impair the good characteristics of the cell, such as making the transistor more likely to punch through. As described above, the conventional method of manufacturing an EPROM cell array has the disadvantage that it is not possible to reduce the junction capacitance of the drain diffusion layer and shorten the access time without impairing the cell characteristics.

[Differences between the invention and the prior art] In contrast to the above-described conventional manufacturing method, the present invention forms a drain and a source on a double gate electrode in a self-line, and then forms a sidewall on the double gate electrode. Using the double gate electrode and sidewall as a mask, impurities of a conductivity type opposite to that of the substrate are implanted into the region directly under the drain and source diffusion layers by ion implantation, thereby keeping the conductivity type of this region unchanged and reducing the impurity concentration. The difference is that there is a process to do this.

[Means for Solving the Problems] The method for manufacturing a nonvolatile semiconductor device of the present invention includes a step of forming a P-type well on the surface of a P-type semiconductor substrate, and a floating gate electrode and a control gate electrode on the substrate. A step of forming a double gate electrode using the double gate electrode as a mask, a step of introducing n-type impurities into the substrate using the double gate as a mask to form a drain diffusion layer region and a source diffusion layer region, and a step of forming a side diffusion layer on the double gate electrode. In the step of forming the wall, and using the double gate electrode and sidewall as a mask, n-type impurities are implanted by ion implantation into the region immediately below the drain diffusion layer and source diffusion layer except for the vicinity of the double gate channel region. The method includes a step of implanting the impurity into the p-type well, without changing the conductivity type, and making the impurity concentration in this region lower than the concentration in the P-type well.

[Embodiments] Next, embodiments of the present invention will be described with reference to the drawings. FIGS. 1(a) and 1(b) are a plan view of an EPROM cell array manufactured by the manufacturing method according to the first embodiment of the present invention, and a vertical cross-sectional view thereof taken along the line AA', and FIGS. (f)
1A and 1B are process diagrams illustrating a method for manufacturing the structure shown in FIGS. 1(a) and 1(b).

In FIG. 1(a), 1 is a control gate electrode (word line), 2 is a floating gate electrode, and these constitute a double gate electrode (the shaded area in the figure).

3 is a field region, 4 is a drain diffusion layer, 5 is a source diffusion layer, and the train diffusion layer is connected to an aluminum wiring (bit line) 7 via a contact hole 6. Reference numeral 8 denotes a side wall provided on the side wall of the word line 1.

Further, in FIG. 1(b), a P-type well 10 is provided on the surface of a P-type semiconductor substrate 9, and a P-type well 10 is provided at a predetermined position on the substrate.
A floating gate electrode 12 via the first gate oxide film 11,
Furthermore, a control gate electrode 14 is provided thereon with a second gate oxide film 13 interposed therebetween. A drain diffusion layer region 15 and a source diffusion layer region 16 are formed on the substrate surface between the gate electrodes. A sidewall 17 is provided on the sidewall of the double gate electrode. Also the drain region,
Directly below the source region is a P-type region with a lower concentration than the P well.

Next, a method for manufacturing an EPROM cell array according to the present invention will be explained with reference to FIG. A P-type well 22 is formed on the surface of a P-type semiconductor substrate 210. Next, a field oxide film is formed by the usual LOCO9 method (not shown in the figure). Next, after forming a first gate oxide film 23 on the active region of the substrate, a first polycrystalline silicon N24 is formed and patterned. Next, the second gate oxide film 2
5, a second polycrystalline silicon layer 26 is formed (FIG. 2(a)). Next, after forming a photoresist 27 in a predetermined position, using this as a mask, the second polycrystalline silicon layer, the second gate oxide film, and the first polycrystalline silicon layer are sequentially etched away to form a floating gate. electrode 28,
A control gate electrode 29 (word line) is formed (see FIG. 2 (
b)).

Next, the photoresist is removed and the oxide film 3 is removed by thermal oxidation.
Arsenic ions are implanted into the gate electrode to form a drain diffusion layer N31 and a source diffusion layer 32 in the gate electrode and self-alignment line (FIG. 2(C)). The steps up to this point are the same as the conventional manufacturing method. Next, for example, an oxide film is deposited on the entire surface of the substrate by a vapor phase growth method, and a sidewall is formed on the side surface of the gate electrode by performing appropriate anisotropic etching. Next, an n-type impurity, such as phosphorus, is implanted by ion implantation using the gate electrode and sidewalls as a mask.
The implantation is accelerated to 50 keV and implanted at a dose of 1×1011012C into the region immediately below the drain diffusion layer and source diffusion layer, excluding the vicinity of the channel region, without changing the conductivity type of this region and reducing the impurity concentration of this region (e.g. IX
10'θcm-3 to 1 x 1017cm-3) to create a low-concentration P-type head area (e.g. I
~ ] x 10"cm-3) 34 (this low concentration P-type head region is not formed near the channel region of the transistor). Next, by vapor phase epitaxy on the substrate. After forming the correlation insulating film 35, a contact hole 36 is formed on the drain and diffusion N32 (second
Figure (e)). Next, an aluminum wiring (bit line) 37 is formed and connected to the drain diffusion layer.

In the above embodiments, the reason why ions are implanted after providing sidewalls on the floating gate electrode and the control gate electrode is as follows. When n-type impurities are ion-implanted using only the control gate electrode as a mask without sidewalls, the impurities implanted in the subsequent heat treatment always spread laterally to some extent. If this implanted impurity reaches the channel region of the transistor, the characteristics of the cell transistor will be impaired. If ion implantation is performed after forming the sidewalls, the n-type impurity will be implanted at a certain distance from the channel region, so this will not affect the channel region. Therefore, P under the drain diffusion layer can be removed without affecting the transistor characteristics.
This makes it possible to lower the well concentration and lower the capacitance between the drain diffusion layer and the well.

FIG. 3 is a longitudinal sectional view of the second embodiment of the present invention, and corresponds to FIG. 2(d) of the first embodiment. In this embodiment, after forming the source and drain, the side walls and upper part of the gate electrode are covered with photoresist, and using this as a mask, n-type impurity ions are implanted. After the implantation, the photoresist is removed, and the rest of the process is the same as in the first embodiment. This embodiment has the advantage that the width of the sidewall can be easily controlled. Furthermore, since the maskability for ion implantation is improved, it becomes possible to implant n-type impurities with higher energy.

[Effects of the Invention] As explained above, the present invention forms a drain diffusion layer and a source diffusion layer in a self-line for a double gate electrode, and then forms a sidewall on the double gate electrode. Using the electrode and sidewall as a mask, impurities of the opposite conductivity type to the substrate are implanted into the region directly under the train/source diffusion, excluding the vicinity of the channel, by ion implantation.
By keeping the conductivity type in this region unchanged and lowering the impurity concentration to form a P-type head region with a lower concentration than the P-well, the EPROM cell has a lower junction capacitance of the beta-train diffusion layer than a conventional EPROM cell. Since cells can be manufactured, and the capacitance attached to the bit line can be kept small even in large scale integration, it is possible to manufacture an EPROM cell array that is highly integrated and has a short access time compared to conventional EPROM cell arrays.

[Brief explanation of the drawing]

FIG. 1(a) shows an E manufactured according to the first embodiment of the present invention.
The plan view of the PROM cell array, FIG. 1(b) is its A-
2(a) to 2(f) are process diagrams explaining the manufacturing method of the E F R0M cell array according to the first embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along the line A'. The sectional view to be explained, FIG. 4(a), is an EP manufactured by a conventional method.
A plan view of the R0M cell array, FIG. 4(b) is A-A.
' Line cross-sectional views, Figures 5 (a) to (e) are conventional EFROM
A process diagram explaining the array manufacturing method, Figure 6 is EPRO
FIG. 7 is a circuit diagram showing a portion between one bit line of an M cell array, and is a graph illustrating the access time of an EPROM integrated circuit. 1, 14. 29°112.158...Control gate electrode, 2, 12.
28゜110.159...Floating gate electrode, 3.101...
...Field area, 4, 15. 32°103.160...Drain diffusion layer, 5, 16.
31゜106.161...Source diffusion layer, 6.36゜104.163...Contact hole? , 37
．． 5゜114.164...Aluminum wiring, 8.17.33...Side wall, 35゜18゜24゜26゜27゜30 ・ 38 ・ 113゜34 ・ ・ 154 ・ 156 ・ 157 ・ 62 ・・- Correlation insulating film, - Low concentration P-type head region, - First polycrystalline silicon layer, - Second polycrystalline silicon layer, - Photoresist, - Oxide film, - Mask material. 9.21° 107.151... P-type semiconductor substrate, 10.22° 108.152... P-type well, 11.23° 109.153... First gate oxide film, 13.25
゜

Claims (1)

[Claims] A nonvolatile memory cell integrated with a memory cell consisting of source and drain diffusion layers formed on a semiconductor substrate, a floating gate electrode formed above the semiconductor substrate between the diffusion layers, and a control gate electrode. A method for manufacturing a semiconductor memory device includes forming a well of the same conductivity type as the substrate on the surface of a single conductivity type semiconductor substrate, and forming a double gate electrode consisting of a floating gate electrode and a control gate electrode on the semiconductor substrate. forming a drain diffusion layer region and a source diffusion layer region by introducing impurities of conductivity type opposite to the substrate into the semiconductor substrate using the double gate electrode as a mask; A step of forming a side wall on the electrode, and using the double gate electrode and the side wall as a mask, impurities having a conductivity type opposite to that of the substrate are implanted into the region immediately below the drain diffusion layer and the source diffusion layer. 1. A method of manufacturing a nonvolatile semiconductor memory device, comprising the step of implanting a non-volatile semiconductor memory device.