JPH10189769A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate machining of a contact while enhancing the machining margin, to stabilize the resistance at a storage node contact part, to facilitate isolation while preventing deterioration of breakdown strength between diffusion layers and to reduce junction capacity and line capacity. SOLUTION: A gate electrode for semiconductor element, a power supply line, a high resistance line, and the like, are formed in multilayer on a semiconductor substrate 2. A trench 4 is then made in a region for forming a first layer line pattern corresponding to a gate electrode for semiconductor element on the surface of semiconductor substrate 2. Subsequently, an insulation layer 6 is formed on the entire surface of the surface of semiconductor substrate 2 including the trench 4 followed by formation of a single crystal silicon layer 7, serving as the diffusion layer and the channel part of the semiconductor element, on the insulation layer 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device suitable for use in a semiconductor memory such as an SRAM, for example, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 7 is a sectional view showing an interlayer structure of a memory cell portion of a typical SRAM in the 0.35 μm generation. Hereinafter, an outline of a conventional manufacturing process will be described with reference to FIG. First, for example, LOCOS
After selectively forming the isolation oxide film 124 having a (local oxidation of silicon) structure, the isolation oxide film 1 is formed.
A gate oxide film 126 is formed on the substrate surface of the element active region surrounded by 24. Then, an MO composed of a polycide layer
Gate electrode of S transistor (also serves as first wiring layer)
After forming the gate electrode 128, a low concentration diffusion layer 130 for forming a lightly doped drain (LDD) structure is formed in the element active region on both sides of the gate electrode 128. Next, after forming a sidewall 132 made of an oxide film,
A high concentration diffusion layer to be a source and a drain of the transistor is formed. After that, the first interlayer insulating film 136
Is formed over the entire surface by a CVD method, and a first connection hole 138 that reaches the source and drain of the MOS transistor and the high concentration diffusion layer where the ground line is to be formed. Next, a second wiring layer 140 is formed of a polycide layer through the first connection hole 138, and the second interlayer insulating film 1 is formed.
42 is formed on the entire surface.

Next, the second interlayer insulating film 142 and the first
The second connection hole 1 is formed in the interlayer insulating film 136 by etching.
The third wiring layer 150 including the high-resistance load element is formed on the second interlayer insulating film 142. Next, a third interlayer insulating film 152 is formed on the entire surface, and further a Si ₃ N ₄ layer 1 for preventing infiltration of moisture into the high-resistance element.
54 are formed. Then, after forming a fourth interlayer insulating film 156 on the Si ₃ N ₄ layer 154, the fourth interlayer insulating film 156 is planarized.

Thereafter, a third connection hole 158 is opened to connect the second wiring layer 140 and the bit line. Next, a Ti / TiN layer 160 is sequentially formed on the entire surface by a sputtering method, then a tungsten layer is formed on the fourth interlayer insulating film 156 including the third connection hole 158, and a buried tungsten layer is formed by etch back on the entire surface. 162 are formed. Next, Ti / T is formed on the fourth interlayer insulating film 156.
The iN layer and the aluminum-based alloy layer are formed by a sputtering method, and are patterned to form a fourth wiring layer 164 which is a bit line. Then, an overcoat film 166 is formed on the entire surface.

[0005]

Since a conventional semiconductor device, particularly a semiconductor device configured as an SRAM, is configured as described above, a transistor gate electrode, a power supply wiring, a high resistance wiring and the like are formed on a silicon substrate. Therefore, there is a problem that a wiring film thickness step occurs in the third-layer wiring structure, and that wiring processing of an upper layer becomes difficult. Further, the PPL process used for element isolation of a conventional semiconductor device has a capacity of 0.1 mm.
From the 35-micron generation onward, there is a problem that it becomes difficult to secure an element isolation margin with respect to process variations, which hinders miniaturization. In addition, since the diffusion layer is formed on the surface of the silicon substrate, the junction capacitance and the wiring capacitance increase, which adversely affects the high-speed operation of the semiconductor device. There has been a problem that the withstand voltage between the drains may be reduced.

Accordingly, an object of the present invention is to increase a processing margin and facilitate contact processing, stabilize the resistance of a storage node contact portion, facilitate isolation between elements, prevent a decrease in breakdown voltage between diffusion layers, and reduce junction capacitance and wiring. An object of the present invention is to provide a semiconductor device capable of reducing the capacity, realizing high density and high speed operation, and a method for manufacturing the same.

[0007]

According to the present invention, there is provided a semiconductor device having a structure in which a gate electrode, a power supply wiring, a high resistance wiring, and the like for a semiconductor element are formed in multiple layers on a semiconductor substrate. A groove is formed in a first-layer wiring pattern formation region corresponding to a semiconductor element gate electrode on the surface of the semiconductor substrate.

According to the present invention, a driver transistor and an access transistor of a first conductivity type are provided on a semiconductor substrate;
A method of manufacturing a semiconductor device for forming a memory cell comprising a high resistance load element transistor of a second conductivity type, comprising forming a groove in a formation region on the semiconductor substrate corresponding to a gate electrode pattern of the driver transistor and the access transistor. A first step of forming, a second step of forming an insulating film on a surface of the semiconductor substrate including the groove, and a diffusion part for drain and source of the driver transistor and the access transistor on the insulating film corresponding to the groove. A third step of forming a single-crystal silicon layer for forming a channel portion and a fourth step of forming a gate electrode in a channel portion of the driver transistor and the access transistor by a first-layer wiring pattern; Interlayer insulating film on the driver transistor and the access transistor formed with Forming a second wiring pattern and forming a contact with the drain / source diffusion portion of the access transistor; and forming an interlayer insulating film covering the second wiring pattern. A sixth step of forming a third-layer wiring pattern serving as the high-resistance load element and power supply wiring on an insulating film, and forming a contact between the diffusion portion of the access transistor and a gate electrode; and an interlayer covering the third-layer wiring pattern. After forming an insulating film, a seventh step of forming a bit contact connected to the second layer wiring pattern on the interlayer insulating film by using a tungsten plug contact, and an eighth step of forming the bit wiring pattern And a process.

In the semiconductor device and the method of manufacturing the same according to the present invention, a groove is formed on the surface of the semiconductor substrate corresponding to the first layer wiring pattern corresponding to the gate electrode of the semiconductor element such as a driver transistor and an access transistor. In the wiring processing of the upper layer portion in the case of the structure, the step of the base becomes small, which is advantageous in terms of processing margin and the like. Further, since the height of the diffusion layer and the height of the first layer wiring pattern can be made substantially equal, the contact processing becomes easy.
Further, the insulating film formed below the channel of the transistor effectively prevents the resistance of the diffusion layer from being reduced due to out diffusion of the impurity of the diffusion layer. Further, it becomes possible to completely perform element isolation of a transistor or the like by using an insulator, thereby improving the breakdown voltage between the diffusion layers and easily increasing the density of the element. The channel of a transistor formed of a single crystal silicon film by an epitaxial method reduces well resistance and prevents formation of a parasitic thyristor.

[0010]

Next, embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described. FIG.
6 to FIG. 6 show a high resistance load type SRA according to the manufacturing method of the present invention.
FIG. 14 is a cross-sectional view illustrating an example of a manufacturing process of the memory cell unit of M.

First, in FIG. 1A, a first layer wiring pattern corresponding to a gate electrode pattern of a driver transistor and an access transistor constituting a memory cell portion of a high resistance load type SRAM is formed on a surface of a Si substrate 2. After opening the portion with a resist, a groove portion 4 is formed by isotropic etching or the like. The depth of the groove 4 is set to be equal to the first layer wiring thickness (140 to 300 nm), and the groove is formed so that the lateral taper amount of the groove and the depth of the groove are equal. Next, as shown in FIG. 1B, an insulating film 6 made of SiO is formed on the surface of the Si substrate 2 including the groove 4 by CVD, for example, to a thickness of 100 nm.

Next, in FIG. 2A, an N-type single-crystal silicon film 7 is formed on the insulating film 6 by a laser annealing method.
For example, after being formed to a thickness of 100 nm, boron is selectively ion-implanted into the NMOS formation region of the single crystal silicon film 7 to form the P well region 8 of the driver transistor and the access transistor in the N-type epitaxial single crystal silicon film. . Further, in the element isolation region of the P well region 8 of the driver transistor, patterning is performed by PR / ET (photoresist / etching) using LP-SiN (silicon nitride at low pressure) as a mask, and the SiO ₂ film 10 is formed by oxidation. Form. Then, FIG.
As shown in (b), after forming a gate oxide film 12 on the surface of the P well region 8, a first polysilicon layer 14 (70 to 150 nm thick) and a first silicide layer 16 (70 to 150 nm thick) are formed. 150 nm) by a CVD method or a sputtering method.
The gate electrode 16 of the MOS transistor of the layer wiring is formed. Thereafter, an N-type low-concentration impurity region 1 for forming an LDD structure in the element active region on both sides of the gate electrode 16 is formed.
8 is formed by ion-implanting arsenic in a self-aligned manner with the gate electrode. Similarly, P-type low-concentration impurity regions 20 are formed by injecting low-concentration boron into a PMOS formation region and a power supply (Vss) line contact portion of a peripheral circuit.

Next, in FIG. 3A, after forming a sidewall 22 on the gate side wall, high-concentration arsenic is ion-implanted into the N-type low-concentration impurity region 18 to form an N-type source / drain. Is formed, and an NMOS transistor having an LDD structure is formed. Similarly, by implanting boron into the P-type low-concentration impurity region 20 and the power supply (Vss) line contact portion of the peripheral circuit, a P-type high-concentration source / drain diffusion layer 26 is formed. Next, in FIG. 3B, a first interlayer insulating film 28 is formed, and a Vss line contact and a bit contact hole 30 for a diffusion layer and a second-layer wiring are formed.

Next, in FIG. 4A, a second polysilicon layer 32 (60 to 60 nm in thickness) and a second polysilicon layer 32 are formed on the first interlayer insulating film 28 and the wiring Vss line contact and the bit contact hole 30. A silicide layer 34 (thickness: 60 to 80 nm) is sequentially formed by a CVD method or sputtering to form a second-layer wiring 36 serving as a Vdd line composed of a polycide layer, and to form a second layer wiring 36 on the polysilicon layer 32 and the polycide layer 34. Bit contact pad 4
0 is formed. Next, in FIG. 4B, after a second interlayer insulating film 42 is formed on the entire surface, in order to connect the high resistance load resistance element constituting the SRAM and the diffusion layer 26 as a storage node, a second step is performed by lithography technology. A connection hole is formed in the second interlayer insulating film and the first interlayer insulating film. Thereafter, on the second interlayer insulating film 42, a polysilicon layer 46 also serving as a high-resistance load resistance element and a third-layer wiring serving as a Vdd line is formed, and BF2 + or phosphorus is ion-implanted into the polysilicon layer 46. After patterning. Also, the power supply (Vd
d) Boron is implanted into the line contact portion to form a P-type high-concentration impurity region, and a third-layer wiring, a high-resistance load resistance element, and a Vdd line are formed.

Next, in FIG. 5, a third interlayer insulating film 4 is formed.
8 is formed on the entire surface, and then a Si ₃ N ₄ based antireflection film 50 is formed.
To form Then, BPSG is formed on the anti-reflection film 50.
After forming a fourth interlayer insulating film 52 of 300 to 700 nm, annealing is performed at a temperature of 850 to 900 ° C., and a flattening process is performed by reflow. Next, in FIG. 6, the fourth interlayer insulating film 52 and the third interlayer insulating film 48 are connected to connect to the second-layer wiring 38 of the bit contact pad 40.
Then, a bit contact hole 54 is formed in the second interlayer insulating film 42. Thereafter, Ti is deposited on the entire surface of the fourth interlayer insulating film 52.
/ TiN layer 56 is formed by a sputtering method, and then a fourth interlayer insulating film 52 including a bit contact hole 54 is formed.
A tungsten layer is formed in the Ti / TiN layer 56, and a tungsten layer 58 is formed in the bit contact hole 54 by etch-back. Next, the fourth interlayer insulating film 52
An aluminum-based alloy layer is formed thereon by sputtering, and is patterned to form a bit wiring layer 60 as a bit line. Reference numeral 62 denotes an anti-reflection film formed on the bit wiring layer 60.

As described above, in the semiconductor device of the present embodiment, the trench 4 is formed in the gate electrode pattern formation region of the memory transistor driver transistor and the access transistor of the high resistance load type SRAM formed on the silicon substrate 2. After forming an insulating film 6 on the entire surface of the silicon substrate 2 including the groove 4, a driver transistor and an access transistor constituting a memory cell portion of the SRAM are formed on the insulating film 6. The level difference in the formation of the second and third wiring layers can be significantly reduced as compared with the conventional semiconductor device, and the processing margin can be increased. Further, the depth of the groove 4 is substantially the same as the height of the diffusion layer and the first layer wiring, so that the contact processing is facilitated, and since the diffusion layer of the storage node contact portion hangs over the edge of the groove, the contact contact is made. This has the effect of increasing the area and stabilizing the resistance value. Further, since the insulating film 6 is formed under the channel region of the MOS transistor, the resistance of the diffusion layer is hardly reduced due to the outdiffusion of the impurity of the diffusion layer. , And the density of the memory cells can be easily increased. Further, by forming the channel region of the MOS transistor with a single crystal film by an epitaxial method, well resistance can be reduced, a parasitic thyristor can be eliminated, and parasitic capacitance (junction capacitance and wiring capacitance) can be reduced. Enables high-speed operation.

In the above example, the case where the present invention is applied to an SRAM has been described. However, the present invention is not limited to an SRAM, but can be applied to a DRAM and other semiconductor devices.

[0018]

As described above, according to the present invention, a groove is formed in a region for forming a first layer wiring such as a gate electrode pattern for a semiconductor element having a multilayer wiring structure formed on a semiconductor substrate. Since an insulating film is formed on the entire surface of the semiconductor substrate including the groove, and a semiconductor element such as an SRAM is formed on the insulating film, the level difference between the underlying layers in forming the second and third wiring layers is greatly reduced. And the processing margin can be widened. Further, the depth of the groove is substantially the same as the height of the diffusion layer and the first layer wiring, so that the contact processing is facilitated, and the diffusion layer of the storage node contact portion is applied to the edge of the groove, so that the contact contact area is reduced. And the resistance value can be stabilized. Further, when the semiconductor element is a MOS transistor, an insulating film is formed under the channel region, so that the resistance of the diffusion layer is unlikely to be reduced due to out-diffusion of the diffusion layer impurities, and complete isolation by the insulating film is achieved. Is easy and the breakdown voltage between the diffusion layers can be improved.
It is easy to increase the density of memory cells. Further, when the semiconductor element is a MOS transistor, the channel region is formed of a single crystal film by an epitaxial method, so that the well resistance can be reduced, the parasitic thyristor can be eliminated, and the parasitic capacitance can be reduced. The effect is that the speed can be increased.

[Brief description of the drawings]

FIGS. 1A and 1B are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to the present invention.

FIGS. 2A and 2B are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to the present invention.

FIGS. 3A and 3B are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to the present invention.

FIGS. 4A and 4B are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the present invention.

FIG. 6 is a sectional view illustrating an example of a manufacturing process of the semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

[Explanation of symbols]

2 ... silicon substrate (semiconductor substrate), 4 ... groove, 6 ...
... Insulating film, 7 single crystal silicon film, 8 well region (channel), 14 polysilicon layer, 16 gate electrode (polycide layer, first layer wiring), 24 diffusion layer ( Nch-source / drain region), 26 diffusion layer (Pch-source / drain region), 28 first interlayer insulating film, 32 polysilicon layer, 34 polycide layer, 38 second Layer wiring, 42... Second interlayer insulating film, 46... Polysilicon layer (third layer wiring), 48.
... Third interlayer insulating film, 52... Fourth interlayer insulating film, 54
... bit contact holes, 58 ... buried tungsten layers, 60 ... bit wiring layers.

Claims (5)

[Claims] 1. A semiconductor device having a structure in which a gate electrode, a power supply wiring, a high resistance wiring, and the like for a semiconductor element are formed in multiple layers on a semiconductor substrate, the semiconductor device corresponding to a gate electrode for a semiconductor element on a surface of the semiconductor substrate. A semiconductor device, wherein a groove is formed in a first-layer wiring pattern formation region. 2. The semiconductor device according to claim 1, wherein an insulating film is formed on the entire surface of the semiconductor substrate including the groove portion, and a single crystal silicon layer serving as a diffusion layer and a channel portion of the semiconductor element is formed on the insulating film. 13. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 2, wherein said semiconductor element is a first conductivity type driver transistor and an access transistor constituting a memory cell. 4. The semiconductor device according to claim 2, wherein said channel portion is formed by ion implantation by an epitaxial method into said single crystal silicon layer. 5. A method for manufacturing a semiconductor device, comprising: forming a memory cell on a semiconductor substrate comprising a driver transistor and an access transistor of a first conductivity type and a high-resistance load element transistor of a second conductivity type; A first step of forming a groove in a formation region corresponding to a gate electrode pattern of the driver transistor and the access transistor on a substrate; a second step of forming an insulating film on a surface of a semiconductor substrate including the groove; A third step of forming a single-crystal silicon layer for forming a drain / source diffusion portion and a channel portion of the driver transistor and the access transistor on an insulating film corresponding to the trench; and a channel portion of the driver transistor and the access transistor. A fourth step of forming a gate electrode using a first layer wiring pattern A fifth step of forming an interlayer insulating film and a second layer wiring pattern on the driver transistor and the access transistor on which the gate electrode is formed, and forming a contact with a drain / source diffusion portion of the access transistor; After forming an interlayer insulating film covering the second layer wiring pattern, a third layer wiring pattern serving as the high resistance load element and the power supply wiring on the interlayer insulating film, and a diffusion portion of the access transistor and a gate electrode. 6th forming contact
Forming an interlayer insulating film covering the third layer wiring pattern, and forming a bit contact connected to the second layer wiring pattern on the interlayer insulating film using a tungsten plug contact. A method of manufacturing a semiconductor device, comprising: a step; and an eighth step of forming the bit wiring pattern.