JPH0595093A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device having a constitution just suitable for fine processing and ensuring high speed operation only with a low power consumption by giving two opposed portions to a gate electrode and providing electrically destructible memory elements to the one area of the main electrode region. CONSTITUTION:Transistors 1035 and 1035' are isolated by a vertical plane, providing a buried interlayer insulating film 1015 therebetween. The isolation width can be narrowed and a gate electrode 23 is arranged opposing to the side wall. Thereby, a large current can be applied while the transistors are in the ON state. Moreover, the conductive and non-conductive conditions of memory can be regulated by breakdown or non-breakdown of an insulating film 1031' provided on a source 1030. The insulating layer 1031' is connected with a bit line wiring 1032 via a contact region 1033. Accordingly, high speed operation can be realized only with a low power consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used for electronic circuits in all kinds of technical fields such as automobiles, power stations, space satellites, as well as OA equipment such as copiers, facsimile machines, printers, video cameras, home electric appliances. The present invention relates to a semiconductor device.

In particular, the present invention relates deeply to a semiconductor memory device that stores the necessary information signals.

[0003]

2. Description of the Related Art FIG. 1 shows the structure of a semiconductor memory in which a storage program is possible only once. This is composed of a memory cell having a MOS field effect transistor (hereinafter referred to as “MOSFET”) as an insulated gate field effect transistor and an insulating film.

Such a memory is, for example, an "A Ne"
w Programmable Cell Utility
zing Insulator Breakdown ”
IEDM'85, pp 639-642.

Another type of semiconductor memory is shown in FIG.

FIG. 2 is a sectional view thereof, and 120 is n.
Mold substrate, 121 is p ⁺ train, 122 is p ⁺ source, 1
23 is a floating gate, 124 is an insulating layer, 125
Is a drain wiring, and 126 is a source wiring. This 12
The floating gate of No. 3 is manufactured by, for example, burying polycrystalline silicon in a silicon oxide film.

In the normal state, the source and the drain are non-conductive. By applying a negative high voltage between the source and drain of this transistor, avalanche breakdown of the pn junction on the drain side, high energy electrons generated at this time are injected into the floating gate, and the source and drain are made conductive. You can write. When this element is used as a memory, whether or not to inject charges into the floating gate is associated with 1 and 0 of information. However, this type of memory has a problem that the charge accumulated in the floating leaks slightly, so that it is not possible to retain the permanent information and the read characteristic changes with time.

Moreover, the above-described MOSFET is not suitable for miniaturization, and has a problem in that the mutual conductance is small (gm characteristic).

Moreover, the gate length is 0.5 μm for miniaturization.
The following MOSFETs based on the scaling law
Can't be expected to improve.

Separately from these, SiO is formed on the Si substrate.
An SOI MOSFET structure has been proposed in which _two layers are provided, a Si mesa structure is further provided, and a gate oxide film is provided on the side wall of the mesa [Japanese Patent Laid-Open No. 14578/1990].

This element structure is shown in perspective views in FIGS.
232 is an insulating film, 231 'is crystalline Si, 236 is a source region, and 237 is a drain region. A gate electrode 235 has a structure that straddles the channel region of the crystalline Si portion. FIG. 3 is a sectional view taken along the line aa 'of FIG.
As shown in FIG. 3, the crystalline Si 231 ′ portion is covered with the gate electrode 235 on the upper three surfaces through the gate oxide film 234, and the lower surface 238 is the surface of the insulating film 232. Also, the size of the crystalline Si portion, W _O <adapted to satisfy 2W _H, channel wall becomes dominant, has a structure in which the channel conductance is increased.

Further, a MOS structurally similar to the conventional example described above.
FETs have also been proposed [Japanese Patent Laid-Open No. Hei.
73].

A plan view of this example is shown in FIG. 5, and AA 'in FIG.
6 is a sectional view of FIG. 6, and FIG. 7 is a sectional view of BB ′ in FIG. 246 forms a source 243, a drain 242 and a channel. It is a crystalline Si layer. Gate electrode 24
The crystalline Si layer 246 covered with 5 is a channel region, which is the substrate 240 and the opening 247.
The drain layer 242 passes through the crystalline Si layer 246 and is connected to the substrate 240 through the opening 248.

As a result of studying each of the conventional examples described in detail above, even though the structure is as described above, there is a large amount of leakage current of the transistors, a large variation of each transistor, and the OFF characteristics of the transistors are poor, resulting in poor operation. It turned out to be stable. First, O of SOI type MOSFET
The reason why the FF characteristics deteriorate will be described. According to the knowledge of the present inventors, the cause is Si that forms a channel.
This is because the region is entirely covered with SiO ₂ which is an insulating film except for the interface with the source and drain regions. That is, the Si region of the channel portion is in a completely floating state, the potential cannot be fixed, and the operation becomes unstable. Further, when the carriers (for example, electrons in the case of p-type MOSFET) generated in the Si region are turned off when the transistor is turned on, there is no place to go and S
OF to remain in the i region until it recombines and disappears
The F characteristic becomes worse.

In the conventional transistor described above, the reason for the large amount of leak current is that the channel region surrounded by the gate electrode is in direct contact with the underlying insulating layer. In other words, this channel region is in a state of being completely depleted when the transistor is turned on, the depletion layer reaches the interface between the channel layer and the insulating layer, and a large amount of recombination current is caused by defects existing there. Because it occurs in.

Further, conventionally, there is a bipolar PROM as one of read-only memories which can be programmed (written) by a user and which can be randomly accessed. A memory cell of this type is shown in FIG. 101 is a bit line, 1
Reference numeral 02 is a word line, 103 is a bipolar transistor arranged in a memory cell, and each emitter 105 of the bipolar transistor is connected to the bit line 101 and each collector 1
The word line bases 06 are in a floating state. Further, 107 is a diode, and the word line is connected to the power supply Vcc 108 via this diode. FIG. 9 shows a sectional structure of the bipolar transistor 103 of this memory. 110 is a p-type Si substrate, 111 is n
⁺ Buried layer, 112 n ^- epi layer, 113 field oxide film, 114 p-type base, 115 n ⁺ emitter layer, and 116 Al wiring. The memory accommodates binary information by destroying the diode between the emitter and the base. FIG. 9A shows a state before writing, and FIG.
Indicates the state after writing.

Before writing, the Al wiring on the n ⁺ emitter has a flat structure as shown by 117. However, if a large current pulse is applied to the word line and the bit line during writing, aluminum and silicon Eutectic alloy 118 is the base layer 1
It goes through 14 and becomes conductive.

However, it is difficult to achieve high integration because the cell size is limited due to the separation of bipolar transistors.
Further, there is a problem in that the eutectic alloy 118 formed by a large current varies from cell to cell and stable reading characteristics cannot be obtained. Also, as a dynamic random access memory (DRAM), a surrounding gate transistor (SGT) is used as an address transistor.
A vertically long memory cell in which a trench capacitor is formed in the main electrode region on the substrate side is proposed.

According to the knowledge of the present inventors, such D
It has been found that the RAM has the following problems. As high integration of 16 megabits or more and miniaturization of cells are advanced, the capacitor size is limited and the capacitance becomes small, so that a large signal charge cannot be stored. On the other hand, in the wiring, the parasitic capacitance increases with the miniaturization. Then, when the stored signal is read out by the capacity division, the finally output signal becomes small and the SN ratio also becomes small. Therefore, the memory malfunctions.

Further, since the structure is vertically long, the manufacturing process is extremely complicated, the yield is not increased, and it is difficult to achieve commercial success. That is, the present inventors have come to the conclusion that the fine transistor such as SGT does not meet the initial purpose of application to DRAM in the current technology.

[Object] The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a semiconductor memory device having a structure suitable for fine processing and capable of operating at high speed with low power consumption. ..

Another object of the present invention is to provide a semiconductor memory device having a memory function capable of stably obtaining an accurate write operation and capable of performing a high-speed and accurate read operation.

An object of the present invention is to provide a plurality of main electrode regions provided along the main surface of a substrate, a channel region provided between the main electrode regions, and a gate provided to the channel region via a gate insulating film. An insulated gate transistor having an electrode, the gate electrode having at least two facing portions facing each other, and an electrically destructible memory element provided in one of the main electrode regions. This is achieved by a semiconductor memory device characterized by being provided.

[0024]

According to the present invention, since the electric field strength in the vertical direction with respect to the carrier moving direction is small due to the two gate electrodes facing each other, a semiconductor device having high mobility and high gm characteristics can be obtained, and hot carriers are generated by the electric field relaxation. Can be prevented and the reliability of the device is improved over the life of the device.

Since the capacitance of the Si portion under the gate oxide film decreases, the S factor (Subthreshold)
d swing) characteristics are improved, and the leak current is extremely reduced.

Further, the area occupied by the elements is reduced and high integration can be realized.

By further improving the present invention, a region having a conductivity type different from the conductivity type of the source drain section and having a higher impurity concentration than the channel region is provided in a portion other than a portion where two opposing gate electrodes are provided in the channel region. However, by adopting a structure in which the impurity concentration is not inverted by the drive voltage applied to the gate when the transistor is driven, the transistor O
At the time of N / OFF, minority carriers (holes in N-channel MOS, electrons in P-channel MOS) move in and out of the semiconductor layer sandwiched between two facing gate electrodes quickly, and the switching characteristics are improved. ..

Further, due to this high concentration layer, even if the channel region is completely depleted when the transistor is ON, the depletion layer does not reach the underlying insulating layer, and dark current generation is suppressed.

Further, when miniaturization of 0.1 μm level is advanced, it is necessary to adapt to the low temperature operation of the liquid nitrogen temperature level, but even if this low temperature operation is performed and carrier is frozen, compared with the conventional case, The increase in parasitic resistance and the decrease in drain current are extremely small.

(Description of preferred embodiments) As one of preferred embodiments of the present invention, a gate electrode has at least opposing portions sandwiching a channel region, and a junction with a source region or a drain region in the channel region is provided. A part of the other part except the part has a transistor provided in contact with the channel region and a doped region in which minority carriers can be transferred, and a semiconductor memory including a destructible insulating layer as a memory element will be described as an example. To do.

In the channel region of the semiconductor device according to the present invention, the width (d ₃ ) in the direction of the facing portion of the channel region sandwiched between the facing portions of the gate electrode and the impurity concentration of the semiconductor in the channel region are determined as follows. To be done. That is, even when the gate voltage is OFF, the depletion layers extending from both sides of the facing portion are connected to each other so that the depletion layer is connected and depleted. Specifically, if the width of the channel region in the direction of the facing portion of the gate electrode is d ₃ and the width of the depletion layer extending from both sides in the same direction is W, the relationship of d ₃ ≦ W is satisfied. This is because if the channel region between the opposite electrodes is completely depleted, the electric field applied to the inside of the channel region is alleviated even if the gate voltage is raised to the level at which the inversion layer is formed, and the device characteristics are improved. To do.

The doped region may be a semiconductor region having a conductivity type different from that of the source and drain regions and having a higher impurity concentration than that of the channel region, and the type and conductivity type of the impurities are limited. is not. Specifically, the impurity concentration in the doped region is set to a concentration at which the doped region is not inverted by the driving voltage applied to the gate when driving the transistor. Functionally, the structure may be such that carriers from the channel region sandwiched between the facing portions of the gate electrode can be received.

The material used for the gate electrode of the present invention includes metal, polycrystalline silicon, silicide, polycide, etc. Specifically, Al, W, Mo, Ni, C
o, Rh, Pt, Pd itself, or a silicide or polycide thereof, which is appropriately selected in consideration of the structure of the MOSFET, driving conditions and the work function thereof.

Further, the shape of the gate electrode and the doped region is such that there is no gate electrode in the portion facing the doped region, or that the same doped region is formed, or as in the embodiment described later, A part of the gate electrode is also arranged in a portion facing the region. Furthermore, the cross-sectional shape of the channel region when cut in the direction perpendicular to the carrier movement direction is a square shape such as a quadrangle so that the three surfaces are surrounded by the gate electrode and the remaining portion is in contact with the doped region. Is preferred. The side may be a side having a curvature instead of an accurate straight line, or each edge portion at that time may be chamfered in consideration of the coverage of the gate insulating film.

As a transistor suitable for the special memory device of the present invention, as will be shown in each embodiment described later, a MOSF is used.
It is preferable that the ET element is of a type that is laid on the substrate and is in contact with the doped region on the substrate side, and that the facing portion of the gate electrode has a surface that intersects the substrate surface.
In addition, the facing portion of the gate electrode may be arranged substantially parallel to the substrate surface and the side surface may be provided with a doped region, but in consideration of the current manufacturing process, the former, that is, each embodiment described later. Is preferable.

For example, H. tadat, K .; sunou
shi, N.N. Okave, A .; Nitayama, K .;
Hieda, F.M. Horiguchi, and F.M. M
asue IEDM (International
(Electron Device Meeting)
(1988) PP222-225 with source and drain provided through the channel above and below.
Surroudin with two gate electrodes facing each other
g Gate transistor (SGT) is known.

On the other hand, in the transistor of the present invention, the source and drain are formed in front of and behind the two gate electrodes facing each other in the lateral direction.
A drain is provided.

By adopting this structure, the source / drain electrodes can be easily formed on the same plane as in the conventional MOSFET. In addition, the channel length is
Since it is determined by the gate electrode width similarly to the SFET, the channel length processing accuracy is high. Further, patterning of a semiconductor for forming two gate electrode structures that are placed horizontally and opposed to each other can be performed by maskless lithography, and the structure is suitable for miniaturization. As a result, the distance between the two gate electrodes can be narrowed, punch-through can be prevented without increasing the impurity concentration, and high gm characteristics can be obtained even with higher integration.

Next, as a transistor suitable for the present invention, a MOSFET element is of a type that is laid on the substrate, and the MOSFET element is in contact with the doped region on the substrate side, and the facing portion of the gate electrode intersects the substrate surface. The reason why the shape arranged so as to have a surface to be formed is good is that the conventional MO described above is used.
Description will be made in comparison with SFET.

In both conventional MOSFETs, at least a part of the channel region is formed in contact with the underlying insulating layer. This causes the following problems.

First, there is a large leak current due to the generation of dark current. In the structure of FIG. 13, the channel region 231 ′ made of silicon is surrounded by the surface 238 of the insulating film 232 and the gate oxide film. When the transistor is turned on, the voltage applied to the gate depletes the entire channel region. As a result, it has a larger current driving capability than other transistors. However, the interface between the gate oxide film and the silicon in the channel portion has good characteristics due to recent process technology (cleaning etc.), but the interface with the insulating film has many defects and a high interface state density. Since the gate electrode is provided adjacent to the insulating layer indicated by 250, the depletion of the entire channel portion means that the depletion layer also contacts the surface 238 on the insulating layer. Therefore, when the transistor is in the ON state, holes are accumulated in this channel region if it is an n-type MOSFET. Next, even if the voltage applied to the gate is changed to turn off the transistor, as long as holes generated from the interface continue to exist in the channel part, electrons are injected from the source side by the holes, and it is quite difficult. The state that cannot be turned off continues. In other words, in a depleted MOSFET, an unnecessary carrier should not be generated as compared with a conventional MOSFET.

This phenomenon also occurs in other conventional examples. This will be described with reference to FIG. In this case, the Si single crystal portion 246 that becomes the channel region
Is connected to the substrate through the opening 247,
The channel is in a floating state, and there is no problem that there is no escape route for unwanted carriers (holes for n-type MOSFETs, electrons for p-type). However, as indicated by reference numeral 251 in FIG. 6, since the channel region is in contact with the surface of the underlying insulating layer 241 ', unnecessary carriers are generated. Therefore, to some extent, the leak current generated from the defect at the Si interface between the insulating layer and the channel region deteriorates the device characteristics.

Next, the second problem will be described. The second problem is that the effective channel width is likely to vary from transistor to transistor.

The channel width of the conventional transistor is shown in FIG.
It is determined by the height and width of the single crystal Si 231 ′ shown in FIG. Usually, this height is determined by the etching depth of Si. When manufacturing a MOSFET having a gate length of 0.1 μm and a gate width of 0.5 μm, this height is about 0.2 μm, which is why the height must be kept within 200 Å. It is extremely difficult to keep this variation range within the wafer surface or between wafers by the current dry etching method. Further, 250 of FIG.
The etching shape on the underlying insulating layer, as shown in (3), has more variation than the upper Si portion, and there is a problem that the thickness of the Si portion changes between the upper Si portion and the lower Si portion.

On the other hand, in the transistor used in the device of the present invention, the channel length is
Since the width is determined by the gate electrode width, the channel length processing accuracy is high. The channel region is defined by the gate electrode portion and the high-concentration layer directly below or above the channel, so that the variation is extremely small. Further, even if the channel portion is depleted when the transistor is ON, the depletion layer does not spread at the boundary with the high concentration layer. Therefore, since the depletion layer is not in contact with the surface of the insulating layer other than the gate oxide film (insulating film), there is no unnecessary carrier generation source.

As described above, a transistor that is finely suited and has a high current driving capability is a memory cell transistor, and the gate of this transistor is a word line.
A memory connected to the bit line is formed on the source region of this transistor through a pn junction. As a result, it is possible to realize a once-permanently writable memory having a small error rate, high density, and high-speed read / write characteristics.

[0047]

(Embodiment 1) A first embodiment of the present invention will be described in detail with reference to FIG. FIG. 10 is a top view of the memory cell of the first embodiment of the present invention. 1001,
1001 ′ is a word line, 1002 and 1002 ′ are bit lines, 1003 and 1003 ′ are power supply lines, 1004 is a Si single crystal as a semiconductor active region that operates as a switching transistor in a memory cell, and 1005 is a power supply line and a drain layer. Contact region, 1006 is the drain layer of the transistor, 1007 is the gate portion of the transistor, 1008 is the source layer of the transistor, 100
Reference numeral 9 is an electrically destructible insulating layer provided between the source layer and the bit line. X ₁ , X ₁ ′, X ₂ , shown in FIG.
Cross-sectional views of X ₂ ′, X ₃ , X ₃ ′, Y, and Y ′ are shown in FIG.
14 to 14. In FIG. 11, 1012 is p-type Si
For example, a substrate having a resistivity of several Ωcm is used.
1013 is a p ⁺ type buried layer, 1014 is a field oxide film, 1015 is an interlayer insulating film, and PSG, BPSG, S
iN, SON, etc. can be used. Reference numeral 1016 is a p-type layer provided immediately below the drain, 1017 is a drain n ⁺ high-concentration layer, and 1018 is a drain power supply wiring connected to the drain layer 1017 via a contact portion 1019 in the figure. The correspondence between FIG. 10 and this FIG. 11 is the drain layer 1 of FIG.
Reference numeral 006 corresponds to 1017 in FIG. 11, and contact portion 1005 in FIG. 10 corresponds to 1019 in FIG. In FIG. 11, the passivation film is omitted.

FIG. 12 is a sectional view of the gate portion of the transistor in the memory cell portion. In FIG. 12, 1021 is
In the channel region, for example, the impurity concentration is 5 × 10 ¹⁴
It is made of a semiconductor of about 5 × 10 ¹⁶ cm ⁻³ . Reference numeral 1022 denotes a gate insulating film, and the oxide film thickness thereof needs to be changed depending on the gate length, but is about 60 Å to 250 Å.

This is not only for the Si oxide film but also for the SiO
It may be N or a laminated film of SiO ₂ and SiON. 10
Reference numeral 23 is a gate electrode. For example, a material having a low resistance such as a polycide structure in which the underlying layer is p ⁺ type polysilicon and the upper layer is W _x Si _1-x and the transistor threshold value is desired is selected. Reference numeral 1024 denotes a cross section of the drain power supply wiring, and 1003 and 1025 in FIG.
Is a cross section of the bit line wiring and corresponds to 1002 in FIG. As can be seen from FIG. 12, the channel region 1021
Are defined in the gate insulating film 1022 and the p layer 1016. Therefore, the channel width of this transistor is the sum of d ₁ and d ₃ , that is, 2d ₁ + d ₃ . Due to the field oxidation step, the gate insulating film thickness under the channel region 1021 changes as shown at 1026 in FIG. 12, and it is relatively difficult to control the value. However, in this transistor, since the channel region in which the transistor actually operates is defined by the underlying p region, it is not affected by the film thickness fluctuation, and the variation among the transistors is extremely small.

FIG. 13 is a sectional view of the source region of the transistor in the memory cell section. In FIG. 13, 1030
Is an n ⁺ -Si region which is a source layer, 1031 ′ is an insulating film provided on the source, and the insulating film is destroyed,
Non-destructive defines conduction and non-conduction state of the memory.
The bit line wiring 1032 is connected to the insulating layer via a contact region 1033. As the insulating layer, for example, SiO ₂ , SiON, a laminated structure of SiO ₂ and SiN, or the like can be used. Alternatively, aluminum oxide, tantalum oxide, or the like can be used.

Next, FIG. 14 which is a section taken along the line YY 'of FIG. 10 will be described.

As shown at 1035 and 1035 'in FIG. 14, each transistor is separated by a vertical surface, and an interlayer insulating film is embedded between each transistor, so that the separation width can be narrowed. It can be said that this is an excellent structure for high integration. The gate electrode structure in this cross section is a normal MOSF.
Although it has a structure similar to that of ET, as shown in FIG. 12 described above, the gate electrode is arranged so as to face the side wall when viewed in a cross section orthogonal to this. Although the gate electrode is also provided on the upper part, d ₁ , shown in FIG.
If the function of d ₃ is expressed as d ₃ <d ₁ (1), the electric field in the channel region is relaxed as compared with a normal MOSFET because the potential is raised from both sides even if the gate voltage is increased. .. Further, since the way of changing the potential changes in the entire channel region, a large current can be passed through the transistor ON by the effects of both of them, and good characteristics with high driving capability were obtained.

FIG. 15 is a circuit diagram showing a 3 × 3 cell semiconductor memory according to the first embodiment.

One cell is an address transistor 10.
40 and a memory element 1041. Of course 1
041 does not become a capacitor before destruction of the insulating film and does not become a capacitor after destruction.

1001, 1001 ', 1001'', 1
001 '''is a word line connected to each gate of the FET.

Reference numerals 1002, 1002 'and 1002''are bit lines connected to one of the memory elements.

Reference numerals 1003, 1003 'and 1003 "are power lines.

As a peripheral circuit of the memory, a bit line voltage setting circuit 1 for setting the bit line voltage to a reference voltage.
042, a word line voltage setting circuit 1043, and a selection signal generation circuit 104 for generating a signal for sequentially selecting bit lines.
4, bit line selection switches 1045, 1045 ', 10
45 ″, a switch 1046 for resetting the bit line read line 1048, and an amplifier 1047.

The operation of the above-mentioned semiconductor memory will be described below.

First, the write operation will be described. This operation includes the following four main operations.

(1) Write Operation Part 1: (Bit Line Precharge) The bit line is set to the reference voltage V _DD by the voltage setting circuit 1042. As a result, there is no potential difference between the power supply line and the bit line, no matter what voltage is applied to the word line, no potential is generated or no current flows between the source and drain of the FET, and the insulating film indicated by 1041 is formed. Not destroyed. The precharge voltage of this bit line may or may not be equal to the power supply voltage, and at that time, the insulating film region is destroyed so as not to be in a conductive state. The value of V _DD can be about 1 to 5 V, for example.

(2) Write Operation Part 2: (Word Line Discharge) The voltage of all word lines is fixed to the first ground potential V _GND1 . For example, it may be OV. This is performed in order to prevent a signal from being mixed into a word line adjacent to a word line which performs a write operation due to crosstalk.

(3) Write operation part 3: (selection of write word line) If the write bit at this time is the cell in the second row and second column with the upper left cell in FIG. 3 as the origin, the word with the write bit The line becomes 1001 'in FIG. Therefore, the potential of this word line is set to V _G. However, at this time, V _G is V _GND1 <V _G <V _GB (2) V _GB is a gate insulating film breakdown voltage.

(4) Write Operation Part 4: (Bit Line Selection) The bit line potential corresponding to the write cell existing on the selected line is set to the ground potential. Then, since all the FETs in the selected line are in the ON state, a high voltage is applied to the insulating film by setting the bit line potential to the ground potential, the insulating film is destroyed, and the conductive state is established. In this writing operation, a current flows between the bit line and the word line upon completion of writing, so it is desirable to sequentially select the bit lines, but it is also possible to write a plurality of bit lines at the same time.

Next, the read operation will be described. This operation includes the following four main operations.

(1) Read Operation Part 1 (Bit Line Precharge) The same operation as at the time of writing is performed. This is because the read operation does not write to the unwritten bits. The voltage at that time may be at the same level as the power supply voltage V _DD .

(2) Read Operation Part 2 (Word Line Discharge) The voltage of all word lines is fixed to the second ground potential V _GND2 . However, the second ground potential V _GND2 and the first ground potential V _GND1 have a relationship of V _GND1 <V _GND2 (Equation (3)).

(3) Read Operation Part 3 (Selection of Line to Read) The potential of the word line of the line to be read is fixed to V _G within the range defined by the equation (2). As a result, the FET on the above line is turned on.

(4) Read Operation Part 4 (Bit Line Read Line Reset) The bit line read line 1048 is reset by the switch 1046. The reset potential is determined by the power source connected to the switch 1046, and the potential is V _GND2 . Then switch 1046 to O
FF is performed, and the bit line read line is put in a floating state.

(5) Read Operation No. 5 (Selection of Bit Line) The bit line sequential selection signal generation circuit 1044 sets the gate of the selected bit selection switch to the high level and turns the switch to O.
The N state is set and the bit line read line is connected. If the selected cell has not been written, the capacitance of the bit line is C
_{Letting BIT} and the capacitance of the read line be C _OUT , the voltage of the read line is

[0071]

[Outer 1] Converge to.

On the other hand, when the selected cell is written and the insulating film is in the conductive state, this read line is in a state of being connected to the power supply V _DD through the transistor. Therefore, the voltage on the read line converges on V _DD . This difference makes it clear whether or not the written cell (bit) is not written. This voltage is
It is detected by 047. Reading is performed by the above operation. In the writing state, the reading speed is determined by the time when the potential of the reading line converges on V _DD . The larger the capacity of the memory, the larger the capacity of the bit line and the bit line read line. Therefore, how to drive this large capacity is a key, and the above-mentioned transistor structure which is fine and has high driving capability becomes extremely effective.

In this embodiment, two types of ground potential are provided,
The operation is performed because the insulating film is not destroyed during the read operation. That is, the potential difference applied to both ends of the insulating film during the read operation is set smaller than that during the write operation.

(Description of Manufacturing Method) Next, a manufacturing method according to the first embodiment of the present invention will be described with reference to FIGS. 16 to 19 are sectional views corresponding to FIG.
Corresponds to FIG. First, boron ions are implanted into the surface of the prepared p-type silicon substrate 1012, and about 900
Activation of impurities in the ion-implanted layer is performed at ℃. After forming the p ⁺ high-concentration layer 1013, the present wafer is washed and placed in an epitaxial growth apparatus to remove the natural oxide film formed on the surface by reducing silane, and the p layer is 2 μm, p ^- layer 1021 is continuously grown to be 0.5 [mu] m. The low temperature epitaxy suppresses the rise of impurities, a sharp junction is obtained for p ⁺ −p and p−p ⁻ , the concentration of the p ⁺ layer is 10 ¹⁹ cm ⁻³ , and the concentration of the p layer is 1.
The concentration of the 0 ¹⁷ cm ⁻³ , p ⁻ layer is about 10 ¹⁶ cm ⁻³ . This wafer is thermally oxidized to a silicon oxide film 106 of about 250 A.
0 is formed, and on top of that, vapor phase chemical vapor deposition (CV
In step D), a 250 Å silicon nitride film 1061 was deposited (FIG. 16).

Next, using this resist as a mask, leaving the transistor formation region in this wafer, the silicon nitride film 1061, the silicon oxide film 1060, and the Si epilayers of the p ⁻ layer 1021 and the p layer 1016 are reacted. It is vertically removed by anisotropic etching. The end of the groove by etching may be in the p layer or the p ⁺ layer, and its control is not strictly required in terms of the device pressure. This is also one of the advantages of this structure. Next, the resist used for patterning is peeled off, and after cleaning, a silicon oxide film 1062 of about 250 Å is formed again on the surface where Si is exposed. Thereafter, a silicon nitride film is deposited on the entire surface by CVD, and only the silicon nitride film on the bottom surface 1063 is removed by anisotropic silicon nitride film etching, as shown in FIG. 4B. In this case, the silicon nitride film 1064 on the columnar Si is left because it is formed of two layers (FIG. 17).

Next, pyrogeneric oxidation is performed at about 900 ° C. to selectively oxidize only the surface on which the silicon nitride film is not formed. By this process, a field oxide film 1014 is formed as shown in FIG. 4C. By this field oxidation step, the silicon pillar I portion is deformed as shown by 1065, but the deformed region is composed of the p layer 1016 or the p ⁺ layer 1013 and is not affected by this deformation. (FIG. 18).

Next, the silicon nitride film 1 used for the selective oxidation.
066 and the underlying pad oxide film 1067 are removed,
After cleaning the exposed Si surface, a gate oxide film 1022 is formed by thermal oxidation. Further, polysiW (tungsten) is continuously deposited, and thereafter, a gate electrode made of p ⁺ -type polysilicon, W _1-X Si _X and W is formed from the W surface by ion implantation of boron and unfurling. In this type of transistor operation, since the corresponding gate-to-gate distance is 0.1 μm, the potential of the channel part is entirely controlled by the gate potential, and the ON-
It is turned off. Therefore, conventional MOSF
Although the threshold value is lower than that of ET, the threshold value is increased by the p ⁺ layer 1068. The upper part of the gate electrode is W
It is made of metal 1069 and realizes low resistance of the word line.

After patterning this gate electrode, the n ⁺ layer is diffused using this gate as a mask to form a source layer 1030,
A drain layer 1017 is formed.

Next, as shown in FIG. 19, the interlayer insulating film 10 is formed.
15 is flattened and formed. This planarization can be accomplished, for example, by combining tetraethyl orthosilicate (TEOS) deposition and etch back. After this,
The thin film SiO ₂ is densified in a N ₂ atmosphere at 550 ° C. Further, as a method of forming the thin film SiO ₂ , a method of forming an oxide film in platinum-hydrogenated water after cleaning and increasing the density in a N ₂ atmosphere of 500 to 600 ° C. is also effective.

Next, a contact hole 1070 is formed only in the source region 1030. The Si surface is exposed only in this contact hole, and a silicon oxide film 1033 of about 50 Å is formed by CVD only in the region of this contact hole. After this,
The silicon oxide film is densified in a N ₂ atmosphere at 550 ° C. Further, as a method of forming the thin film SiO ₂ , a method of forming an oxide film in platinum-hydrogenated water after cleaning and increasing the density in a N ₂ atmosphere of 500 to 600 ° C. is also effective. After that, power supply and bit line wirings are formed, patterned, and a passivation film is formed to form the present cell structure. In this description, the n-channel MOSFET has been described as an example, but the p-channel MOSFET can be manufactured in the same process if the conductivity types are reversed, and thus the description thereof is omitted. Therefore, the peripheral circuit is an n-type channel MOSFE.
It can be manufactured as a CMOS structure composed of T and p-type channel MOSFETs.

As described above, the first embodiment of the present invention
Is not a method of forming a conductive state or a non-conductive state depending on the breakdown or non-destruction state of the insulating film and reading a slight accumulated charge unlike the conventional DRAM or EPROM.
Even with miniaturization, high S / N can be read. In addition, since a transistor of a new structure is adopted for this reading and it has a fine and high driving ability characteristic, high integration and high speed reading can be realized.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. 21 to 24. The same parts as those in FIGS. 11 to 14 are designated by the same reference numerals and the description thereof will be omitted.

[0083] The configuration is different from the first embodiment, p as a channel region ^- this p the same conductivity type on the layer 1017 ^-
That is, the p-layer 1080 having a higher impurity concentration than that of the layer is formed.

This structure has p well layer 1016, p ⁻ layer 1
017, p layer 1080 may be formed by epitaxial growth while changing the impurity concentration, and in manufacturing, the same steps as those of the above-described first embodiment can be performed.

When the drain layer 1017 and the power source are contacted, the Si layer on the drain upper surface is formed as shown in FIG.
It may be performed after slightly etching as indicated by 081.

Next, the operation of the transistor used in this embodiment will be described.

The impurity concentration of the p layers 1016 and 1080 is such that an inversion layer is not formed on the interface side with the upper gate insulating film 1022 even when the gate voltage during operation reaches the maximum value. There is. Therefore, the p ⁻ layer 10
21. The channel is formed only on the side wall of the gate insulating film 21 and the gate insulating film 1022. Therefore, this structure is equivalent to a structure consisting of two gates facing each other, and the operation is stable.

Further, although the insulating film thickness of the edge portion of Si is usually thinner than that of the flat surface portion and the withstand voltage is lowered, according to the present embodiment, as shown by the edge portion 1082, the concentration of the inner p layer is high, Since it has a sufficient withstand voltage, it can be used even if the film thickness is thinner than that of the first embodiment. Thereby, a high gm characteristic is obtained.

Due to this excellent transistor characteristic, high-speed reading as a memory can be realized.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG. Similar to the second embodiment, the third embodiment also relates to a method for improving the memory cell transistor shown in the first embodiment. Cross-sectional views of portions other than the cross-section shown in FIG. 25, which correspond to the first embodiment, are as shown in FIGS. Is the same. The same parts are denoted by the same reference numerals and the description thereof will be omitted. The feature of the third embodiment is that the n ⁻ layer 1085 is provided near the source and drain gate electrodes. The structure of the present embodiment can be easily formed in a self-aligned manner by using the insulating layer provided on the side wall of the gate electrode, as in the case of manufacturing a structure such as LDD, GOLD and the like. According to this example, it is possible to relax the electric field at the source and drain ends of the gate electrode and prevent unwanted carriers from entering the channel region. As a result, not only fast read characteristics can be realized in the memory, but also hot carriers and the like can be prevented and higher reliability can be obtained.

In this embodiment, the n ^- layer is provided symmetrically to the source and the drain, but the high electric field is actually applied to the drain end, and in the sense that the source side enhances the driving capability. The n ⁻ layer may be provided only on the drain side because it is not necessary to add a resistance component.

(Embodiment 4) In this embodiment, wirings connected to the source and drain of a transistor are arranged so as to cross each other.

A fourth embodiment of the present invention will be described. Figure 2
6 is a plan view, FIG. 27 is a sectional view taken along line X ₁ X ₁ ′ of FIG.
Shows the YY 'cross section of FIG. In the case of the above-described first embodiment, the word line runs in the horizontal direction and the bit line and the power supply line are provided in the vertical direction. On the other hand, in this embodiment, the layout is such that word lines 1001, 1001 'and power supply lines 1096, 1096' run in the horizontal direction, while only bit lines 1002, 1002 'run in the vertical direction. Since this transistor has a vertically long shape,
By running the power line laterally in this way,
The area per 2 cells is smaller than that of the first embodiment, and there is an advantage that higher integration can be achieved.

One configuration that enables the layout of FIG. 26 will be described with reference to FIGS. In FIG. 27,
1100 is n ⁺ type polysilicon-W as a power supply line
_{The 1-X} Si _X -W wiring 1101 is a direct contact portion in which the n ⁺ type polysilicon is in contact with the drain layer 1017. As shown in FIG. 28, lengthen this horizontally by 1
It can be seen that two polysilicon-polycide W wirings 023 and 1100 are arranged. Other than the ones shown in FIGS. 27 and 28, a system in which a two-layer metal wiring is used and the first-layer metal is a bit line and the second-layer metal is a power line may be used.

(Embodiment 5) Next, regarding Embodiment 5 of the present invention, the layout diagram of the memory cell is shown in FIG. 29, the X ₁ X ₁ ′ cross section of FIG. 29 is shown, and the X ₃ X ₃ ′ of FIG. 29 is shown. This will be described with reference to FIG. 31, which is a cross section. 29, 1105 and 110
As shown in FIG. 6, this embodiment is different from the above-described first embodiment in that the contact size of the source and drain layers of the transistor is wide. By widening the long contact in the direction orthogonal to the current flow direction (YY 'direction) of the transistor, it is possible to make contact also on the sidewalls of the source layer and the drain layer.
Contact resistance decreases. Especially as miniaturization progresses,
At the same time as the drivability of the transistor, parasitic resistance and capacitance have a significant influence on the circuit characteristics. In this respect, the above structure is excellent in reducing parasitic resistance. Therefore, in order to clarify the structure of the contact, a detailed description will be given with reference to FIGS.

In FIG. 30, reference numeral 1105 is a drain layer contact hole, 1107 is a first interlayer insulating layer for stopping the contact etching, and 1109 is a second interlayer insulating layer. In this case, a material that can achieve the selection ratio is used. For example, the first interlayer insulating layer may be a silicon nitride film, and the second interlayer insulating layer may be a silicon oxide film. As a result, it becomes possible to make contact with the wiring metal over a wide area as indicated by 1108 in FIG.

On the other hand, as for the contact of the source portion, as shown in FIG. 31, the thin film insulating layer 1111 for memory is attached to the exposed n ⁺ layer surface 1110, and the metal 1 for wiring is provided through the p ⁺ layer.
I am in contact with 032. As described above, by using the structure of this embodiment, the resistance of the contact portion is further reduced, and high-speed reading can be realized.

(Sixth Embodiment) FIG. 32 shows a sixth embodiment.
This will be described using 33. Example 6 is manufactured by a method different from the manufacturing method described in Example 1 for the structure of Example 1 described above. 1A to 1C showing a manufacturing method of Example 1.
Descriptions of the same parts as those in FIGS. 6 to 20 are omitted, and the same parts are denoted by the same reference numerals.

As shown in FIG. 32, the greatest feature is that a field oxide film is formed by film formation and etching instead of selective oxidation. The processes up to the formation of the pad oxide film surrounding the columnar semiconductor region and the process of forming the silicon nitride film are the same as in the first embodiment. Then, the silicon oxide film on the surface obtained by anisotropically etching the silicon nitride film is peeled off, and a thermal oxide film 1092 is formed again. Then, an interlayer insulating film is formed by using TEOS, and SiO _{2 is} etched back.
The layer 1091 is formed. It suffices that a sufficient etching selection ratio between the silicon nitride film and the silicon oxide film is obtained at the time of this etching back.

By this etching back, the surface of the field oxide film is set to be higher than the interface between p layer 1016 and p ⁺ buried layer 1013 and lower than the interface between p layer 1016 and p ⁻ layer 1021. Next, the silicon nitride film is removed by etching, the pad oxide film is removed, and after cleaning, gate oxidation is performed as shown in FIG.
A field oxide film shape as shown in 091 'is obtained. After that, the gate electrode layers 1068, 10 are formed in the same manner as in Example 1.
69 may be formed. When the manufacturing method described above is used, a high temperature step is not included and excessive diffusion of impurities is reduced,
The size of the channel region is stable. Further, there is an advantage that there is no distortion generated by field oxidation or the like. As a semiconductor memory, the variation of each memory cell is reduced, so that there is an advantage that the present device can be realized with a high yield.

As a result of manufacturing a semiconductor memory and performing a write operation and a read operation based on each of the above-described embodiments, it was confirmed that each of the embodiments performs an operation that is better than expected.

Next, a PN junction destruction type memory will be described as a memory element.

(Embodiment 7) FIGS. 34 and 35 are sectional views of a memory cell according to Embodiment 7 of the present invention and correspond to FIG. 13 described above. The difference from FIG. 13 is that the insulating layer 1031 ′ (FIG. 13) forming the memory element is the p ⁺ -type semiconductor layer 103.
1 (FIG. 34) is replaced with a PN junction destruction type memory. The other configuration of the semiconductor memory is the same as that of the first embodiment.

Here, 1030 is n ⁺ − which is the source layer.
Si region, 1031 is p ⁺ provided on its source
In the region, the conduction / non-conduction state of the memory is defined by this pn junction. On the p ⁺ layer, contact region 1033
It is connected to the bit line wiring 1032 via.

Next, the operation method and storage method of the memory device of the present invention will be described. FIG. 36 shows the layout of the memory cell of this example as an equivalent circuit.
010 to 1001 '''' are word lines, 1002 to 100
Reference numeral 2 ″ denotes a bit line, and 1003 to 1003 ″ denote power supply lines. Each cell has a fine transistor 1040 with high current driving capability and a pn junction 1041 provided in the source layer of the transistor to form a memory cell.
Further, as memory peripheral circuits, a bit line voltage setting circuit 1042, a word line voltage setting circuit 1043, a bit line sequential selection signal generation circuit 1044, bit line selection switches 1045 to 1045 ″, a bit line read line 104.
8 is composed of a switch 1046 and an amplifier 1047.

Next, the write operation will be described.

(1) Write Operation Part 1: (Precharge Bit Line) The bit line is set to the voltage _VDD by the voltage setting circuit 1042.
Set to. As a result, there is no potential difference between the power supply line and the bit line, no matter what voltage is applied to the word line, no potential is generated or no current flows between the source and drain, and the pn junction 1041 is destroyed. Not done. The precharge voltage of this bit line may be other than equal to the power supply voltage V _DD as long as it does not bring the pn junction region into a conductive state. The value of V _DD can be about 1 to 5 V, for example.

(2) Write Operation Part 2: (Word Line Discharge) The voltage of all word lines is fixed to the first ground potential V _GND1 . For example, it may be 0V. This is performed in order to prevent a signal from being mixed into a word line adjacent to a word line which performs a write operation due to crosstalk.

(3) Write Operation 3 (Selection of Write Word Line) It is assumed that the write bit at this time is the cell in the second row and second column with the upper left cell as the origin. The word line having the write bit is 1001 'in FIG. Therefore, the potential of this word line is set to V _G. However, V _G is V _GND1 <V _G <V _GB formula (2). V _GB is a gate insulating film breakdown voltage.

(4) Write Operation Part 4 (Bit Line Selection) The bit line potential corresponding to the write cell existing on the selected line is set to the ground potential. Then, all the transistors of the selected line are in the ON state, so that by setting the bit line potential to the ground potential, a high voltage is applied to the pn junction, and the pn junction is destroyed and becomes conductive. In this write operation, since a current flows between the bit line and the word line upon completion of the write, it is desirable to sequentially select the bit lines, but it is also possible to write a plurality of bit lines at the same time.

Next, the read operation will be described.

(1) Read Operation Part 1 (Bit Line Precharge) The same operation as in writing is performed. This is because the unwritten bits are not written by the read operation. The voltage at that time may be at the same level as the power supply voltage V _DD .

(2) Read Operation Part 2 (Word Line Discharge) The voltage of all word lines is fixed to the second ground potential V _GND2 . However, the second ground potential V _GND2 and the first ground potential V _GND1 have a relationship of V _GND1 <V _GND2 (3).

(3) Read Operation Part 3 (Selection of Line to Read) The potential of the word line of the line to be read is fixed to V _G within the range defined by the equation (2). As a result, the transistor on the above line is turned on.

(4) Read Operation Part 4 (Bit Line Read Line Reset) The bit line read line 1048 is reset by the switch 1046. The reset potential is the above switch 1
It is determined by the power source connected to 046, and its potential is V _GND2 . After that, switch 1046 to OF
Then, the bit line read line is set to the floating state.

(5) Read Operation No. 5 (Selection of Bit Line) The bit line sequential selection signal generation circuit 1044 sets the gate of the selected bit selection switch to the high level, turns the switch ON, and connects it to the bit line read line. .. now,
When the selected cell is not written, assuming that the bit line capacitance is C _BIT and the read line capacitance is C _OUT , the read line voltage is

[0117]

[Outside 2] Converge to.

On the other hand, the selected cell is written, and pn
When the junction is conducting, this read line is in connection with the power supply V _DD through the transistor. Therefore, the voltage on the read line converges on V _DD . This difference makes it clear whether the cell (bit) is written or not. This voltage is the amplifier 104
7 to detect. Reading is performed by the above operation. In the writing state, the reading speed is determined by the time when the potential of the reading line converges on V _DD . The larger the capacity of the memory, the larger the capacity of the bit line and the bit line read line. Therefore, the key is how to drive this large capacity, and the transistor structure described in this embodiment, which is fine and has a high driving capability, is extremely effective.

In this embodiment, two types of ground potential are provided,
The operation is performed because the pn junction is not destroyed during the read operation. That is, the potential difference applied to both ends of the pn junction during the read operation is set smaller than that during the write operation.

Next, the manufacturing method of the seventh embodiment will be described. Basically, it is the same as the step shown in FIG. 16 to FIG. 20 of Example 1, except that a p-type semiconductor layer is formed instead of the insulating layer, and the step of FIG. Like

That is, according to the process shown in FIG.
After the formation, only the source region 1030 has the contact hole 107.
Open 0. The Si surface is exposed only in this contact hole, and p ⁺ layers 400Å to 800Å shown at 1033 in FIG. 4 are formed by LPCVD only in the region of this contact hole.
After that, power supply and bit line wirings are formed into a film, patterned, and a passivation film is formed to form the present cell structure.

As described above, according to the embodiment of the present invention, conduction and non-conduction states are formed by the destruction and non-destruction state of the pn junction, and unlike the conventional DRAM and E ² PROM, a slight accumulated charge is accumulated. Therefore, even if the miniaturization progresses, a high S / N can be read.
In addition, a transistor with a new structure is adopted for this reading,
Since it is fine and has high driving ability characteristics, high integration and high-speed reading can be realized.

(Embodiment 8) Next, an embodiment 8 of the invention will be described with reference to FIGS. 38 (a) and 38 (b). FIG. 23,
The same parts as 24 are designated by the same reference numerals, and the description thereof is the same as that of the second embodiment, so that the description thereof is omitted here. In this example, the memory element is a p ⁺ pn ⁺ junction and the junction capacitance is small.

(Ninth Embodiment) The present embodiment shown in FIG. 39 is the same as FIG. 25 of the above-mentioned third embodiment. The only difference is that the p ⁺ -type semiconductor layer 1031 is formed instead of the insulating layer to form a pn junction.

Example 10 Example 10 shown in FIG. 40 is the same as FIG. 28 of Example 4. The only difference is that the p ⁺ semiconductor layer 1031 is formed instead of the insulating layer.

(Embodiment 11) Next, Embodiment 11 of the present invention will be described with reference to FIG. This figure is a sectional view equivalent to FIG. 34, and only this part is different, and therefore the difference will be described only by this figure. Also, like the previous time, the same parts are denoted by the same reference numerals, and description thereof will be omitted. This Example 11 is Example 1.
The difference from Example 1 is that the p ⁺ layer was selectively formed on the Si layer in Example 1, while the n ⁺ source layer 1030 was used in Example 3
This is that p ⁺ layer 1088 is formed in the n ⁺ layer by ion-implanting p type ions such as boron and annealing using the contact hole as an upper mask. When the structure of this embodiment is used, the leak current of the pn junction is reduced, the conduction and non-conduction modes become more prominent, and high S / N is obtained. Further, after the ion implantation, a high-resistance layer provided by forming a p ⁺ layer of amorphous to the n ⁺ layer in, it is possible to achieve non-conduction of.

(Embodiment 12) This embodiment is the same as the embodiment 5 shown in FIG. 31 except that the memory element of the source section is exposed.
^{In this} structure, the protruding surface 1110 of the ⁺ layer 1030 is covered. This memory element can be formed as a p ⁺ type semiconductor layer by selective deposition by the LPCVD method. In this example, the source contact resistance is further reduced, and high-speed reading is possible.

According to the embodiment described above, a conductive or non-conductive state can be formed by breaking or non-destructing a pn junction as a semiconductor junction, and a signal written with a high S / N can be read out. In memory, low error rate,
A highly reliable memory can be realized. Furthermore, since a new type of transistor with high driving capability is used for the memory cell, there is an effect that a high speed and highly integrated memory can be realized.

That is, a semiconductor layer is used as a memory element and PN is used.
Since the information is recorded in either the destroyed or non-destructed state of the junction, the variation in the destroyed state is smaller for each cell than in the case of the insulating film, so that the reliability is high.

In any case, in the present invention, a pn junction, an insulating film / semiconductor junction, a metal / insulating film / semiconductor junction, a PIN junction, a semiconductor / insulating film / semiconductor junction PI is used as a memory element.
Any electrically destructible junction such as a junction, an IN junction, a Schottky junction, or a hetero junction is used.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to these embodiments and includes various modifications by combining or exchanging the elemental technologies.

According to the embodiment described above, the conductive state and the non-conductive state are formed by the destruction and non-destruction state of the memory element,
It is possible to read signals written with high S / N,
A low error rate and highly reliable memory can be realized. Furthermore, by using a new type of transistor with a high driving capacity for a memory cell, a high speed and highly integrated memory can be realized.

[Explanation of Another Preferred Embodiment] In a more preferred embodiment of the present invention, a source region, a drain region, a channel region provided between them, and a gate insulating film for the channel region are provided. A gate electrode provided via the gate electrode, and a semiconductor region having the same conductivity type as the channel region and having an impurity concentration higher than that of the channel region, the gate electrode being provided in contact with the channel region. A plurality of semiconductor structures each having at least two facing portions facing each other, the facing portions having a surface intersecting a junction surface between the channel region and the semiconductor region; A first wiring having a common gate electrode of a plurality of semiconductor structures and a source region as a memory element in a source region of the plurality of semiconductor structures are different from each other. In a semiconductor device including a second wiring that connects a plurality of semiconductor structures by forming a PN junction through an electro-type material, a power supply line is provided between the second wirings. Is.

Alternatively, a source region, a drain region,
In a semiconductor device having a channel region provided between them and a gate electrode provided to the channel region via a gate insulating film, the semiconductor device provided in contact with the channel region has the same conductivity as the channel region. A semiconductor region having a higher impurity concentration than the channel region,
The gate electrode has at least two facing portions facing each other, and a plurality of semiconductor structures are provided so that the facing portions have a surface intersecting a bonding surface between the channel region and the semiconductor region. A first wiring that is unique and has a common gate electrode of the plurality of semiconductor structures, and connects the plurality of semiconductor structures through a source region of the plurality of semiconductor structures via an insulating film as a memory element. In a semiconductor device having two wirings, a power supply line is provided between the second wirings.

A dynamic RAM (DRA) is provided as a user-programmable and randomly-accessible memory.
There is M). This type of memory cell is shown in FIG.
Reference numeral 501 is a bit line, 502 is a word line, 503 is a MOS transistor arranged in a memory cell. Each MOS transistor 504 is connected to a bit line 501, each gate is connected to a word line 502, and each drain is connected to a capacitor 507. There is. 508 is a field plate of a capacitor held at the ground potential.

A memory cell is selected by selecting and driving the word line, and cell information is output to the bit line. This minute signal is received by the sense amplifier, amplified, sent to the output buffer amplifier, and output.

However, if a small signal charge is large b
Since it is read to the it line capacitance and the slight change thereof is amplified and read by the sense amplifier, there is a problem that the noise margin is narrow and a small noise causes malfunction. In order to improve this problem, a structure having a dummy bit line as shown in FIG. 43 has been proposed. Memory cell 503 is bit
The dummy memory cell 513 is connected to the dummy bit line 512.

By differentially amplifying the information of the memory cell 503 and the signal level of the dummy cell 513 by the sense amplifier 511 by the selection of the word line 502, the noises generated at the intersections of the word line 502 and the bit line cancel each other out. There is an advantage called.

Further, in order to achieve high integration and high speed in the memory, fine transistors having high current driving capability are required.

Thus, the noise is reduced by providing the dummy cell, but the method of detecting the minute voltage read from the essentially small capacity to the large capacity remains unchanged. Therefore, further miniaturization will be promoted in the future, and bit
As the number increases and the cell size decreases, the bit line capacitance further increases and the memory cell capacitance further decreases. In order to increase the capacity of the memory cell, it is sufficient to thin the insulating film thickness of the capacitor, but at present, it is roughly 100Å.
It has been thinned to the following, and if the film is made thinner than this,
The problems of tunnel current and dielectric strength cannot be ignored, and it becomes difficult to secure reliability. Further, there is a means for arranging a shield line for preventing crosstalk in order to reduce noise, but this causes an increase in bit line capacitance and a signal level is lowered, so that the essence of S / N is essential. Does not result in an improvement.

As described above, the conventional dynamic R
In the AM type memory, it is not possible to secure a sufficient noise margin when miniaturization and increase in number of bits are promoted in the future.

Further, as a result of examining the structure of the transistor in each of the conventional examples, it was found that the leakage current of the transistor was large, the variation of each transistor was large, and the OFF characteristics of the transistor were poor, resulting in unstable operation. did.

Therefore, the common points of the embodiments described below are the source region, the drain region, the channel region provided between them, and the gate electrode provided to the channel region via the gate insulating film. And a semiconductor region which is provided in contact with the channel region and has the same conductivity type as that of the channel region and a higher impurity concentration than the channel region, and the gate electrode has two facing portions facing each other. A gate electrode of the transistor is provided by using a transistor having at least the facing portion and having a surface intersecting a junction surface between the channel region and the semiconductor region. In a memory cell in which a memory element is formed between the source layer of the transistor and the bit line as a word line, adjacent b By disposing the power wiring between t line is to provide a semiconductor memory device adapted for miniaturization.

According to the embodiments described below, it is possible to realize a semiconductor memory device having a large noise margin in which noise is greatly reduced by the power supply wiring arranged between the bit lines.

Basically, the dummy bit as described with reference to FIG. 43 can be removed, and the driving method can be simplified.

(Embodiment 13) Embodiment 13 will be described. Since the configuration of the memory cell of this example is the same as that of FIGS. 11 to 14, detailed description thereof will be omitted here. Differences from the configuration of the embodiment are characteristically shown in FIG.

The present embodiment is an example in which the present invention is applied to a memory cell which writes into a bit by breaking or non-breaking an insulating film.

FIG. 33 is a circuit diagram showing the layout of the memory cell of this embodiment. Figure 1
The same numbers are given to the same parts as 5, and the description is omitted. Reference numeral 1081 is an insulating thin film as a memory element provided in each memory cell.

Next, the operation method and storage system of the memory device of the present invention will be described. 1001-100
Reference numeral 1 '''is a wart line, 1002 to 1002''is a bit line, and 1003 to 1003''is a power supply line. Each cell is a transistor 1040 that is fine and has high current drive capability.
And a capacitor 1081 including an insulating layer as a memory element is provided in the source layer of the transistor to form a memory cell. Further, as a peripheral circuit of the memory, a switch 1042 for precharging the bit line, a word line voltage setting circuit 1043, a bit line sequential selection signal generating circuit 1
044, bit line selection switches 1045 to 104
5 ″, a switch 1046 for resetting the bit line read line 1048, and an amplifier 1047.

Next, the write operation will be described.

(1) Write Operation Part 1: (Precharge Bit Line) Turn on the bit line 1042 switch MOS to set the voltage V
Precharge _DD . As a result, there is no potential difference between the power supply line and the bit line, no matter what voltage is applied to the wort line, no potential is generated or no current flows between the source and drain, and the memory element 1081 shown in 1041 is destroyed. Not done. The precharge voltage of the bit line may be other than the power supply voltage V _PD , as long as the pn junction region is destroyed and does not become conductive. V _DD
The value of can be about 1 to 5 V, for example.

(2) Write Operation Part 2: (Word Line Discharge) The voltage of all word lines is fixed to V _GND1 at the first ground potential. For example, it may be 0V. This is performed in order to prevent a signal from being mixed into the word line adjacent to the word line in which the write operation is performed due to crosstalk.

(3) Write Operation Part 3 (Selection of Word Line to Write) This time, the write bit is 2 with the upper left cell as the origin.
Assume that the cell is in the second row and the second row. The word line having the write bit is 1001 'in FIG. Therefore, the potential of this word line is set to V _G. However, V _G is V _GND1 <V _G <V _GB formula (2). V _GB is a gate insulating film breakdown voltage.

(4) Write Operation Part 4 (Bit Line Selection) The bit line potential corresponding to the write cell existing on the selected line is set to the ground potential 1. Then, since all the transistors in the selected line are in the ON state, by setting the bit line potential to the ground potential, a high voltage is applied to the pn junction, the pn junction is destroyed, and the conductive state is established. At this time, since the power supply wiring is arranged between the bit lines, the adjacent bits are cross-talked.
Since there is no risk of the line cells being destroyed, the peripheral circuit necessary for fixing the potential of the adjacent bit line is not necessary. In this write operation, a current flows between the bit line and the word line upon completion of writing,
It is desirable to sequentially select the bit lines, but it is also possible to write a plurality of bit lines at the same time.

Next, the read operation will be described.

(1) Read Operation Part 1 (Bit Line Precharge) The same operation as in writing is performed. This is because the read operation does not write to the unwritten bits. The voltage at that time may be at the same level as the power supply voltage V _DD . (2) Read Operation Part 2 (Word Line Discharge) The voltage of all word lines is fixed to the second ground potential V _GND2 . However, the second ground potential V _GND2 and the first ground potential V _GND1 have a relationship of V _GND1 <V _GND2 (Equation (3)).

(3) Read Operation Part 3 (Selection of Line to Read) The potential of the word line of the line to be read is fixed to V _G within the range defined by the equation (2). As a result, the transistor on the above line is turned on.

(4) Read Operation Part 4 (Reset Bit Line Read Line) The bit line read line 1048 is reset by the switch 1046. The reset potential is the above switch 1
It is determined by the power source connected to 046, and its potential is V _GND2 . After that, switch 1046 to OF
Then, the bit line read line is set to the floating state.

(5) Read Operation No. 5 (Selection of Bit Lines) The bit line sequential selection signal generation circuit 1044 sets the gate of the selected bit selection switch to the high level, turns the switch ON, and connects it to the bit line read line. .. now,
If the selected cell is not written, change the capacitance of the bit line to C
_If the capacitance of _BIT and the read line is C _OUT , the voltage of the read line is

[0160]

[Outside 3] Converge to.

On the other hand, when the selected cell is written and the memory element is in the conductive state, this read line is connected to the power supply V _DD through the transistor. Therefore, the voltage on the read line converges on V _DD . This difference reveals whether the cell (bit) was written or not written. This voltage is detected by the amplifier 1047. Reading is performed by the above operation, but in the writing state, the reading speed is determined by the time when the potential of the reading line converges to V _DD . The larger the capacity of the memory, the larger the capacity of the bit line and the bit line read line. Therefore, the key is how to drive this large capacity,
The transistor structure described in this embodiment, which is fine and has high driving capability, is extremely effective.

In this embodiment, two types of ground potential are provided,
The operation is performed because the memory element is not destroyed during the read operation. That is, the potential difference applied to both ends of the memory element during the read operation is set smaller than that during the write operation.

The method of manufacturing the memory cell of this example is shown in FIG.
Since it is the same as the method described in 4 to 18, detailed description will be omitted here.

The capacitor having an electrically destructible insulating film as a memory element, which is provided in each memory cell, has a PN junction in which a semiconductor film having a conductivity type opposite to that of the main electrode region is used instead of the insulating film. Can be replaced by

In this case, the structure of the memory cell is changed from the insulating film to the semiconductor film, and other basic structures are the same. The circuit configuration of the semiconductor memory when the PN junction is used as a memory element is as shown in FIG. Also, the operating method is basically the same.

Example 14 Next, Example 14 of the present invention.
46, a top view is shown in FIG. 46, an X ₃ X ₃ ′ sectional view of FIG. 46 is shown in FIG. 47, and an YY ′ sectional view is shown in FIG. 48, which will be described with reference to these figures.

In this embodiment, the power supply lines 1003, 100
3'is a wiring layer 1018 of the first layer, which is a bit line 100
2, 1002 'are formed by the second wiring layer 1082. Reference numerals 1083 and 1083 'are passivation films. By separately providing the wiring layers for the power supply line and the bit line in this manner, the area per cell is reduced as compared with the above-mentioned embodiments, and there is an advantage that high integration can be achieved.

In this embodiment, the same effect can be obtained even if the bit line is the first layer and the power supply line is the second layer. Also,
The same effect can be obtained even if the structure of the memory element is replaced with an insulating film and a P-type semiconductor film is used.

Example 15 Next, Example 15 of the present invention.
FIG. 49 shows a plan view of the above. FIG. 50 shows a sectional view taken along the line YY 'of FIG. 49, and description will be given with reference to these drawings.

In this embodiment, the power supply lines 1003 and 10
Reference numeral 03 'denotes the first wiring layer 1018, which has a bit line 1
002 and 1002 'are second wiring layers 1082 formed directly above the memory cells. By adopting such a structure, higher integration can be achieved.

In this embodiment, the same effect can be obtained even if the bit line is the first layer and the power supply line is the second layer. Also,
The same effect can be obtained by using a P-type semiconductor layer instead of the insulating film for the structure of the memory element.

Example 16 Next, Example 16 of the present invention will be described.
FIG. 51 shows a plan view of the above. A sectional view taken along line X ₃ X ₃ ′ of FIG. 40 is shown in FIG.

In this embodiment, the power supply lines 1003, 100
3'is formed by using the wiring layers of the first layer 1032 'and the second layer 1082, and the space between the first and second wiring layers is provided in parallel with the wiring. Connected via contact holes. By forming the power supply line by using the two layers of wiring, it is possible to more reliably prevent crosstalk between bit lines.

In this embodiment, the same effect can be obtained by using a P-type semiconductor film instead of the insulating film for the structure of the memory element.

(Embodiment 17) Next, FIG. 53 is a plan view showing Embodiment 17 of the present invention. A sectional view taken along line X ₃ X ₃ ′ of FIG. 53 is shown in FIG.

In this embodiment, the adjacent power supply line 100
3, 1003 'are connected to each other by a second wiring layer 1082, and the bit lines 1002, 1002' are covered with a power supply line. With such a structure, crosstalk between bit lines can be prevented more reliably.

In the present embodiment, the same effect can be obtained even if the structure of the memory element is replaced by the P-type semiconductor instead of the insulating film.

According to the above-described embodiments, in a semiconductor memory device in which conductive and non-conductive states are formed by the destruction and non-destruction of a memory element, crosstalk between bits can be prevented more reliably, and a low error rate, A highly reliable memory can be realized.

(Embodiment 18) In the embodiment described below, a barrier layer is provided between an insulating film for forming a memory element and a main electrode region provided below the insulating film.

The barrier layer may be made of any material as long as it can prevent the reaction between the electrode provided on the insulating film and the main electrode region. Specifically, TiN, Ti,
A material selected from W and the like is preferably used.

With such a structure, it is possible to prevent a short circuit and a leakage current from occurring between the main electrode region and the channel region due to the reaction between the electrode and the main electrode region after the insulation layer is destroyed (writing operation).

Specifically, the configuration shown in FIGS. 55 and 56 in which the configurations of FIGS. 13 and 14 are improved, the configuration shown in FIG. 57 in which the configuration of FIG. 20 is improved, and the configurations of FIGS. 23 and 24 are improved. 58 and 59, as well as the configuration shown in FIG. 60 which is an improvement of FIG. 25, FIG. 61 which is an improvement of FIG. 28, and FIG. 62 which is an improvement of FIG.

55 to 62, reference numeral 2
Reference numeral 010 is a barrier layer.

(Embodiment 19) This embodiment shown in FIG. 63 is an example in which the technique of the barrier layer is applied to a PN junction breakdown type memory.

2010 is a barrier layer, 2011 is a semiconductor thin film made of a semiconductor of the same conductivity type as the main electrode region 1030,
Reference numeral 2012 is a thin film made of a semiconductor having a conductivity type different from that of the semiconductor thin film 2011.

The thin films 2011 and 2012 are made of phosphorus-doped polycrystalline Si, boron-doped polycrystalline Si, or the like, respectively.

As described above, by forming the memory element separately from the transistor, the influence of junction breakdown can be prevented from affecting the transistor.

[0188]

According to the present invention, it is possible to provide a fine memory cell and a semiconductor memory device capable of operating at high speed with low power consumption. Moreover, the layout of the memory cell is simple and the entire occupied area can be reduced. Further, it is possible to provide a memory cell having high driving ability and good switching characteristics.

[Brief description of drawings]

FIG. 1 is a schematic diagram for explaining a conventional semiconductor memory device.

FIG. 2 is a schematic cross-sectional view for explaining a conventional semiconductor memory device.

FIG. 3 is a schematic cross-sectional view for explaining a conventional transistor.

FIG. 4 is a schematic perspective view for explaining a conventional transistor.

FIG. 5 is a schematic top view for explaining a conventional semiconductor device.

FIG. 6 is a schematic cross-sectional view showing a conventional semiconductor device.

FIG. 7 is a schematic cross-sectional view showing a conventional semiconductor device.

FIG. 8 is a circuit diagram showing a conventional bipolar transistor memory.

FIG. 9 is a schematic sectional view for explaining a conventional bipolar transistor memory.

FIG. 10 is a schematic top view of the semiconductor device according to the first embodiment of the present invention.

11 is a schematic cross section taken along line X ₁ X ₁ ′ in FIG.

12 is a schematic cross section taken along line X ₂ X ₂ ′ in FIG.

13 is a schematic cross section taken along line X ₃ X ₃ ′ in FIG.

14 is a schematic cross section taken along line YY ′ in FIG.

FIG. 15 is a circuit configuration diagram of a semiconductor device according to a first embodiment.

FIG. 16 is a schematic diagram for explaining the manufacturing method of Example 1.

FIG. 17 is a schematic view for explaining the manufacturing method of the first embodiment.

FIG. 18 is a schematic view for explaining the manufacturing method of Example 1.

FIG. 19 is a schematic view for explaining the manufacturing method of Example 1.

FIG. 20 is a schematic diagram for explaining the manufacturing method of Example 1.

FIG. 21 is a schematic sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 22 is a schematic cross-sectional view of a semiconductor device according to a second embodiment.

FIG. 23 is a schematic sectional view of a semiconductor device according to a second embodiment.

FIG. 24 is a schematic sectional view of a semiconductor device according to a second embodiment.

FIG. 25 is a schematic sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 26 is a schematic top view of a semiconductor device according to a fourth embodiment of the present invention.

27 is a schematic cross section taken along line X ₁ X ₁ ′ in FIG.

28 is a schematic cross section taken along line YY ′ in FIG.

FIG. 29 is a schematic top view of a semiconductor device according to a fifth embodiment of the present invention.

30 is a schematic cross section taken along line X ₁ X ₁ ′ in FIG.

31 is a schematic cross section taken along line X ₃ X ₃ ′ in FIG.

FIG. 32 is a schematic view for explaining the manufacturing process for the semiconductor device according to the sixth embodiment of the present invention.

FIG. 33 is a schematic view for explaining the manufacturing process for the semiconductor device according to the sixth embodiment of the present invention.

FIG. 34 is a schematic cross-sectional view of a semiconductor device according to Example 7.

FIG. 35 is a schematic cross-sectional view of a semiconductor device according to Example 7.

FIG. 36 is a circuit configuration diagram of a semiconductor device according to a seventh embodiment.

FIG. 37 is a schematic view for explaining the method for manufacturing the semiconductor device according to the seventh embodiment.

FIG. 38 is a schematic cross-sectional view of a semiconductor device according to Example 8.

FIG. 39 is a schematic cross-sectional view of a semiconductor device according to Example 9.

FIG. 40 is a schematic cross-sectional view of a semiconductor device according to Example 10.

FIG. 41 is a schematic sectional view of a semiconductor device according to an eleventh embodiment.

FIG. 42 is a schematic cross-sectional view of a semiconductor device according to Example 12.

FIG. 43 is a circuit configuration diagram for explaining a semiconductor memory device.

FIG. 44 is a circuit configuration diagram of a semiconductor memory device according to a thirteenth embodiment.

FIG. 45 is a circuit configuration diagram of a semiconductor memory device according to another embodiment.

FIG. 46 is a schematic top view of a semiconductor memory device according to Example 14 of the present invention.

47 is a schematic cross-sectional view of a semiconductor memory device according to Example 14. FIG.

48 is a schematic sectional view of a semiconductor memory device according to Example 14. FIG.

FIG. 49 is a schematic top view of the semiconductor memory device according to the fifteenth embodiment.

FIG. 50 is a schematic cross-sectional view of a semiconductor memory device according to Example 15 of the present invention.

51 is a schematic top view of the semiconductor memory device according to Example 16 of the present invention. FIG.

52 is a schematic cross section taken along line X ₃ X ₃ ′ in FIG.

53 is a schematic top view of the semiconductor memory device according to example 17 of the present invention. FIG.

54 is a schematic sectional view taken along line X ₃ X ₃ ′ in FIG.

55 is a schematic cross-sectional view for explaining an example of the semiconductor memory device according to the eighteenth embodiment. FIG.

FIG. 56 is a schematic cross-sectional view for explaining an example of the semiconductor memory device according to the eighteenth embodiment.

FIG. 57 is a schematic cross-sectional view for explaining an example of the semiconductor memory device according to the eighteenth embodiment.

FIG. 58 is a schematic cross sectional view for illustrating the example of the semiconductor memory device according to the eighteenth embodiment.

FIG. 59 is a schematic sectional view showing an example of a semiconductor memory device according to Example 18.

FIG. 60 is a schematic sectional view showing an example of a semiconductor memory device according to an eighteenth embodiment.

FIG. 61 is a schematic sectional view showing an example of a semiconductor memory device according to an eighteenth embodiment.

FIG. 62 is a schematic sectional view showing an example of a semiconductor memory device according to Example 18.

FIG. 63 is a schematic cross-sectional view of a semiconductor memory device according to Example 19 of the present invention.

Front page continuation (72) Inventor Genzo Monma 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Ishi ▲ saki ▼ Akira 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Within the corporation

Claims (10)

[Claims] 1. A plurality of main electrode regions provided along a main surface of a substrate, a channel region provided between the main electrode regions, and a gate electrode provided on the channel region via a gate insulating film. An insulated gate transistor having at least two facing portions facing each other, and an electrically destructible memory element provided in one of the main electrode regions. A semiconductor memory device characterized by. 2. The semiconductor memory device according to claim 1, wherein the memory element has a semiconductor layer, and writing is performed by breaking a junction between the semiconductor layer and another layer adjacent to the semiconductor layer. 3. The gate electrode and the high-impurity concentration semiconductor region provided adjacent to the channel region surround at least the entire surface along the carrier movement direction in the channel region. The semiconductor storage device according to 1. 4. A second semiconductor region having the same conductivity type as the channel region and a higher impurity concentration than the channel region is provided on a side of the channel region facing the high impurity concentration semiconductor region. The semiconductor memory device according to claim 3, wherein 5. A third semiconductor region having the same conductivity type as that of the main electrode region and a lower impurity concentration than that of the main electrode region is provided between the main electrode region and the channel region. The semiconductor memory device according to claim 1. 6. The semiconductor memory device according to claim 1, wherein the power supply wiring is long in the source / drain direction of the transistor. 7. The semiconductor memory device according to claim 1, wherein the power supply wiring is long in a direction intersecting the source / drain direction of the transistor. 8. A plurality of main electrode regions provided along a main surface of a substrate, a channel region provided between the main electrode regions, and a gate electrode provided on the channel region via a gate insulating film. A memory cell including an insulated gate transistor having the gate electrode having at least two facing portions facing each other, and an electrically destructible memory element provided in one of the main electrode regions. A plurality of memory cells are provided, and the plurality of memory cells are matrix-connected by a first wiring that commonly connects the gate electrodes of the memory cells and a second wiring that commonly connects the memory elements of the memory cells. A semiconductor memory device characterized in that a power supply line is provided between the second wirings. 9. A plurality of main electrode regions, a channel region provided between them, a gate electrode provided to the channel region via a gate insulating film, and a channel region provided in contact with the channel region. A semiconductor region having the same conductivity type as that of and having a higher impurity concentration than the channel region,
And an electrically destructible memory element provided in one of the main electrode regions, the insulated gate transistor having at least two portions in which the gate electrode opposes each other. A characteristic semiconductor memory device. 10. A plurality of memory cells including the transistor and the memory element are provided, a plurality of first wirings connecting these gate electrodes of the plurality of memory cells in common, and a memory element of the plurality of memory cells. Are connected in a matrix by a plurality of second wirings that commonly connect
10. The semiconductor memory device according to claim 9, wherein a power supply line is provided between the second wirings.