JP3207952B2 - Digital oscilloscope - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in an automatic setting function in a sampling oscilloscope.

[0002]

2. Description of the Related Art A conventional oscilloscope automatic setting function (so-called auto setup function) comprises a peak hold circuit for measuring a peak value of an input signal, a level search of a trigger signal branched from an input section, and a frequency counter. ing. In such a configuration, the maximum value and the minimum value of the input signal are obtained by the peak hold circuit, the unit for each scale of the voltage axis (vertical axis) is determined, and the frequency of the input signal is obtained by the frequency counter. , A unit for each scale on the time axis (horizontal axis) is determined, and an appropriate trigger level for the input signal is obtained by a trigger level search. These actions are:
It is performed automatically under the control of the CPU. At this time, the frequency is obtained by switching the frequency given to the counter and repeatedly measuring the input signal, or preparing a plurality of counters and switching and repeatedly measuring the input signal until the peak value is obtained. Such a method is adopted. However, in the case of a sampling oscilloscope used for high frequency measurement, since the input band is several GHz or more, if the input signal is branched to the peak hold circuit for this automatic setting, the band will drop.
It is difficult to add a peak hold circuit. At the same time, splitting the input signal and inputting it to the frequency counter results in a lower input band. In addition, it is very difficult to manufacture a counter that counts a frequency of several GHz. Furthermore, since the trigger section is configured to input another signal (synchronous signal) by an external trigger, obtaining a set value on the time axis poses a problem. This is because, even if the frequency of the trigger signal is simply counted by the frequency counter, if the trigger is a different signal, it is difficult to obtain an optimum time axis set value.

[0003]

Therefore, the sampling oscilloscope used for high frequency measurement has a problem that it is difficult to operate the automatic setting function with the conventional configuration. An object of the present invention is to solve this problem and to realize a digital oscilloscope that can automatically set even when an input signal has a high frequency in a sampling oscilloscope used for high frequency measurement.

[0004]

According to the present invention, there is provided a sample and hold circuit for sampling a signal input from an input terminal by sequential sampling, a CPU for controlling the overall operation and setting a value, and An analog / digital converter for converting a signal from analog to digital, and the analog / digital converter
These digital data are input and stored, and output to the display system.
A memory that includes a digital / analog converter for digital / analog conversion on the output from the CPU, a comparator for comparing the output from the output and the sample hold circuit from the digital / analog converter, the output from the comparator of the time width is measured, a counter for outputting the measurement result to the CPU, calculates the digital data from the analog / digital converter, digitally provided a digital peak-hold circuit for obtaining the peak value, This is a digital oscilloscope that can be automatically set.

[0005]

Since sampling is performed by sequential sampling and the result is automatically set using the measurement result, it is possible to automatically set the time axis and the like at a high speed without performing an excessive counter operation.

[0006]

FIG. 1 shows a basic configuration diagram of the present invention. In the figure, reference numeral 1 denotes an input terminal for inputting an analog input signal to be measured. Reference numeral 2 denotes a sample and hold circuit which samples a signal input from an input terminal. Reference numeral 3 denotes an analog / digital converter (hereinafter, referred to as “ADC”), which performs analog / digital conversion of a signal from the sample hold circuit 2. A memory 4 stores digital data from the ADC 3 and outputs the digital data to a display system. 5 is a comparator, ADC
3 and the output of the sample-and-hold circuit 2 are compared with each other, and the result is output. 6 is a counter,
The time width of the output signal of the comparator 5 is measured, and the measurement result is output to the CPU 9. Reference numeral 7 denotes a digital / analog converter which performs digital / analog conversion on the output from the CPU 9. Reference numeral 8 denotes a digital peak hold circuit that calculates digital data from the ADC 3 and digitally obtains a peak value. A CPU 9 controls the entire operation and sets values.

The operation of such a configuration will be described with reference to a time chart shown in FIG. a indicates an input signal, b indicates an output signal of the sample-and-hold circuit 5, and c indicates an output of the comparator 5. According to the sequential sampling, the input signal a becomes a signal extended in the time axis direction by the sample-and-hold circuit 2 as shown in b, and this is output to the ADC 3. Note that the sequential sampling is one of the sampling methods usually performed in a sampling oscilloscope.
Specifically, one waveform is collected for one trigger signal that is output once, and the time at which this data is collected is shifted from the time at which the trigger signal is generated by a small amount of time. It is equivalently reproduced. Therefore, even if the input signal exceeds several GHz due to the cycle in which the trigger signal is generated, that is, the sampling frequency and the shift time described above, the sample-and-hold circuit 2 sets
Is a signal enlarged in the time axis direction.

A digital peak hold circuit 8 sets a PEAK value α of digital data between the acquisitions.
β was measured, and the CPU 9 determined the level A as DA
Set to C7. Here, between acquisitions refers to a period until the number of data of sampling data (sampled input signal) reaches a predetermined sampling number. For example, it refers to a period in which the number is determined to be sufficient for screen display.

The output c of the comparator 5 is the result of comparing the signal from the digital peak hold circuit 8 with the voltage level A. When the signal from the digital peak hold circuit 8 is higher than the voltage level A, an H level signal is output, and when the signal is opposite, an L level signal is output. As described above, the input signal of the output of the sample and hold circuit 2 is delayed in time. Therefore, even if the input signal is high-speed without using an expensive high-frequency comparator, the signal c can be output with an accurate operation. For example, assuming that the output of the sample and hold circuit 2 is b 'when the shift time is set to 1/2 the sampling period, the output of the comparator 5 is indicated by c', so that the number of counters is doubled. 2 is also shown in the understanding.

The frequency of the input signal can be calculated from the count result obtained by the counter 6 and the relationship between the sampling trigger signal and the display time axis. Here, just in case, the automatic setting does not refer to the setting of the time axis or the like in the display when the power is first turned on, but the automatic setting as shown in the present invention in the state where the signal is input. Activating the function means setting the optimal time axis for measuring the input signal.

Since the above-mentioned sampling interval is determined by the time axis of the display screen, it is compared with a system in which the gate time of a normal counter is changed to obtain the frequency of the input signal, and directly (calculated once). Optimal time axis settings can be made (without re-doing). The time axis is set based on such a method shown in the present invention, and the voltage axis is set from the values of α and β. Therefore, automatic setting can be performed at high speed.

Further, since the PEAK value by the digital peak hold circuit 8 and the number of counters by the counter 6 are updated every acquisition, the optimal voltage axis and time axis can be automatically set at high speed on the display screen. Becomes Furthermore, this sampling method uses aliasing to count the signal after sampling.
Count errors may occur. In this case, the acquisition time is measured by the CPU to confirm the aliasing and determine whether or not the count value is valid.

[0013]

As is apparent from the above description,
According to the present invention, the following effects can be obtained . sequential
Sample by sampling and use the measured result
By automatically setting, even if the input signal is high-speed, it is possible to automatically set the display screen appropriately and in accordance with human thinking without preparing a high-speed counter. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of the present invention.

FIG. 2 is a time chart showing the operation of the present invention.

[Explanation of symbols]

 1 input terminal 2 sample and hold circuit 3 ADC 4 memory 5 comparator 6 counter 7 DAC 8 digital peak hold circuit 9 CPU

Claims (1)

(57) [Claims] 1. A sample and hold circuit for sampling a signal input from an input terminal by sequential sampling, a CPU for controlling the overall operation and setting a value, and an analog for converting a signal from the sample and hold circuit into an analog / digital signal / Digital converter and digital data from the analog / digital converter.
Input and stored, the memory for output to the display system, and a digital / analog converter for digital / analog conversion on the output from the CPU, an output from the digital / analog converter the sump <br/> Ruhorudo circuit a comparator for comparing the output from the time width of the output from the comparator measures, calculates a counter for outputting the measurement result to the CPU, and the digital data from the analog / digital converter, digitally A digital oscilloscope which is provided with a digital peak hold circuit for obtaining a peak value and can be automatically set.