JP3205099B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device suitable for use as a driving device of a device using switching elements in upper and lower arms such as an inverter, and particularly to a large voltage fluctuation in an inverter driving device and the like. The present invention relates to a semiconductor integrated circuit device suitable for use in preventing malfunctions due to mutual interference between upper and lower arms and between upper arm phases to which noise is added and noise.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a configuration of a three-phase inverter using an IGBT as a switching element for explaining the prior art. In FIG. 6, 1 is a main power source, 2
Is an upper arm switching element, 3 to 5 are lower arm switching elements, 6 to 8 are upper arm drive circuits, 9 to 11 are output stage elements, 12 is a level shift circuit, and 13 is a lower arm drive circuit.

In general, as shown in FIG. 6, an inverter comprises a main power supply 1 obtained by rectifying 200 V AC of a commercial power supply, and a high-voltage side arm (hereinafter referred to as a totem pole connection (series connection) between terminals thereof). , An upper arm) and a power switching element unit including a power switching element 3 to 5 of a low-voltage side arm (hereinafter, referred to as a lower arm), and upper arm driving circuits 6 to 8 for driving them. It comprises output stage elements 9 to 11, a level shift circuit 12, and a lower arm drive circuit 13.

In the above, IGBTs, MOSFETs and the like are used as power switching elements, and the driving circuit 6
8 and 13 are driven. The power switching element unit includes a power switching element 2 that forms an upper arm for three phases of U, V, and W and a U that forms a lower arm between terminals of a main power supply 1 in which commercial power AC200V is rectified. , V,
The power switching elements 5, 4, and 3 for three phases of W are connected by totem pole connection.

The switching elements 3 to 5 constituting the lower arm are driven and controlled by a lower arm drive circuit 13. Also, the switching element 2 forming the upper arm
Are driven in a floating state with respect to the reference potential, U, V, and V are high-voltage side circuits to which drive signals are transmitted from the lower arm drive circuit 13 that is a low voltage side circuit via the level shift circuit 12. It is driven by drive circuits 6 to 8 for three phases of W and output stage elements 9 to 11.

The above-described inverter device has upper and lower arm driving circuits 6 to 8, 13, a level shift circuit 12, and an output stage element 9 in order to reduce the area and increase the speed of signal transmission.
To 11 are configured as monolithic integrated circuits.

[0007] As a prior art relating to this type of inverter device, for example, “The 4-th International Sympo”
sium on Power Semiconductor Devices & ICs 1992 ”, '500V Three Phase Inverter ICs Based
on a New Dielectric Isolation Technique 'A. Nakaga
wa Toshiba R & D Center and (*) Semiconductor Grou
p), etc. are known.

In the inverter according to the prior art,
When the inverter operates on the main power supply 1 rectifying AC200V, the inverter driving device of the monolithic configuration includes the upper arm driving circuits 6 to 8, the output stage elements 9 to 11 corresponding to these driving circuits, and the lower arm driving circuit 13. 400 between each phase of the upper arm drive circuits 6 to 8
Since a voltage difference of 600 V is generated, the drive circuit of the upper arm and the drive circuit of the lower arm are provided on separate dielectric isolation semiconductor islands.
Similarly, the drive circuit of each phase of the upper arm is formed on a separate dielectric isolation semiconductor island.

However, in the prior art configured as described above, it is conceivable that noise is generated between the semiconductor islands due to the voltage change dv / dt at the time of switching, and this noise is generated by the lower arm drive circuit system. logic,
The effect of the other upper arm drive circuit on each phase has not been sufficiently considered.

[0010]

The prior art described above is
When using a rectified power supply from a commercial 200V AC power supply,
A voltage fluctuation of 280 V to max 600 V may be applied to the inverter driving device operating in the inverter module due to a ripple of the power supply, a voltage for the regenerative power supply, and a jump voltage due to an inductance of wiring in the module. is there.

When the driving circuit is constituted by a driver IC constituted by one chip and used, the driving circuit of the upper arm is driven by a signal via a level shift circuit to drive an output element such as an IGBT. This operation is performed.

FIG. 7 is a sectional view of a dielectric isolation substrate showing a part of the configuration of a driver IC in which a drive circuit is formed by one chip.

Now, for example, from the state in which the U-phase lower arm switching element 5 is on and the state in which the V-phase lower arm switching element 4 is on, only the V-phase lower arm switching element 4 is turned off. And In this case, in FIG. 7, the potential of the semiconductor island 15 constituting the V-phase upper arm drive circuit is set to GND because the V-phase lower arm switching element 4 is turned off and the V-phase upper arm switching element is turned on. Or power supply potential (15V)
From 280V to max600V.

At this time, the parasitic capacitance C of the semiconductor island isolation oxide film 16 and the rise of this potential dv / dt cause Cd
A noise current of v / dt is generated. When this noise is taken into a single crystal island other than the V-phase upper arm drive circuit single crystal island 15, it affects the drive circuits in these islands.

That is, in the above-described conventional technology, the potential of the single crystal island forming the drive circuit fluctuates rapidly due to the operation of the switching element forming the arm. As a result, interference between the drive circuits, malfunction, and the like occur. Is caused.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to be suitable for use in an inverter driving device or the like which can prevent the above-mentioned malfunction due to mutual interference and noise with a minimum chip size. An object of the present invention is to provide a semiconductor integrated circuit device.

[0017]

According to the present invention, the object is to provide a substrate holding dielectric isolated semiconductor islands on which a drive circuit and the like are formed, and a potential between the dielectric isolated semiconductor islands. Is achieved by fixing the potential of the floating polysilicon portion and absorbing noise by this potential.

That is, the object is to provide a dielectric isolated semiconductor island in which a drive circuit for each phase having a different upper arm is provided between dielectric isolated semiconductor islands in which a drive circuit of a switching element constituting an upper and lower arm is formed. At least one contact portion for polysilicon is provided between them, and the polysilicon substrate portion is fixed at a constant potential, or the island interval between the islands is increased at a constant interval, and , A metal wiring is provided, and at least one contact is provided.
Alternatively, this is achieved by wiring the wiring so as to have a constant potential and fixing the potential.

[0019]

By providing a contact between the dielectric isolation semiconductor islands and fixing the potential to GND or a constant potential, noise generated by a large voltage fluctuation is transmitted through the polysilicon substrate portion via the island isolation oxide film. This noise can be absorbed when trying to flow to another semiconductor island.

Thus, when the inverter is driven by using the semiconductor integrated circuit device according to the present invention, it is possible to prevent a malfunction due to mutual interference between upper and lower arms and between upper arm phases and noise.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the semiconductor integrated circuit device according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing an arrangement according to functions of an inverter driving device having a monolithic structure according to an embodiment of the present invention. The embodiment of the present invention is an example in which the drive unit of the inverter according to the prior art described with reference to FIG. 6 is made monolithic according to the present invention. FIG. 2 is an enlarged view of a portion A in FIG. 1 for explaining the first embodiment of the present invention.
FIG. 3 is a sectional view taken along line BB of FIG. 2. 1 to 3, 1
Reference numerals 8 to 20 denote semiconductor islands on which the driving circuits 6 to 8 for the upper arm three phases and their output stage elements 9 to 11 are formed, respectively.
Reference numeral 21 denotes an output stage element of the lower arm drive circuit. Reference numeral 22 denotes a drive circuit and an output stage element for each phase between the dielectric isolation semiconductor islands constituting the upper arm drive circuit and the lower arm drive circuit, and for each phase of the upper arm. Exposed portions of the polysilicon substrate such as between the dielectric isolation semiconductor islands, 24 are metal wirings, 25 is a contact, 26 is a high concentration impurity semiconductor layer, 27 is a polysilicon substrate, and 16 and 17 are oxide films. is there.

The inverter driving apparatus according to the embodiment of the present invention shown in FIG. 1 is formed on a dielectrically separated semiconductor substrate, and includes driving circuits 6 to 8 corresponding to three phases of the upper arm and output stage elements 9 to 11, respectively. Are formed in the semiconductor islands 18 to 20 for each phase, and the level shift circuit 12, the lower arm drive circuit 13, and the lower arm output stage element 21 are respectively formed in other semiconductor islands.

Then, between the semiconductor islands on which the drive circuits and the like for the upper-arm switching elements are formed, and between these semiconductor islands and the semiconductor islands on which the drive circuits and the like for the lower-arm switching elements are formed. The exposed portion 22 of the polysilicon substrate, which is exposed to the outside, is provided in a strip shape wider than the exposed portion of the polysilicon substrate of the other separation portion in order to provide a contact according to the present invention.

In the exposed portion 22 of the polysilicon substrate,
As shown in the enlarged views and cross-sectional views of FIGS. 2 and 3, a metal wiring 24 connected to GND or a constant potential is provided, and a contact 25 is provided in at least one of the metal wirings 24, and the potential of the polysilicon substrate 27 is reduced. Are fixed to GND or a constant potential. The contact 25 electrically connects the metal wiring 24 thereon and the polysilicon substrate 27 via an n-type or p-type high-concentration semiconductor layer 26 provided on the polysilicon substrate. Further, the contact 25 is formed by providing a step in the protective oxide film 17 provided on the surface of the substrate in order to ease the coverage of the contact wiring, and forming the metal wiring 24 in that portion.

When the first embodiment of the present invention configured as described above is applied to an inverter driving device that operates in an inverter module having a main power supply obtained by rectifying a commercial 200 V AC power supply, as described above. Due to the ripple of the power supply, the voltage of the regenerative power of the power supply, the jump voltage due to the inductance of the wiring in the module, etc., a maximum of 400 to 600
V voltage fluctuation may be added.

For example, in FIG. 6, when the U-phase lower arm switching element 5 is turned on and the V-phase lower arm switching element 4 is turned on, only the V-phase lower arm switching element 4 is turned off. In 3, U
The potential of the semiconductor island 18 on which the phase upper arm drive circuit is formed is GND or the power supply potential (15 V), and the potential of the semiconductor island on which the V phase lower arm drive circuit is formed is GND.
Alternatively, from the state of the power supply potential, the potential of the semiconductor island 19 on which the V-phase upper arm drive circuit is formed rapidly rises from 280 V to max.
May rise to 600V. At this time, a noise current of Cdv / dt is generated by the parasitic capacitance C of the oxide film 16 separating the respective semiconductor islands and the rise dv / dt of the voltage, so that the V-phase upper arm drive circuit is formed. It flows out from the island 19 to the polysilicon substrate 27.

However, according to the above-described embodiment of the present invention, since the potential of the polysilicon substrate 27 is fixed to GND or a fixed potential, the noise current is absorbed by this potential and the U-phase upper arm driving circuit is absorbed. Are not taken into the semiconductor island 18 in which is formed, and it is possible to prevent mutual interference and malfunction from occurring.

Similarly, it is possible to prevent the noise current from affecting circuits in other semiconductor islands.

FIG. 4 is a diagram for explaining a second embodiment of the present invention. The reference numerals in FIG. 4 are the same as those in FIG.

The second embodiment of the present invention is an example in which a metal wiring 24 is provided along an exposed portion 22 of a polysilicon substrate separating each semiconductor island.

In this embodiment, the wiring between the phases of the upper arm drive circuit and the wiring between the upper arm drive circuit and the lower arm drive circuit, which cause a high potential difference, generate parasitic capacitance via the oxide film 17 on the polysilicon substrate. In order to alleviate the parasitic capacitance between the wirings having a high potential difference, a metal wiring 24 is provided along the exposed portion 22 of the polysilicon substrate, and a contact 25 is provided at at least one position. Things.

FIG. 5 is a view for explaining a third embodiment of the present invention, in which contacts 25 are provided at the corners of four semiconductor islands.

As described above, by providing the contacts 25 at the corners of the four semiconductor islands, the width of the polysilicon substrate between the semiconductor islands, which has been widened for providing the contacts 25, can be reduced, and the chip area can be reduced. Can be reduced.

The contact 25 is provided on the oxide film with a step 28 having a shape such that the shape of the step enters the corner of the dielectric isolation island, and the metal wiring 24 extends over the isolation oxide film on the semiconductor island. The insulation withstand voltage is not reduced.

In each of the embodiments of the present invention described above, a plurality of contacts 25 can be provided as necessary. In the above-described embodiment of the present invention, the driving circuit is configured to be monolithically formed in one semiconductor island. However, in the present invention, the above-described semiconductor island is formed as a semiconductor island group having a plurality of semiconductor islands. The driving circuit may be configured as follows.

In the above-described embodiments of the present invention, the present invention has been described as being applied to a circuit for driving a switching element of an inverter. However, the present invention is applicable to various devices having a power switching element on upper and lower arms. The present invention can be applied to a driving circuit of a switching element and the like.

[0038]

As described above, according to the present invention, the present invention is used for a driving circuit of a switching element such as a power conversion device having a power switching element in an upper and lower arm, and is used between driving circuits and an element of an upper arm. A semiconductor integrated circuit device capable of preventing a malfunction due to mutual interference and noise between the phases of the drive circuit and performing a stable operation can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing an arrangement according to functions of an inverter driving device having a monolithic configuration according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a first embodiment of the present invention, which is an enlarged view of a portion A in FIG. 1;

FIG. 3 is a sectional view taken along line BB of FIG. 2;

FIG. 4 is a diagram for explaining a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a third embodiment of the present invention.

FIG. 6 shows a switching element for explaining the prior art,
FIG. 3 is a block diagram showing a configuration of a three-phase inverter using a GBT.

FIG. 7 is a sectional view of a dielectric isolation substrate showing a part of a configuration of a conventional driver IC in which a driving circuit is formed by one chip.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main power supply 2 Upper arm switching element 3-5 Lower arm switching element 6-8 Upper arm drive circuit 9-11,21 Output stage element 12 Level shift circuit 13 Lower arm drive circuit 16,17 Oxide film 18-20 Semiconductor island 22 Exposed portion of polysilicon substrate 24 Metal wiring 25 Contact 26 High concentration semiconductor layer 27 Polysilicon substrate

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-270677 (JP, A) JP-A-61-224343 (JP, A) JP-A-62-51740 (JP, U) (58) Investigation Field (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/3205 H01L 21/822

Claims (7)

(57) [Claims] 1. A semiconductor integrated circuit device in which a drive circuit for driving a switching element forming an upper arm and a lower arm is formed on a plurality of semiconductor islands in a dielectric isolation substrate. Metal along the exposed portion of the polysilicon substrate, which is the support for the semiconductor island exposed to the
Wiring is performed, and the exposed portion of the polysilicon substrate portion is exposed.
An opening having a step is provided in the oxide film formed thereon, and a contact is arranged , whereby the potential of the polysilicon is set to G.
A semiconductor integrated circuit device fixed at ND or a constant potential. Wherein said contact is via a high-concentration impurity semiconductor layer of n-type or p-type provided on the surface of the polysilicon, to connect the connecting metal wires to polysilicon and GND or a constant potential the semiconductor integrated circuit device according to claim 1, wherein the this. 3. A semiconductor integrated circuit device in which a drive circuit for driving a switching element forming an upper arm and a lower arm is formed on a plurality of semiconductor islands in a dielectric isolation substrate. Metal along the exposed portion of the polysilicon substrate, which is the support for the semiconductor island exposed to the
Wiring is performed, and the exposed portion of the polysilicon substrate portion is exposed.
The oxide film formed on places the con <br/> tact with an opening having steps, the exposed portion to which the contact is provided, the strip width is not wider than the other exposed portion by the contact A semiconductor integrated circuit device wherein the potential of polysilicon is fixed to GND or a fixed potential. 4. A semiconductor integrated circuit device in which a drive circuit for driving a switching element forming an upper arm and a lower arm is formed on a plurality of semiconductor islands in a dielectric isolation substrate. Formed on at least one of the exposed portions of the polysilicon substrate portion , which is a support for the semiconductor island exposed to the outside, on the exposed portion of the polysilicon substrate portion.
A contact is formed by providing a stepped opening in the
And the contacts are provided at the corners of four semiconductor islands
It is and, thereby, GND potential of the polysilicon
Alternatively, a semiconductor integrated circuit device fixed at a constant potential. 5. The method according to claim 1, wherein the contact is a surface of polysilicon.
The high-concentration impurity semiconductor layer n Katachima other of p-type provided in
Connected to polysilicon or GND or constant potential
5. The semiconductor integrated circuit device according to claim 4 , wherein said semiconductor integrated circuit device is connected to said metal wiring . 6. A switch constituting an upper arm and a lower arm.
The drive circuit for driving the
Semiconductor integrated circuit device formed on a number of semiconductor islands
The semiconductor islands exposed between the semiconductor islands.
Four semi-conductors of the exposed part of the polysilicon substrate part which is the support
On the corner of the body island, on the exposed part of the polysilicon substrate part
An opening with a step is provided in the formed oxide film to
And expose the exposed portion where the contact is provided to another
In the form of a band wider than the exposed part, by the contact,
The potential of polysilicon is fixed to GND or constant potential
A semiconductor integrated circuit device characterized by the above-mentioned. 7. A switch constituting an upper arm and a lower arm.
The drive circuit for driving the
Semiconductor integrated circuit device formed on a number of semiconductor islands
The semiconductor islands exposed between the semiconductor islands.
Metal wiring is exposed on the exposed part of the polysilicon substrate
And at least one of the polysilicon substrates
The oxide film formed on the exposed part of the plate part has a stepped opening
Parts are arranged and contacts are arranged, and the four contacts are provided.
At the corners of the semiconductor island
Silicon potential fixed to GND or constant potential
A semiconductor integrated circuit device characterized by the above-mentioned.