JP3139313B2 - Bipolar semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar semiconductor integrated circuit having an improved element layout pattern and circuit configuration.

[0002]

2. Description of the Related Art In a bipolar semiconductor integrated circuit, since each element is separated by a PN junction, a target element, for example, an adjacent PNP or NPN junction region appears between transistors. Therefore, equivalently,
A transistor is formed by the isolation region and a part of elements on both sides thereof, and a parasitic element, for example, a parasitic transistor appears depending on an applied voltage, and a parasitic effect unfavorable as a semiconductor circuit occurs.

Japanese Patent Publication No. 4-67787 discloses a bipolar integrated circuit in which the active elements are separated by a PN junction, and the current flowing through an output transistor is increased without increasing the chip area of the semiconductor integrated circuit. A parasitic element that appears between the control transistor and the output stage transistor by interposing the output stage transistor on one side and the control transistor on the other side with the current supply transistor Which suppresses the parasitic effect caused by the above.

[0004]

However, when a negative potential is applied to the output stage transistor when driving a motor load or the like, the arrangement of the output stage transistor, the current supply transistor, and the transistor in the control circuit is concerned. Depending on the arrangement on the semiconductor pattern, the parasitic effect may not be sufficiently reduced and a malfunction may occur.

[0005] FIG. 12 illustrates a time course of the motor terminal voltage (V _M) and the motor current (I _M) when driving the DC motor. A negative current is generated when the motor rotates and stops, and at this time, a negative voltage is generated in the output stage transistor. This negative current is several hundred mA in the case of an in-vehicle motor. In such a case, a malfunction may occur as described above.

SUMMARY OF THE INVENTION It is an object of the present invention to further suppress the parasitic effect and eliminate malfunction even when a negative potential is applied during driving of a motor load or the like.

[0007]

According to a first aspect of the present invention, there is provided an output circuit section formed on one integrated circuit chip and having an output transistor.
And a control circuit section having a control transistor for controlling the output circuit section. In a bipolar semiconductor integrated circuit in which each element is separated from each other by a PN junction, of the control transistors, on the integrated circuit chip all the transistors are formed on a rectangular, Ri name to place its short sides towards the output stage transistor side and the output
Around the stage transistor, on the side of the control transistor.
Epitaxy of at least three of the side and two adjacent sides
And the output layer is connected to the output stage.
A parasitic transistor formed between the transistor and the control transistor
To function as a collector of the transistor is characterized in Rukoto.

[0008]

[0009] The invention of claim 2, claim 1
In bipolar semiconductor integrated circuit according to the control circuit is comprise a NPN transistor, the N
A constant current is supplied to the emitter of the PN transistor.
To form a capacitor using the PN junction capacitance of the base and emitter, and connect the base and collector to ground
And the control circuit is configured to
The output circuit section is delayed by using the charging time of the capacitor.
It is characterized by controlling by

[0010] Further, the invention according to claim 3 is one collection.
Formed on an integrated circuit chip, with output stage transistors
Output circuit section and a control transformer for controlling the output circuit section.
And a control circuit section having a transistor.
Junction-separated bipolar semiconductor integrated circuits
The integrated circuit chip among the control transistors.
All transistors formed in a rectangle on the
With its short side facing the output stage transistor side
And the control circuit section includes an NPN transistor.
This NPN transistor is
The constant current is supplied to the PN junction of the base and the emitter.
While forming a capacitor using the capacity, the base,
The collector is connected to ground potential,
The control circuit unit utilizes the charging time of the capacitor.
And delaying and controlling the output circuit section.
I have. The invention described in claim 4 is the invention according to claim 2 or 3
3. The bipolar semiconductor integrated circuit according to claim 1, wherein the output circuit unit includes a current supply transistor that supplies a current to the output stage transistor, and the current supply transistor
Are those in which the collector of the emitter and the output stage transistor of the motor current to the output stage transistor from a connected said current supplying transistor is supplied, the charging time of the capacitor formed in the control circuit unit using, and the output stage transistor and the current supply transistor is characterized in that so as not to turn on at the same time.

According to a fifth aspect of the present invention, there is provided a bipolar semiconductor integrated circuit which is formed on one integrated circuit chip, has an output stage transistor and a control transistor for controlling the output stage transistor, and is PN junction separated. In the bipolar semiconductor integrated circuit, there is provided a parasitic current detecting means for detecting a parasitic current generated between the output stage transistor and the control transistor, and a current corresponding to the parasitic current is detected by the parasitic current detecting means. It is characterized in that it is supplied to the output side of the collector and the emitter of the transistor to cancel the parasitic current.

[0012] The invention according to claim 6 is the same as the invention according to claim 5.
In the bipolar semiconductor integrated circuit described in the above, the parasitic current detecting means controls the current equivalent to the current flowing through the epitaxial layer formed near the control transistor and from which a current corresponding to the parasitic current is drawn out. And a current mirror circuit for supplying the output side of the collector and the emitter of the transistor for use.

[0013]

According to the first aspect of the present invention, the parasitic current generated in the control transistor is proportional to the collector facing length of the control transistor with respect to the output stage transistor to which a negative potential is applied. The parasitic current can be reduced only by considering the arrangement of the transistors. By setting the current to be higher than the parasitic current, malfunction can be avoided.

Further, by operating the epitaxial layer as a collector of the parasitic transistor, the parasitic current generated in the control transistor can be further reduced. Further, according to the invention described in claim 2, 3, control
Parasitic current generated in the transistor for
In the case where a parasitic transistor is formed by a negative potential input, only a current is drawn from the collector of the grounded NPN transistor, so that a malfunction does not occur due to a capacitor and a stable delay time is always generated.
Thus, the output circuit section can be controlled.

According to the fourth aspect of the present invention, since the time constant is formed by using the capacitor according to the second or third aspect, the current supply for the current supply formed in the output circuit portion is provided.
Simultaneous ON of transistor and output stage transistor
Current penetration inside the integrated circuit chip can be eliminated, and element destruction due to overcurrent can be prevented. Claims 5 and 6
According to the invention described in (1), a current corresponding to a parasitic current generated in the control transistor is detected and supplied to the control transistor. By supplying the control current to the control transistor, it is possible to control the output stage transistor in which the influence is removed by the direct detection of the parasitic current.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of a forward / reverse motor drive circuit. Here, reference numeral 23 denotes a control circuit, reference numerals 20 and 21 denote signal input terminals, reference numeral 22 denotes a power supply input terminal for the control circuit, reference numeral 24 denotes an attached heat cutoff circuit, and the like. Built-in. On the output side of the control circuit 23, an output circuit formed by a combination of a transistor and a diode is configured.

In the output circuit, 25 and 27 are NPN transistors for supplying current, and 46 and 47 are PNP transistors for driving the transistors. Reference numerals 26 and 28 denote NPN transistors for absorbing current. These 26 and 28 are so-called output stage transistors. FIG.
Output power supply input terminals for supplying power to the NPN transistors 5, 27, 29, 30, 31, and 32 are output clamp diodes, and 34 and 35 are output terminals. The output terminals 34 and 35 are connected to a DC motor 50 as an output load. The terminal 36 is a ground terminal (OV). The motor 50 depends on the state of the signal input terminals 20 and 21.
Is controlled to rotate forward, reverse, or stop.

FIG. 2 shows the output transistor 2 shown in FIG.
6 is a diagram schematically illustrating a cross-sectional configuration of a chip of a bipolar semiconductor integrated circuit, focusing on a current supply NPN transistor 25 and a transistor 61 in a control circuit. A buried layer 3 is formed in a silicon P-type substrate 1, on which N-type epitaxial layers 4, 41, 42, and 43 separated by a separation layer 2 by P-type diffusion are formed. Bases 5a to 5 formed by P ⁺ diffusion are formed on the upper part of the N-type epitaxial layer.
The respective regions of emitters 6a to 6c by c and N ⁺ diffusion and collectors 7a to 7d by N ⁺ diffusion are formed.

The bases 5a to 5c are provided with base terminals 8
a to 8c and emitters 6a to 6c have an emitter terminal 9a.
To 9c and collectors 7a to 7c have a collector terminal 10
a to 10c are ohmic-connected. The hatched area indicated by reference numeral 11 separating the terminals is an oxide film. Here, between the output stage transistor 26 and the current supply transistor 25,
The epitaxial layer 41 sandwiched between the separation layer 2 is disposed, GN into the epitaxial layer 41 through the N ⁺ diffusion region 7 d
The D terminal 16 is connected. In this case, it may be wired to _Vcc instead of being connected to the GND terminal. Further, the transistor 61 included in the control circuit 23 in FIG. 2 is arranged on the opposite side of the current supply transistor 25 and the output stage transistor 26.

When a negative voltage as shown in FIG. 12 is applied to the output terminal 35 connecting the emitter 6b of the transistor 25 and the collector 7c of the transistor 26 with aluminum wiring, as described in the prior art, A parasitic NPN transistor 15 having the collector region 4 of the output transistor 26 as an emitter, the isolation layer 2 as a base, and the epitaxial layer 41 as a collector is generated. The current amplification factor h _FE of the transistor 15 is generally low, but when the negative voltage applied to the output terminal 35 increases, the current flowing from the epitaxial layer 41 also increases.

On the other hand, since the above-mentioned parasitic transistor 15 has a lateral structure, the collector is a multi-collector, and the collector of the transistor 25 and other elements on the chip constituting the control circuit, for example, the transistor 6
Also connected to one collector. Therefore, output terminal 3
If the negative voltage to 5 becomes large, the current drawn from the above-mentioned element in the control circuit becomes large, and a malfunction occurs. FIG. 3 shows an equivalent circuit of this parasitic transistor configuration. Here, the base of the transistor 62 is connected to the collector of the transistor 61, and the transistor 61 is an input stage of the transistor 62.
The transistors 61 and 62 are transistors constituting a logic circuit in the control circuit, and 71 to 73 are parasitic transistors represented by equivalent circuits.

The parasitic transistor 15 shown in FIG.
In FIG. 3, this is indicated by a parasitic transistor 71, which is equivalent to a diode whose collector and base are short-circuited. The parasitic transistor connected to the collector of the transistor 25 in FIG. 2 is indicated by 72, and the parasitic transistor 71 has a common base and emitter. The parasitic transistor connected to the collector of the transistor 61 in the control circuit is indicated by 73. This transistor 61
The sw1 is driven based, by a constant current source I _1, to <br/> drives the next stage of the transistor 62 to change the collector potential.

In the above configuration, when a negative voltage is applied from the output terminal 35, current is not only drawn from the common emitter of the parasitic transistors 71 to 73, but also another NPN on the integrated circuit chip is operated by a current mirror operation. Current will also be drawn from the collector of the transistor.
Thus by the negative potential, the collector current I ₇₃ becomes large from the constant current source I ₁ of the parasitic transistor 73, without the transistor 62 causes the normal operation to the base current at the OFF time of the transistor 61 to the transistor 62 of the next stage is not supplied, Therefore, a malfunction occurs in the semiconductor integrated circuit constituting the entire circuit.

In the present invention, when a negative voltage is applied to the output terminal 35, the parasitic current caused by the current drawn from the output terminal 35 is reduced by a collector (an N-type collector such as an NPN transistor) forming each parasitic transistor. (Region) It was quantified that there was a proportional relationship with the ratio of facing length as shown in FIG. In FIG. 4, the horizontal axis represents the collector facing length ratio _RL in the plane pattern, and FIG. 5 shows the plane pattern of the output stage circuit portion and the one-part control circuit in FIG. Peripheral epitaxial layer region 10 for length L _A and output stage transistor 26
0 ratio of the opposing length L _c of. The vertical axis _RI indicates the ratio of the parasitic current I ₇₃ of the transistor 61 to the parasitic current I ₇₁ of the epitaxial layer region 100.

This is because the current density in the cross-sectional direction via the base of the P diffusion separation layer is considered to be substantially equal, and therefore the current value tends to increase as the cross-sectional area between the collector and the emitter of the lateral NPN transistor increases. Is shown. Here, since the depth direction is the same, the facing cross-sectional area and the facing length have a proportional relationship. For example, the ratio of the collector facing length of the parasitic transistor 71 of FIG. 3 (the transistor 15 of FIG. 2) to the collector facing length of the parasitic transistor 73 is 1/10.
At 0, the ratio between the current I ₇₁ to be _extracted and the parasitic collector current I ₇₃ is about 10 ⁻⁵ . And
For example, when I ₇₁ is 0.3 A, I ₇₃ is about 3 μA.

Due to the above quantitative relationship, a negative voltage is applied to the output terminal 35.
If the current generated by the potential is clarified, the parasitic current I₇₃
And the constant current value I of the control circuit shown in FIG._ITo I_I
-I ₇₃> Ic_min(Ic_minDrives the transistor 62
), The transistor 62 at the next stage is
A sufficient driving current can be secured. Therefore, applying a negative potential
Even at times, good semiconductor integrated circuits without malfunction
Can provide roads.

FIG. 5 shows a specific layout of each element described in FIG. 1 in a planar layout pattern on a semiconductor chip. The transistors 25 to 28, 46, 47 and the diodes 29, 31 correspond to the element numbers shown in FIG. Reference numerals 100 and 101 represent N-type epitaxial layer regions. Further, the circuit blocks 23 and 24 in FIG.
5, and is not shown in FIG. 5. Here, R on the horizontal axis in FIG.
_L (collector facing length ratio) is the value of transistor 6 in the control circuit.
Collector facing length ratio around the N-type epitaxial layer 100 of the transistor 26 for a collector facing length L _A L
_Represents the ratio to _C.

As described above, the N-type epitaxial layer region 1
00 surrounds the output transistor,
The proportion occupied by the parasitic collector current of the parasitic transistor 71 shown in FIG. 3 is increased, so that the proportion of the collector current value of the parasitic transistors 72 and 73 which may cause a malfunction is reduced. Although the above configuration is effective, the present invention is characterized by the following point in order to further reduce the parasitic current. That is, at least one transistor 61 for connecting a constant current power supply to the collector is incorporated in at least one of the circuit blocks 23 and 24 arranged on the upper surface of the chip, and the short side of the rectangular planar pattern of the transistor is an output transistor. 26 and 28. Although only one transistor (transistor 61) in the control circuit is shown in FIG. 5, among transistors in the control circuit, all transistors in a rectangular pattern are arranged in the same manner as the transistor 61 described above. Have been.

As described above, the short side of the planar pattern of the transistor element shape 5 of the control circuit including the transistor 61 is opposed to the output transistors 26 and 28 , so that the ratio of the opposing length of the horizontal axis shown in FIG. Can be reduced from the long side length to the short side length of the transistor 61. Generally, the ratio of the long side length to the short side length is about 3: 2, which can be reduced to about 2/3. Therefore, the parasitic current ratio on the vertical axis can be reduced. By setting the pattern arrangement of the transistors constituting the control circuit and the like to be opposite to the short sides, the parasitic current value due to the application of the negative potential to the output terminal can be reduced. Therefore, with the arrangement structure of FIG. 5, a configuration in which a malfunction does not easily occur is obtained.

Since the parasitic current is calculated based on the load state and the pattern layout in the circuit configuration, a malfunction due to the parasitic can be completely prevented by supplying a higher control current. In FIG. 5, the transistor 61 is arranged above the output transistors 26 and 28 , and thus has the orientation shown in FIG.
6, 28 the orientation of the transistor 61 when it is disposed on the left and right of the the short side L _A becomes the direction rotated 90 ° from the shown faces the output transistor 26, 28 side. When the transistor 61 is arranged obliquely upward at 45 degrees with respect to the output transistors 26 and 28, the former is the direction shown in FIG. 5 when the direction is higher than the 45 degrees direction, and the latter is the direction shown in FIG. The direction is rotated 90 degrees from the direction of 5. This is true for all transistors patterned on a rectangle in the control circuit.

FIG. 6 shows a specific structure and wiring for a section taken along the line AA ′ of FIG. Here, the cross section of the epitaxial layer region 101 is omitted. FIG. 6 shows FIG.
The same elements as those described above are given the same numbers. 26, 29, 25, 46, and 61 indicated by broken lines indicate the same element numbers as those shown in FIG. This embodiment shows a sectional arrangement and a wiring method.

FIG. 7 shows another embodiment of FIG. 5. In the case where there is a dicing surface below the output stage transistors 26 and 28, there are no elements which cause a parasitic effect below the dicing surface. It has a surrounding configuration. As described above, according to the above-described embodiment, in the bipolar semiconductor integrated circuit, the epitaxial layer regions are arranged in at least three directions of the output stage transistor without significantly increasing the chip size of the integrated circuit. By setting the short side of at least one transistor constituting this circuit to the output stage transistor and setting the set value of the constant current section such as the control circuit section beyond the parasitic current, It is possible to provide a good semiconductor integrated circuit that does not cause a circuit malfunction while effectively reducing parasitic effects due to elements.

FIG. 8 shows a specific circuit of FIG. 1, and the same elements and the same circuit blocks are denoted by the same reference numerals. Note that the diodes 29 to 32 are omitted. Signal input terminal 2
0, the comparator 82 connected to the signal input terminal 21, and the transistor 5 connected to each comparator.
Inverter 8 composed of transistors 1, 53 and transistors
7, 88, each having its output connected to transistors 52, 54. The collectors of these transistors 51, 52, 53, 54 have I ₁₀ , I
A constant current power supply set to ₂₀ , I ₃₀ and I ₄₀ and a capacitor 5
7, 58, 59 and 60 are connected to the comparators 83 to 86 at the same time. These comparators are connected to transistors 46, 25, 26, 28, 27, 47 constituting an output circuit via a logic circuit.

In the present invention, the signal input terminals 20 and
The comparators 81 and 82 operate according to the potential input to 21 , and when this output changes, for example, when the transistor 53 shifts from ON to OFF, the capacitor 5
9 proceeds to the charging by I _30,

[0035]

## EQU1 ## Since the threshold voltage of the comparator 85 is not reached until t _d = C ₅₉ * V _ref5 / I _30, a delay occurs. Here C ₅₉ is the capacitance value of the capacitor 59, V _REF5 represents the threshold voltage of the comparator 85. Accordingly, the comparator 85 to be connected to the next stage after this t _d is operated, a signal is transmitted to the logic circuit.

In the present invention, by utilizing the delay caused by the constant current charging of the capacitor and providing a time difference to the signal to the logic circuit block, the current supply transistor 25 or 27 shifts from OFF to ON, or Due to the delay when the output transistor 26 or 28 shifts from OFF to ON, simultaneous ON of the current supply and output transistors connected by wiring is prohibited.

Next, the specific logic will be described. Table 1 shows the relationship between signal input and output.

[0038]

[Table 1] In this case, focusing on the output transistor 26, when the input terminal 21 changes from L to H, the capacitor 59 and the comparator 85
_Causes a delay of t _d and the output transistor 26 is turned on.
Also, focusing on the output transistor 25, when the input terminal 21 changes from H to L, the capacitor 60 and the comparator 86 set t.
Since the output transistor 25 is turned on due to a delay of _d , the output transistors 25 and 26 can be simultaneously turned off. As described above, according to this configuration, it is possible to eliminate current penetration inside the integrated circuit chip, and to provide a good semiconductor integrated circuit.

FIG. 9 shows input / output waveforms when the circuit of FIG. 8 is employed. The output waveforms of the output terminals 34 and 35 with respect to the input waveforms to the signal input terminals 20 and 21 with the horizontal axis representing time. Is shown. During the time t _{d in} the figure, the current supply and the output transistor can be simultaneously turned off.
FIG. 10 is a cross-sectional view schematically showing an embodiment in which a capacitor for generating the above-described delay is formed, focusing on the transistor 53, the capacitor 59 , and the output transistor 26 of FIG. I have. Reference numeral 1 denotes a P-type substrate, and bases 5c, 5e, which are P-type diffusion regions, are added to the N-type epitaxial layer on the N-type buried layer via the separation layer 2.
5e and N ⁺ emitters 6c, 6e, 6e and N ⁺
Output transistor 26 having collectors 7c, 7e, 7e by diffusion, transistor 59 'and transistor 5
3 are formed.

The emitter 6e of the transistor 59 '
Forming a capacitor with the PN junction capacitance of the constant current source I and ₃₀ is supplied, the collector 7e, and ground wire the base 5e, in the base 5e and emitter 6e reverse biased junction in. Also, the emitter 6e of the transistor 59 '
Region 1 in which the thickness of the oxide film clearly indicated by oblique lines is reduced.
1 'is provided thereon, and a wiring member connected to the ground is provided thereon. In addition to the PN junction capacitor, a MOS type capacitor is formed. Thus, the same capacitance value can be realized with a small transistor area. In particular, it is not necessary to form both the PN junction capacitance and the MOS capacitance as in this case,
Only the N junction capacitance may be used. This capacitor corresponds to the capacitor 59 in FIG. 8 and generates a delay of t _d together with the constant current source I ₃₀ . This capacitance value is less than 100 pF
The current value of the constant current source I ₃₀ is also 10 for a delay of about μsec.
Very small, less than μA.

Now, consider the case where the constant current source I ₃₀ is not connected to the transistor 53. At this time, the transistor 59 'in the case of forming the capacitor by is a negative potential to the output terminal 35 the current is drawn from the Ru and the output terminal 35 is applied, the transistor 59' and a collector is grounded in, from the ground to draw current, without adversely any effect on the capacitor, always be capable of supplying a stable delay time t _d.

In fact, in the circuit shown in FIG. 8, the constant current I ₃₀ supplied to the capacitor is also supplied to the transistor 53. Therefore, there is a possibility that a parasitic transistor using the epitaxial layer region 47 of the transistor 53 as a collector may occur. Therefore, even if the capacitor is formed by the transistor 59 'as described above, it may be affected by other elements. In order to suppress the influence, a detection circuit for detecting a parasitic current may be formed, and a current corresponding to the parasitic current detected by the circuit may be supplied to a collector serving as an output of the transistor 53. Actually, in the present embodiment, a current mirror circuit is configured as shown in FIG.

This current mirror circuit is composed of PNP transistors 63 and 64 formed in the present integrated circuit chip as shown in FIG. 11, and the collector and base of the input-side transistor 63 are shown in FIG. However, the wiring is provided in the epitaxial layer region formed near the transistor 53, and the collector of the output-side transistor 64 is connected to the emitter 6 f of the transistor 53.

The above-described epitaxial layer region near the transistor 53 is a region having a collector formed by N ⁺ diffusion and having the same collector facing length with respect to the output transistor 26. Here, the vicinity range is a range in which the parasitic collector currents are almost equal when the collector facing lengths are equal. Specifically, in FIG. It is considered that the range exists near 53.

FIG. 11 is an equivalent circuit diagram showing a state in which the influence of the parasitic transistor is prevented. When a negative potential is applied to the output terminal 35 and a current is drawn from the output terminal 35, the epitaxial region 4 of the output transistor 26 shown in FIG.
And a parasitic NPN transistor 76 using the collector region 47 of the transistor 53 as a collector, a parasitic NPN transistor 75 using the collector region 48 of the transistor 59 'as a collector, and an output transistor of the current mirror circuit. A parasitic NPN transistor 77 having the epitaxial layer region as a collector is formed. At this time, as described above, the parasitic transistor 7
5 draws a current from the ground, so that there is no problem in circuit. However, the parasitic transistor 76 has a constant current I ₃₀
To draw current from the effect on the output of the transistor 53, and in this circuit, since the constant current I ₃₀ is also supplied to the capacitor 59 is considered the influence of the time constant, for example.

Therefore, when the current mirror circuit is configured as described above, the parasitic transistor 76 and the parasitic transistor 77 have the same collector facing length with respect to the output transistor 26, so that the parasitic collector current I ₇₆
And I ₇₇ are equal. That is, the extracted parasitic current I
_{Since the} current I ₇₇ supplied via the current mirror circuit is equal to the current I ₇₆ , the current supplied to the transistor 53 does not change even if the parasitic transistor operates. As a result, the completely eliminate the influence of the parasitic current I ₇₆ by the negative voltage applied to the output.

As can be seen from the above description, this current mirror circuit exerts its effect even in a circuit in which no capacitor is formed. That is, in the case of FIG. 3 as well, the current mirror circuit can be added to the control transistor 61 to eliminate the influence of direct detection of the parasitic current. In this case, the output side of the control transistor 61 is connected to the collector. It is an example of time. By supplying a current corresponding to the parasitic current to the output side of the collectors and emitters of the plurality of control transistors, the parasitic effect can be canceled.

In summary, as shown in FIG. 4, it is necessary to reduce the collector facing length and supply a constant current that does not malfunction without exceeding the parasitic current generated even in this case.
By adding a current mirror circuit as shown in (1), there is no need to consider the effects of parasitic currents.
Current consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating an example of a forward / reverse rotation motor driver circuit.

FIG. 2 is a cross-sectional configuration diagram of a bipolar semiconductor integrated circuit showing features of the present invention.

FIG. 3 is an equivalent circuit diagram focusing on the parasitic transistor of FIG. 2;

FIG. 4 is a graph showing a relationship between a collector facing length ratio and a parasitic current in a planar pattern of a transistor relating to a parasitic.

FIG. 5 is a plan pattern diagram of an output stage circuit and a partial control circuit in FIG. 1, showing features of the present invention.

FIG. 6 is a cross-sectional configuration view taken along the line A-A ′ of FIG. 5;

FIG. 7 is a plane pattern diagram showing another embodiment of FIG. 5;

FIG. 8 is a detailed circuit block diagram of FIG. 1;

9 is a timing chart showing an input / output relationship in the circuit of FIG. 8;

FIG. 10 is a sectional view showing an embodiment of the present invention.

FIG. 11 is an equivalent circuit diagram of FIG.

FIG. 12 is a graph showing changes over time of a motor terminal voltage and a motor current when the motor is driven.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type board | substrate 2 P-type isolation layer 4,41-47 N-type epitaxial layer 5a-5c P-type diffusion layer 6a-6c N-type diffusion layer 7a-7c N-type diffusion layer 15,71-77 Parasitic transistor 25,27 Current Supply transistor 46, 47 Driving transistor for current supply transistor 26, 28 Output stage transistor 29-31 Output clamp diode 61 Transistor in control circuit 100, 101 N-type epitaxial layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H02P 7/06 H01L 27/06 101P H03F 3/183 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21 / 8222 H01L 21/76 H01L 27/06 H01L 27/082 H02P 7/06 H03F 3/183

Claims (6)

(57) [Claims] An output circuit section formed on one integrated circuit chip and having an output transistor, and a control circuit section having a control transistor for controlling the output circuit section, and a PN is provided between each element. In the bipolar semiconductor integrated circuit separated by junction, of the control transistors, all transistors formed in a rectangular shape on the integrated circuit chip are arranged with their short sides facing the output stage transistor side. Do
And the control section around the output stage transistor.
At least the side on the transistor side and the two sides adjacent to it
Surround the three sides with an epitaxial layer,
Between the output transistor and the control transistor.
Function as the collector of the formed parasitic transistor
Bipolar semiconductor integrated circuit, characterized in that that. 2. The control circuit section includes an NPN transistor.
The NPN transistor includes
When a constant current is supplied to the
Form a capacitor using the combined capacitance and
Connected to the ground potential
The control circuit unit uses the charging time of the capacitor.
And delaying and controlling the output circuit unit using
The bipolar semiconductor integrated circuit according to claim 1 . 3. An integrated circuit device, comprising :
Output circuit section having power stage transistor and output circuit
A control circuit section having a control transistor for controlling the section;
Bipolar device with PN junction separated between devices
In the semiconductor integrated circuit, among the control transistors, on the integrated circuit chip
All the transistors that are formed on a rectangle
Do not arrange the short side to the output stage transistor side.
And the control circuit section includes an NPN transistor
The NPN transistor is
A constant current is supplied to the PN junction capacitor of the base and the emitter.
To form a capacitor that utilizes
Is connected to ground potential and
The control circuit unit utilizes the charging time of the capacitor.
A bipolar semiconductor integrated circuit, wherein the output circuit section is controlled with a delay . 4. The output circuit section includes a current supply transistor for supplying a current to the output stage transistor,
The emitter of the current supply transistor and the output stage transformer
Are those in which the collector of the register is the current in the output stage transistor from a connected said current supplying transistor is supplied, by using the charging time of the capacitor formed in the control circuit unit, said output stage Transistor
4. The bipolar semiconductor integrated circuit according to claim 2, wherein the current supply transistors are not turned on at the same time. 5. A bipolar semiconductor integrated circuit formed on one integrated circuit chip, having an output stage transistor and a control transistor for controlling the output stage transistor, and separated by a PN junction. And a parasitic current detecting means for detecting a parasitic current generated between the transistor and the control transistor. The parasitic current detecting means supplies a current corresponding to the parasitic current to an output side of a collector and an emitter of the control transistor. A bipolar semiconductor integrated circuit, wherein the parasitic current is offset. 6. The control circuit according to claim 6, wherein said parasitic current detecting means is formed in the vicinity of said control transistor and from which an electric current corresponding to said parasitic current is extracted and a current equivalent to the current flowing through said epitaxial layer is collected by said collector of said control transistor. 6. A bipolar semiconductor integrated circuit according to claim 5 , further comprising a current mirror circuit for supplying an output side of said emitter.