JP2004120917A - Inverter device and motor drive unit using the same - Google Patents

Inverter device and motor drive unit using the same Download PDF

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Publication number
JP2004120917A
JP2004120917A JP2002282141A JP2002282141A JP2004120917A JP 2004120917 A JP2004120917 A JP 2004120917A JP 2002282141 A JP2002282141 A JP 2002282141A JP 2002282141 A JP2002282141 A JP 2002282141A JP 2004120917 A JP2004120917 A JP 2004120917A
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circuit
inverter device
semiconductor chip
drive circuit
upper arm
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JP4000976B2 (en
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Naoki Sakurai
桜井　直樹
▲高▼橋　可昌
Yoshimasa Takahashi
Mutsuhiro Mori
森　　睦宏
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Power Conversion In General (AREA)
  • Inverter Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a an inverter device equipped with a highly reliable boosting level shift circuit without using a photocoupler. <P>SOLUTION: The inverter device comprises a first semiconductor chip including an upper arm drive unit and a current detection circuit; a second semiconductor chip including a lower arm drive unit and a drive signal processing circuit; and a third semiconductor chip including a high-withstand voltage MOSFET for the level shift circuit. The first and second semiconductor chips are formed on an SOI board, the chips are arranged on an insulating board and resin-molded, and a semiconductor switching element is arranged as an individual component. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、主端子間に直列接続した複数の電力スイッチング素子からなるアームを備えたインバータ装置に関わり、特に低圧側回路から高圧側回路に制御信号を伝達する昇圧レベルシフト回路を備えたインバータ装置や、高圧側回路から低圧側回路に制御信号を伝達する降圧レベルシフト回路を備えたインバータ装置に関する。
【０００２】
【従来の技術】
図１６に従来技術のインバータ装置の１アーム分のブロック図を示す。図１６で、１１１は第１電力スイッチング素子、１１２は第２電力スイッチング素子、１１３は上アーム駆動回路、１１４は下アーム駆動回路、１２０は主電源高圧端子、１２１は出力端子、１２２は主電源接地端子、１２３は第１電力スイッチング素子のゲート端子、１２４は第２電力スイッチング素子のゲート端子、１２５は上アーム駆動用電源、１２６は下アーム駆動用電源、１２７は駆動信号処理回路、１３０はホトカプラである。第１電力スイッチング素子１１１のエミッタは出力端子１２１に接続しているため、第１電力スイッチング素子１１１は主電源接地端子１２２に対して電位的に浮動の状態で駆動される。上アーム駆動回路
１１３は、浮動の電位に接続されており第１電力スイッチング素子１１１がオン状態では主電源と同じ高電圧が加わるため、接地電位に対して絶縁されている。絶縁した上アーム駆動回路１１３に、駆動信号処理回路１２７から信号を伝えるためにホトカプラ１３０を使用している（例えば、特許文献１参照）。
【０００３】
別の従来技術では図１７に示ように、下アームから上アームへの信号の伝達にホトカプラの代わり高耐圧ｎ型ＭＯＳＦＥＴと電圧検知回路からなる昇圧レベルシフト回路を使用し、昇圧レベルシフト回路と上下駆動回路と信号処理回路とを１チップに集積している（例えば、特許文献１と、非特許文献１を参照）。
【０００４】
図１８に前記従来技術や別の従来技術の集積回路の断面構造を示す。図１８に示すように、ポリシリコン２００を支持体として酸化膜２０１ａ，２０１ｂ，
２０１ｃで囲んだシリコン単結晶島内に、ｎ＋　層２０２ａ，２０２ｂ，２０２ｃと、ｎ−　層２０３ａ，２０３ｂ，２０３ｃとを設ける。このように単結晶島を酸化膜で囲んだ基板を誘電体分離基板という。ｎ−　層２０３ａ内にはｐ層２０４を設け、ｐ層２０４内にはｎ＋　層２０５を設けてある。ｎ＋　層２０５，ｐ層２０４，ｎ−　層２０３の表面にはゲート酸化膜２０６ａを設け、ゲート酸化膜２０６ａにはゲート電極２０７ａを設けてある。ゲート電極２０７ａは絶縁膜２０８で囲まれていて、ソース電極２１０ａと絶縁されている。
ｎ＋　層２０２ａ，ｎ−　層
２０３ａ，ｐ層２０４，ｎ＋　層２０５ａ，ゲート酸化膜２０６ａ，ゲート電極
２０７ａで高耐圧ｎ型ＭＯＳＦＥＴ３１を形成している。
【０００５】
図１８の符号１３２は上アーム駆動回路の低耐圧ｎ型ＭＯＳＦＥＴを示す。
ｎ−　層２０３ｂ内にはｐ層２１３を設け、ｐ層２１３内には２個のｎ＋　層２１２を設けてある。ｎ＋　層２１２，ｐ層２１３，表面にゲート酸化膜２０６ｂを設け、ゲート酸化膜２０６ｂ表面にはゲート電極２０７ｂを設けてある。高耐圧ｎ型ＭＯＳＦＥＴ１３１と低耐圧ｎ型ＭＯＳＦＥＴ１３２とは酸化膜２０８ｂを介して電極２１０ｂで接続している。符号１３３は抵抗を示し、ｎ−　層２０３ｃ内にｐ層２１４を設けてある。ｐ層２１４は酸化膜２０８ｃの上に配置した電極２１０ｃを介して低耐圧ｎ型ＭＯＳＦＥＴ１３２に接続している。
【０００６】
【特許文献１】
特開平５−３１６７５５号公報
【非特許文献１】
日立高耐圧モノリシックＩＣデータブック　モーター駆動用ＩＣシリーズ，株式会社日立製作所，２００１年３月，ｐ．１１３〜１１６
【０００７】
【発明が解決しようとする課題】
前記ホトカプラを使用した従来技術ではホトカプラの発光素子に化合物半導体を使用しているため高価である。また前記高耐圧ｎ型ＭＯＳＦＥＴを使い検出回路を使用して駆動信号を下アームに伝える別の従来技術では、高耐圧ｎ型ＭＯＳＦＥＴと駆動回路と信号処理回路とを誘電体分離基板に１チップに集積するために、チップの耐圧を高くすると、例えば図１８の高電位のｎ＋　層２０２ａとソース電極２１０ａとを絶縁する酸化膜２０８ａを厚くする必要があるが、厚くすると酸化プロセスの時間が長くなり、生産時間が長くなるだけでなく、集積回路の製造途中で酸化膜によるウエハのそりが発生し、ウエハ割れが発生し取得率が落ちる問題がある。
【０００８】
本発明の目的は、上記課題を解決した信頼性が高い、低圧側回路から高圧側回路に制御信号を伝達する昇圧レベルシフト回路を有するインバータ装置および、高圧側回路から低圧側回路に制御信号を伝達する降圧レベルシフト回路を有するインバータ装置を提供することである。
【０００９】
【課題を解決するための手段】
本発明のインバータ装置は、上アーム駆動回路と電流検出回路とを１個のＩＣチップに、高耐圧ｎ型ＭＯＳＦＥＴを１チップに、下アーム駆動回路とを駆動信号処理回路を１個のＩＣチップにし、これらのチップを絶縁基板上に配置した。
【００１０】
また、本発明のインバータ装置は、上アーム駆動回路と電流検出回路とを１個のＩＣチップに、セット信号用高耐圧ｎ型ＭＯＳＦＥＴを１チップに、リセット信号用高耐圧ｎ型ＭＯＳＦＥＴを１チップに、下アーム駆動回路と駆動信号処理回路を１個のＩＣチップにし、これらのチップを絶縁基板上に配置した。
【００１１】
さらに本発明のインバータ装置は、上アーム駆動回路と電流検出回路と異常検出回路と１個のＩＣチップに、セット信号用高耐圧ｎ型ＭＯＳＦＥＴを１チップに、リセット信号用高耐圧ｎ型ＭＯＳＦＥＴを１チップに、セット信号用高耐圧ｐ型ＭＯＳＦＥＴを１チップに、リセット信号用高耐圧ｐ型ＭＯＳＦＥＴを１チップに、下アーム駆動回路と電流検出回路と駆動信号処理回路とを１個のＩＣチップにし、これらのチップを絶縁基板上に配置した。
【００１２】
【発明の実施の形態】
以下、本発明の実施例を図面を用いて詳しく説明する。以下の実施例では電力スイッチング素子としてＩＧＢＴを例に説明するが、パワーＭＯＳＦＥＴでも同様である。以下の説明で、高耐圧とは１００Ｖ以上の耐圧定格値のことであり、低耐圧とは２０Ｖ以下の耐圧定格値のことである。また、本発明の実施例では、インバータ装置の主端子に１００Ｖ以上の電圧が印加され、少なくとも１０Ａ以上の最大主電流が流れている。
【００１３】
（実施例１）
図１は本実施例のインバータ装置の１アーム分のブロック図である。図１に示すように、主電源高圧端子１０に第１電力スイッチング素子１のコレクタが接続し、第１電力スイッチング素子１のエミッタと第２電力スイッチング素子２のコレクタが出力端子１１に接続している。主電源接地端子１２に第２電力スイッチング素子２のエミッタが接続し、この主電源接地端子１２を接地する。第１電力スイッチング素子１のゲート端子１３に上アーム駆動回路２０が接続し、第２電力スイッチング素子２のゲート端子１４に下アーム駆動回路２１が接続している。
【００１４】
第１電力スイッチング素子１のエミッタは出力端子１１に接続しているため、第１電力スイッチング素子１を主電源接地端子１２に対して電位が浮動の状態で駆動する。このため、上アーム駆動回路２０はトランス等で絶縁した上アーム側電源高圧側端子１５から電力を供給する。下アーム駆動回路２１には主電源接地端子１２に接続した電源７から電力を供給する。
【００１５】
駆動信号処理回路８から上下各アームへ駆動信号を送る。下アームは駆動信号処理回路８の信号を下アーム駆動回路２１で受け、第２電力スイッチング素子２を導通状態にする。高耐圧ｎ型ＭＯＳＦＥＴ３１のソースは主電源接地端子１２に接続し、高耐圧ｎ型ＭＯＳＦＥＴ３１のドレインは電流検出回路３０の一方の端子に接続している。電流検出回路３０の他方の端子は上アーム側電源高圧側端子１５に接続し、高耐圧ｎ型ＭＯＳＦＥＴ３１のゲートが駆動信号処理回路８に接続している。駆動信号処理回路８から高耐圧ｎ型ＭＯＳＦＥＴ３１のゲートにオン信号が加わると、高耐圧ｎ型ＭＯＳＦＥＴ３１が導通して電流が流れ、この電流を電流検出回路３０が電圧に変換して上アーム駆動回路２０に伝え、上アーム駆動回路２０が第１電力スイッチング素子１を導通する。
【００１６】
図２に本実施例の実装模式図を示す。本実施例では上アーム駆動回路２０と、電流検出回路３０とを第１のＩＣチップ８１とし、下アーム駆動回路２１と駆動信号処理回路８とを第２のＩＣチップ８２とし、高耐圧ｎ型ＭＯＳＦＥＴ３１を個別部品の第３のチップとし、ＩＣチップ８１と、ＩＣチップ８２と、高耐圧ｎ型ＭＯＳＦＥＴ３１の３個のチップを配置した。
【００１７】
ＩＣチップ８２は、ワイヤボンデイング５０で第２電力スイッチング素子２のゲート端子１４に接続し、ワイヤボンデイング５１で下アーム側電源高圧側端子１７に接続し、さらに、ワイヤボンデイング５２で下アーム側電源接地側端子
１８に接続している。
【００１８】
高耐圧ｎ型ＭＯＳＦＥＴ３１のソースは、ワイヤボンデイング５７でＩＣチップ８２に接続し、ゲートはワイヤボンデイング５８でＩＣチップ８２に接続し、ドレイン（裏面側）は配線７０に接続している。配線７０とＩＣチップ８１とはワイヤボンデイング５６で接続している。
【００１９】
ＩＣチップ８１は、ワイヤボンデイング５３で第１電力スイッチング素子１のゲート端子１３に接続し、ワイヤボンデイング５４で上アーム側電源高圧側端子１５に接続し、ワイヤボンデイング５５で上アーム側電源接地側端子１６に接続している。
【００２０】
本実施例では、下アーム駆動回路２１と駆動信号処理回路８とを集積したＩＣチップ８２と、上アーム駆動回路２０と電流検出回路３０とを集積したＩＣチップ８１と、高耐圧ｎ型ＭＯＳＦＥＴ３１の３つのチップを絶縁基板８０の一方の面に配置し、絶縁基板８０上で各チップを適切な距離（０．５ｍｍ以上）を保持して配置しているので上アームと下アームとの絶縁が容易に確保できる。さらに、本実施例では図２に示すように、ＩＣチップ８１から引き出す接続端子とＩＣチップ８２から引き出す接続端子とを、略長方形の絶縁基板の対向する２辺の上に配置してあるので上下アームの絶縁が確実にできる。また、本実施例では、ＩＣチップ８１と、ＩＣチップ８２と、高耐圧ｎ型ＭＯＳＦＥＴ３１とは同一パッケージに樹脂モールドされているので外界からの水分から十分に保護されている。なお、モールドする樹脂は絶縁基板８０の表裏全面を被覆しても良いし、絶縁基板上のＩＣチップとワイヤボンデイングのみを被覆し、放熱を促進するために絶縁基板の裏面はモールドせずに露出させておいても良い。
【００２１】
本実施例ではホトカプラを用いることなく、シリコン半導体素子と絶縁基板とによって構成されているので、ホトカプラを使用する場合に比べて安価に製造できる。さらに、本実施例では電力スイッチング素子の高耐圧ｎ型ＭＯＳＦＥＴは個別の高耐圧部品を用いるので、誘電体分離基板を用いる場合に必要な、インバータ装置の耐圧を高めるための酸化膜の膜厚を増やす特殊な製造プロセスなどなしで容易に耐圧を高くできる。
【００２２】
（実施例２）
図３に本実施例の、上アーム駆動回路２０，下アーム駆動回路２１の回路構成を示す。本実施例では上アーム駆動回路２０がｐ型ＭＯＳＦＥＴ２２とｎ型
ＭＯＳＦＥＴ２３とからなるＣＭＯＳＦＥＴ構成、下アーム駆動回路２１がｐ型ＭＯＳＦＥＴ２４とｎ型ＭＯＳＦＥＴ２５とからなるＣＭＯＳＦＥＴ構成となっている他は実施例１と同様である。
【００２３】
本実施例では上下のアーム駆動回路がＣＭＯＳＦＥＴ構成なので、第１電力スイッチング素子１及び第２電力スイッチング素子２がターンオン、あるいはターンオフに遷移するときにだけ電流が上アーム駆動回路２０，下アーム駆動回路
２１に流れるので、駆動電力の発生を抑制できる。
【００２４】
（実施例３）
図４に本実施例を示す。本実施例では、電流検出回路３０が抵抗３２を備え、これ以外は実施例２と同様である。駆動信号処理回路８から高耐圧ｎ型ＭＯＳＦＥＴ３１のゲートにオン信号が伝わるとドレインとソースの間に電流が流れ、ドレインに接続した抵抗３２で電圧降下が発生する。この電圧降下によってｐ型ＭＯＳＦＥＴ２２が導通し、ｎ型ＭＯＳＦＥＴ２３が非導通になり、上アーム駆動電源６の高圧側電位が第１電力スイッチング素子１のゲートに印加されて、第１電力スイッチング素子１が導通する。
【００２５】
（実施例４）
図５に本実施例を示す。本実施例では、電流検出回路３０が、抵抗３２と抵抗３２の両端に接続したツェナーダイオード３３を備えたことが実施例３と異なる。高耐圧ｎ型ＭＯＳＦＥＴ３１が流す電流は、製造ばらつきでしきい値電圧が下がっていたり、あるいは周囲温度が低い場合に増加し、抵抗３２両端に発生する電圧が大きくなり、ｐ型ＭＯＳＦＥＴ２２，ｎ型ＭＯＳＦＥＴ２３を破壊するおそれがある。本実施例のツェナーダイオード３３は抵抗両端に発生する過大な電圧を抑制する。
【００２６】
図６は本実施例の高耐圧ｎ型ＭＯＳＦＥＴ３１の斜視図である。図６に示すように、ｎ＋　層９０の上にｎ−　層９１を形成し、このｎ−　層９１内にｐ層９２ａ，９２ｂを形成してある。ｐ層９２ａ内にｎ＋　層９３ａを、ｐ層９２ｂ内にｎ＋　層９３ｂを形成し、ｎ＋　層９３ａ，ｐ層９２ａ，ｎ−　層９１，ｐ層９２ｂ，ｎ＋　層９３ｂに渡って表面にゲート酸化膜９４を設け、さらにゲート酸化膜９４の上にゲート電極９５を設けてある。ｐ層９２ａ，９２ｂと、ｎ＋　層９３ａ，９３ｂと、ゲート酸化膜９４，ゲート電極９５とでＭＯＳＦＥＴを構成する。
【００２７】
ｐ層９２ａ，９２ｂと、ｎ＋　層９３ａ，９３ｂとはソース電極１００とオーミック接続している。また、ｎ−　層９１内にはｐ層９７ａ，９７ｂ，９７ｃを配置し、ｐ層９２ｂ，ｎ−　層９１，ｐ層９７ａに渡って酸化膜９９ａを、ｐ層９７ａ，ｎ−　層９１，ｐ層９７ｂに渡って酸化膜９９ｂを設けてある。さらに、ｐ層
９７ｂ，ｎ−　層９１，ｐ層９７ｃに渡って酸化膜９９ｃを、ｐ層９７ｃ，ｎ−　層９１，ｎ＋　層９８に渡って酸化膜９９ｄを設けてある。
【００２８】
ソース電極１００は酸化膜９９ａ上をｎ＋　層９８の延在する方向に沿って伸び、ｐ層９７ａにオーミック接続した電極１０１ａが酸化膜９９ｂ上をｎ＋　層９８の延在する方向に沿って伸びている。さらに、ｐ層９７ｂにオーミック接続した電極１０１ｂが酸化膜９９ｃ上をｎ＋　層９８の延在する方向に沿って伸び、ｐ層９７ｃにオーミック接続した電極１０１ｃが酸化膜９９ｄ上をｎ＋　層９８の延在する方向に沿って伸びている。また、ｎ＋　層９８にオーミック接続した電極１０２もｐ層９２ｂの延在する方向に沿って伸びている。ドレインの電極１０２がｎ＋　層９０にオーミック接続している。
【００２９】
高耐圧ｎ型ＭＯＳＦＥＴ３１は以下の様に動作する。ソース電極１００を接地し、ドレインの電極１０２に高電圧を加えた状態でゲート電極９５に正の電圧を加えると、ｐ層９２ａ，９２ｂが反転してチャネルができ、電子がチャネルを通ってｎ−　層９１に流れ、さらに電子がｎ＋　層９０を通りドレインの電極１０２に達する。ソース電極１００，電極１０１ａ，電極１０１ｂ，電極１０１ｃをｎ＋　層９８の方向に伸ばすことで空乏層を伸ばし素子の耐圧を上げている。端部は切断面が表面に現れているため、再結合準位が多いので、空乏層が端部に達すると、もれ電流が増加する。ｎ＋　層９８及び電極１０２は酸化膜９９ａ，９９ｂ，
９９ｃ，９９ｄ中の電荷や図に示していない保護膜中の電荷によりｎ−　層９１がｐ型に反転し、空乏層が端部に達することを防止している。ｎ−　層９１の抵抗率と、厚さ、及びｐ層９７ａ，９７ｂ，９７ｃの数とを増やすことで製造方法を変えることなく容易に素子の耐圧を高くできる。
【００３０】
図７に図６に示す高耐圧ｎ型ＭＯＳＦＥＴのゲート電極の幅Ｗ（図６奥行き方向で、以後単にゲート幅Ｗと略す。）と抵抗３２両端の電圧との関係を示す。図７では抵抗３２が１ｋΩの場合を示し、ゲート幅Ｗが１０μｍ以上では横軸は対数目盛りである。ゲート幅Ｗがゼロでは電流が流れず、抵抗３２両端に発生する電圧は０Ｖであるが、ゲート幅Ｗを増すと電流が増え、抵抗３２両端の電圧が増加する。ツェナーダイオード３３を抵抗３２に接続した場合は、図７に示すように、ゲート幅Ｗを増やして電流を増加させてもツェナー電圧で抵抗３２の両端に発生する電圧が抑制される。しかし、ゲート幅Ｗが１００００μｍ以上になると、抵抗３２の両端の電圧が再び増加する。これは、ＩＣに集積できるツェナーダイオードでは抵抗成分が大きく、電流が多くなると電圧降下が大きくなるためである。抵抗３２の値を小さくすると、抵抗３２の両端に発生する電圧は抑制されるが、抵抗３２に流れる電流が多くなり損失が多くなるので望ましくない。ｐ型ＭＯＳＦＥＴ２２，ｎ型ＭＯＳＦＥＴ２３が破壊しないようなツェナー電圧以下で使用するためにはゲート幅Ｗは１００００μｍ以下が望ましい。また、ツェナー電圧以下の領域では製造ばらつきや温度変化による電流変動により抵抗３２両端の電圧が変動するので、ゲート幅Ｗは１０μｍ以上が望ましく、結局、高耐圧ｎ型ＭＯＳＦＥＴ３１のゲート幅Ｗは１０μｍ〜１００００μｍが望ましい。
【００３１】
（実施例５）
図８に本実施例を示す。本実施例は抵抗３２両端にコンデンサ３４が接続している他は実施例４と同様である。上側アース電位（出力端子１１と上アーム側電源接地側端子１６の電位）は第１電力スイッチング素子１が導通しているときは主電源電圧に、第２電力スイッチング素子２が導通しているときは接地電位になり、第１電力スイッチング素子１と第２電力スイッチング素子２とが何れも非導通であるときはほぼ（主電源電圧）／２になる。第１電力スイッチング素子１が導通する過程で、上側アース電位は、（主電源電圧）／２から主電源電圧に変動し、第２電力スイッチング素子２が導通する過程で、電圧は（主電源電圧）／２から接地電位に変動する。この電圧変動ｄＶ／ｄｔと高耐圧ｎ型ＭＯＳＦＥＴ３１のソース，ドレイン間容量Ｃｓｄ（図示せず。）により過渡的にＣｓｄ×ｄＶ／ｄｔの大きさで電流が流れるので、本実施例では、コンデンサ３４を抵抗３２両端に配置してソース，ドレイン間容量Ｃｄｓに直列に接続して見かけのソース，ドレイン間容量を小さくし、この電流を抑制した。
【００３２】
図９に本実施例の実装図を示す。配線７１ａ，７１ｂの上にコンデンサ３４を接続し、ＩＣチップ８１とはワイヤボンデイング５９，６０で接続している。半導体基板に形成するコンデンサの容量は、チップ面積の制約のために１０ｐＦ程度が上限である。このため、本実施例ではコンデンサ３４を抵抗３２，ツェナーダイオード３３とは別のチップとし、個別部品の第４チップとしたが、もちろん、ツェナーダイオード３３と同じチップにコンデンサ３４を作製できればそのようにしても良い。本実施例では、１枚の長方形の絶縁基板の上に前記４個のチップを搭載し、絶縁基板とこれらのチップとを実施例１と同様にして樹脂モールドした。
【００３３】
（実施例６）
図１０に本実施例を示す。本実施例では２個の高耐圧ｎ型ＭＯＳＦＥＴ３１，３５を備え、各々のドレインに抵抗３２，３６とツェナーダイオード３３，３７とが接続し、抵抗３２の一方の端子はＲＳフリップフロップ３８のセット側Ｓに接続している。抵抗３６の他方の端子は、ＲＳフリップフロップ３８のリセット側Ｒに接続し、ＲＳフリップフロップ３８の出力がＮＯＴ回路の入力に接続している。ＮＯＴ回路の出力はｐ型ＭＯＳＦＥＴ２２とｎ型ＭＯＳＦＥＴ２３のゲート端子に接続している。
【００３４】
本実施例では、ｐ型ＭＯＳＦＥＴ２２と、ｎ型ＭＯＳＦＥＴ２３と、ＮＯＴ回路１９と、ＲＳフリップフロップ３８と、抵抗３２，３６と、ツェナーダイオード３３，３７とを第１のＩＣチップ８１に集積し、ｐ型ＭＯＳＦＥＴ２４と、ｎ型ＭＯＳＦＥＴ２５と、駆動信号処理回路とを第２のＩＣチップ８２として集積している。高耐圧ｎ型ＭＯＳＦＥＴ３１，３５はそれぞれ個別部品の第３チップ，第４チップとして独立している。
【００３５】
本実施例の動作を説明する。駆動信号処理回路８から短時間（１μｓ程度）のパルスを高耐圧ｎ型ＭＯＳＦＥＴ３１のゲート端子に加えると、パルスが入力されている時間だけ高耐圧ｎ型ＭＯＳＦＥＴ３１が導通して、抵抗３２の両端に電圧が発生し、ＲＳフリップフロップ３８のセット側Ｓに入力信号が加わり、ＲＳフリップフロップ３８の出力が上アーム側電源電圧になる。この出力はＮＯＴ回路１９で反転して、ｐ型ＭＯＳＦＥＴ２２，ｎ型ＭＯＳＦＥＴ２３のゲートに上アーム側電源の接地電位として加わりｐ型ＭＯＳＦＥＴ２２が導通，ｎ型
ＭＯＳＦＥＴ２３が非導通になり、第１電力スイッチング素子１が導通する。
【００３６】
第１電力スイッチング素子１を非導通にするときは、駆動信号処理回路８から短時間，高耐圧ｎ型ＭＯＳＦＥＴ３５のゲート端子にパルスを加えると、パルスが入力されている時間だけ高耐圧ｎ型ＭＯＳＦＥＴ３５が導通して、抵抗３６両端に電圧が発生し、ＲＳフリップフロップ３８のリセット側Ｒに入力信号が加わり、ＲＳフリップフロップ３８の出力が上アーム側電源の接地電位になる。この出力がＮＯＴ回路１９で反転し、ｐ型ＭＯＳＦＥＴ２２とｎ型ＭＯＳＦＥＴ２３のゲートが上アーム側電源電位になり、ｐ型ＭＯＳＦＥＴ２２が非導通，ｎ型
ＭＯＳＦＥＴ２３が導通になって第１電力スイッチング素子１が非導通になる。本実施例では、高耐圧ｎ型ＭＯＳＦＥＴ３１，３５に電源電圧が加わった状態で短時間電流が流れるだけなので、高耐圧ｎ型ＭＯＳＦＥＴ３１，３５での損失を大幅に低減できる。
【００３７】
図１１は本実施例の実装模式図である。長方形の絶縁基板８０の上に、ｐ型
ＭＯＳＦＥＴ２４とｎ型ＭＯＳＦＥＴ２５と駆動信号処理回路８とを集積した
ＩＣチップ８２と、ｐ型ＭＯＳＦＥＴ２２とｎ型ＭＯＳＦＥＴ２３とＲＳフリップフロップ３８と抵抗３２，３６とツェナーダイオード３３，３７とを集積したＩＣチップ８２と、高耐圧ｎ型ＭＯＳＦＥＴ３１，３５の４個のチップを配置している。
【００３８】
ＩＣチップ８２は、ワイヤボンデイング５０により第２電力スイッチング素子２のゲート端子１４に接続し、ワイヤボンデイング５１で下アーム側電源高圧側端子１７に接続し、さらに、ワイヤボンデイング５２により下アーム側電源接地側端子１８に接続している。
【００３９】
高耐圧ｎ型ＭＯＳＦＥＴ３１のソースはワイヤボンデイング５７でＩＣチップ８２に接続し、ゲートはワイヤボンデイング５８でＩＣチップ８２に接続し、ドレイン側（裏面側）は配線７０に接続している。配線７０とＩＣチップ８１はワイヤボンデイング５６で接続している。
【００４０】
高耐圧ｎ型ＭＯＳＦＥＴ３５のソースはワイヤボンデイング６２でＩＣチップ８２に接続し、ゲートはワイヤボンデイング６３でＩＣチップ８２に接続し、ドレイン側（裏面側）は配線７２に接続している。配線７２とＩＣチップ８１とはワイヤボンデイング６１で接続している。
【００４１】
ＩＣチップ８１は、ワイヤボンデイング５３で第１電力スイッチング素子１のゲート端子１３に接続し、ワイヤボンデイング５４で上アーム側電源高圧側端子１５に接続し、さらに、ワイヤボンデイング５５で上アーム側電源接地側端子
１６に接続している。
【００４２】
（実施例７）
図１２に本実施例を示す。本実施例では上アーム側電源高圧側端子１５に高耐圧ｐ型ＭＯＳＦＥＴ４０，４１のソースが接続している。高耐圧ｐ型ＭＯＳＦＥＴ４０のドレイン端子は抵抗４２の一方の端子と、ツェナーダイオード４３のカソードと、ＲＳフリップフロップ４６のセット端子Ｓとに接続している。抵抗４２の他方の端子とツェナーダイオード４３のアノードは接地している。高耐圧ｐ型ＭＯＳＦＥＴ４１のドレイン端子は抵抗４４の一方の端子と、ツェナーダイオード４５のカソードと、ＲＳフリップフロップ４６のリセット端子Ｒとに接続している。抵抗
４４の他方の端子とツェナーダイオード４５のアノードとは接地している。高耐圧ｐ型ＭＯＳＦＥＴ４０，４１のゲートには異常信号検出回路３９の出力信号を入力する。ＲＳフリップフロップ４６の出力は駆動信号処理回路８に接続してある。
【００４３】
本実施例では、ｐ型ＭＯＳＦＥＴ２２とｎ型ＭＯＳＦＥＴ２３とＮＯＴ回路
２６とＲＳフリップフロップ３８と抵抗３２，３６とツェナーダイオード３３，３７と異常信号検出回路３９とを第１のＩＣチップ８１として集積し、ｐ型ＭＯＳＦＥＴ２４とｎ型ＭＯＳＦＥＴ２５とＲＳフリップフロップ４６と抵抗４２，４４とツェナーダイオード４３，４５と駆動信号処理回路とを第２のＩＣチップ８２として集積し、高耐圧ｎ型ＭＯＳＦＥＴ３３，３１を第３チップ、第５チップとし、高耐圧ｐ型ＭＯＳＦＥＴ４０，４１を第６チップ，第７チップとして独立したチップとしている。
【００４４】
本実施例は以下のように動作する。過電流，温度異常，上アーム側電源電圧低下，主電源過電圧などの異常を異常信号検出回路３９が検知すると、高耐圧ｐ型ＭＯＳＦＥＴ４０のゲートに短時間オン信号が入力し、降圧レベルシフト回路を構成する高耐圧ｐ型ＭＯＳＦＥＴ４０が導通して抵抗４２に電流が流れ、抵抗
４２両端に発生した電圧信号をＲＳフリップフロップ４６のセット側Ｓに入力し、ＲＳフリップフロップ４６出力信号が駆動信号処理回路８に伝わる。
【００４５】
異常状態が解除されると、異常信号検出回路３９から高耐圧ｐ型ＭＯＳＦＥＴ４１のゲートに短時間オン信号が入力され、高耐圧ｐ型ＭＯＳＦＥＴ４１が導通して抵抗４４に電流が流れる。このとき、抵抗４４両端に電圧が発生しＲＳフリップフロップ４６のリセット側Ｒに信号が入力され、ＲＳフリップフロップ４６出力が接地電位になる。これ以外の動作は実施例６と同様である。
【００４６】
図１３に本実施例の実装図を示す。絶縁基板８０上に、ｐ型ＭＯＳＦＥＴ２４とｎ型ＭＯＳＦＥＴ２５と抵抗４２，４４とツェナーダイオード４３，４５と
ＲＳフリップフロップ４６と駆動信号処理回路８とを集積したＩＣチップ８２と、ｐ型ＭＯＳＦＥＴ２２とｎ型ＭＯＳＦＥＴ２３とＲＳフリップフロップ３８と抵抗３２，３６とツェナーダイオード３３，３７と異常信号検出回路３９とを集積したＩＣチップ８２と、高耐圧ｎ型ＭＯＳＦＥＴ３１，３５と、高耐圧ｐ型
ＭＯＳＦＥＴ４０，４１との６個のチップを配置した。
【００４７】
ＩＣチップ８２は、ワイヤボンデイング５０で第２電力スイッチング素子２のゲート端子１４に接続し、ワイヤボンデイング５１で下アーム側電源高圧側端子１７に接続し、さらに、ワイヤボンデイング５２で下アーム側電源接地側端子
１８に接続している。
【００４８】
高耐圧ｎ型ＭＯＳＦＥＴ３１のソースはワイヤボンデイング５７でＩＣチップ８２に接続し、ゲートはワイヤボンデイング５８でＩＣチップ８２に接続し、ドレイン側（裏面側）は配線７０に接続している。配線７０とＩＣチップ８１とはワイヤボンデイング５６で接続している。
【００４９】
高耐圧ｎ型ＭＯＳＦＥＴ３５のソースはワイヤボンデイング６２でＩＣチップ８２に接続し、高耐圧ｎゲートはワイヤボンデイング６３によりＩＣチップ８２に接続し、ドレイン側（裏面側）は配線７１に接続している。
【００５０】
高耐圧ｐ型ＭＯＳＦＥＴ４０のソースはワイヤボンデイング６４ａでＩＣチップ８１に接続し、ゲートはワイヤボンデイング６４ｂでＩＣチップ８１に接続し、ドレイン側（裏面側）は配線７３に接続している。配線７３とＩＣチップ８２はワイヤボンデイング６６で接続している。
【００５１】
高耐圧ｐ型ＭＯＳＦＥＴ４１のソースはワイヤボンデイング６５ａでＩＣチップ８１に接続し、ゲートはワイヤボンデイング６５ｂによりＩＣチップ８１に接続し、ドレイン側（裏面側）は配線７４に接続している。配線７４とＩＣチップ８２はワイヤボンデイング６７で接続している。
【００５２】
ＩＣチップ８１はワイヤボンデイング５３で第１電力スイッチング素子１のゲート端子１３に接続し、ワイヤボンデイング５４で上アーム側電源高圧側端子
１５に接続し、さらに、ワイヤボンデイング５５により上アーム側電源接地側端子１６に接続している。
【００５３】
図１４に、本実施例のＩＣチップ８１，８２の断面説明図を示す。シリコン単結晶１５０上に酸化膜１５１を形成し、ｎ−　層１５２，１５７，１６２，１６４は酸化膜１５１によって各々絶縁されている。ｎ−　層の間の酸化膜１５１はシリコン基板面に垂直に形成されている。このようにほぼ垂直の酸化膜で絶縁した基板をＳＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板という。ｎ−　層１５２中にｐ層１５３を設け、ｐ層１５３中にｎ＋　層１５４ａ，１５４ｂを設けてある。ｎ＋　層１５４ａ，ｐ層１５３，ｎ＋　層１５４ｂに渡ってゲート酸化膜１５５を配置し、さらにゲート酸化膜１５５上にゲート電極１５６を設けた。ｎ＋　層１５４ａ，１５４ｂと、ｐ層１５３と、ゲート酸化膜１５５と、ゲート電極１５６とでｎ型ＭＯＳＦＥＴ２３を形成する。
【００５４】
ｎ−　層１５７中にはｎ層１５８を設け、ｎ層１５８中にはｐ＋　層１５９ａ，
１５９ｂを設けてある。ｐ＋　層１５９ａ，ｎ層１５８，ｐ＋　層１５９ｂに渡ってゲート酸化膜１６０を設け、さらにゲート酸化膜１６０上にはゲート電極１６１を設けてある。ｐ＋　層１５９ａ，１５９ｂと、ｎ層１５８と、ゲート酸化膜１６０と、ゲート電極１６１とでｐ型ＭＯＳＦＥＴ２２を形成し、ｎ−　層１６２中にｐ層１６３を設けて抵抗３２を形成し、ｎ−　層１６４中にｐ＋　層１６５とｎ＋　層
１６６を設けてツェナーダイオード３３を形成している。
【００５５】
誘電体分離基板は絶縁のための酸化膜が例えば図１８に示すように傾斜しているために、シリコン単結晶島間の距離を短くできない。これに対してＳＯＩ基板は絶縁のための酸化膜が垂直なので、シリコン単結晶間距離を小さくでき、素子面積も小さくできるので安価に製造できる。
【００５６】
（実施例８）
図１５に本実施例の３相モータ駆動装置の回路を示す。駆動回路８３Ｕ，８３Ｖ，８３Ｗの点線で囲んだ部分は同一パッケージに組み込まれていて、これらは実施例１〜実施例７と同様の駆動回路である。下アーム駆動電源７はＵ，Ｖ，Ｗ相とも共通である。上アーム駆動電源６Ｕ，６Ｖ，６ＷはＵ，Ｖ，Ｗ相独立である。直流の主電源５００はＵ，Ｖ，Ｗに共通である。マイコン３００からの指令により駆動信号処理回路８Ｕ，８Ｖ，８ＷがＵ，Ｖ，Ｗ各相の電力スイッチング素子１Ｕ，１Ｖ，１Ｗ，２Ｕ，２Ｖ，２Ｗをパルス幅変調（ＰＷＭ）信号でオン，オフして周波数可変の交流に変換し、モータ４００を所定の回転数にする。異常信号検出回路３９Ｕ，３９Ｖ，３９Ｗが動作すると駆動処理回路８Ｕ，８Ｖ，８Ｗからマイコンへ異常信号が伝わり、電力スイッチング素子１Ｕ，１Ｖ，１Ｗ，２Ｕ，２Ｖ，２Ｗを保護する。
【００５７】
なお、マイコン３００には主電源５００からモータ４００に供給する電流値の検出信号や、モータ４００の回転子位置の検出信号を入力し、これに基づいて駆動回路８３Ｕ，８３Ｖ，８３Ｗを制御する。
【００５８】
【発明の効果】
本発明のインバータ装置は、ホトカプラや誘電体分離基板を用いずに、上アーム駆動回路，電流検出回路を１つのＩＣチップに、高耐圧ｎ型ＭＯＳＦＥＴを１チップに、下アーム駆動回路，駆動信号処理回路を１つのＩＣチップにし、電力スイッチング素子を個別部品にして構成し、前記ＩＣチップをＳＯＩ基板上に形成したので、信頼性が高い高耐圧のインバータ装置を実現できる。
【図面の簡単な説明】
【図１】実施例１のインバータ装置のブロック図。
【図２】実施例１の実装模式図。
【図３】実施例２のインバータ装置の回路構成説明図。
【図４】実施例３のインバータ装置の回路構成説明図。
【図５】実施例４のインバータ装置の回路構成説明図。
【図６】実施例４の高耐圧ｎ型ＭＯＳＦＥＴの斜視図。
【図７】実施例４の高耐圧ｎ型ＭＯＳＦＥＴのゲート幅Ｗと抵抗両端電圧の関係の説明図。
【図８】実施例５のインバータ装置の回路構成説明図。
【図９】実施例５の実装模式図。
【図１０】実施例６のインバータ装置の回路構成説明図。
【図１１】実施例６の実装模式図。
【図１２】実施例７のインバータ装置の回路構成説明図。
【図１３】実施例７の実装模式図。
【図１４】実施例７のＩＣチップの断面説明図。
【図１５】実施例８の３相モータ駆動装置の回路構成図。
【図１６】ホトカプラを使用した従来技術のインバータ装置の説明図。
【図１７】昇圧レベルシフト回路を用いた別の従来技術のインバータ装置の説明図。
【図１８】誘電体分離基板を使用した従来技術の集積回路の断面図。
【符号の説明】
１…第１電力スイッチング素子、２…第２電力スイッチング素子、６…上アーム駆動電源、７…下アーム駆動電源、８…駆動信号処理回路、１０…主電源高圧端子、１１…出力端子、１２…主電源接地端子、１３，１４…ゲート端子、１５…上アーム側電源高圧側端子、１６…上アーム側電源接地側端子、１７…下アーム側電源高圧側端子、１８…下アーム側電源接地側端子、１９…ＮＯＴ回路、
２０…上アーム駆動回路、２１…下アーム駆動回路、２２，２４…ｐ型ＭＯＳＦＥＴ、２３，２５…ｎ型ＭＯＳＦＥＴ、３０…電流検出回路、３１，３５…高耐圧ｎ型ＭＯＳＦＥＴ、３２，３６，４２，４４…抵抗、３３，３７，４３，４５…ツェナーダイオード、３４…コンデンサ、３８，４６…ＲＳフリップフロップ、３９…異常信号検出回路、４０，４１…高耐圧ｐ型ＭＯＳＦＥＴ、５０，５１，５２，５３，５４，５５，５６，５７，５８，５９，６０，６１，６２，６３，６４ａ，６４ｂ，６５ａ，６５ｂ…ワイヤボンデイング、７０，７１ａ，７１ｂ，７２，７３，７４…配線、８０…絶縁基板、８１，８２…ＩＣチップ、９０，９３ａ，９３ｂ，９８，１５４ａ，１５４ｂ，１６６…ｎ＋　層、９１，１５２，１５７，１６２，１６４…ｎ−　層、９２ａ，９２ｂ，９７ａ，９７ｂ，９７ｃ，１５３，１６３…ｐ層、９４，１５５，１６０…ゲート酸化膜、９５，１５６，１６１…ゲート電極、９６…絶縁膜、１００…ソース電極、１０１ａ，１０１ｂ，１０１ｃ，１０２…電極、１５０…シリコン単結晶、１５１…酸化膜、１５８…ｎ層、
１５９ａ，１５９ｂ，１６５…ｐ＋　層、３００…マイコン、４００…モータ、
５００…主電源。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an inverter device having an arm composed of a plurality of power switching elements connected in series between main terminals, and particularly to an inverter device having a boost level shift circuit for transmitting a control signal from a low voltage side circuit to a high voltage side circuit. Further, the present invention relates to an inverter device provided with a step-down level shift circuit for transmitting a control signal from a high-voltage side circuit to a low-voltage side circuit.
[0002]
[Prior art]
FIG. 16 shows a block diagram of one arm of the conventional inverter device. In FIG. 16, 111 is a first power switching element, 112 is a second power switching element, 113 is an upper arm drive circuit, 114 is a lower arm drive circuit, 120 is a main power supply high voltage terminal, 121 is an output terminal, and 122 is a main power supply. Ground terminal, 123 is the gate terminal of the first power switching element, 124 is the gate terminal of the second power switching element, 125 is the power supply for driving the upper arm, 126 is the power supply for driving the lower arm, 127 is the drive signal processing circuit, and 130 is the drive signal processing circuit. It is a photocoupler. Since the emitter of the first power switching element 111 is connected to the output terminal 121, the first power switching element 111 is driven in a floating state with respect to the main power supply ground terminal 122. Upper arm drive circuit
Reference numeral 113 is connected to a floating potential, and when the first power switching element 111 is in the ON state, the same high voltage as that of the main power supply is applied. A photocoupler 130 is used to transmit a signal from the drive signal processing circuit 127 to the insulated upper arm drive circuit 113 (for example, see Patent Document 1).
[0003]
In another conventional technique, as shown in FIG. 17, a boosting level shift circuit including a high-breakdown-voltage n-type MOSFET and a voltage detection circuit is used instead of a photocoupler to transmit a signal from a lower arm to an upper arm. The vertical drive circuit and the signal processing circuit are integrated on one chip (for example, see Patent Document 1 and Non-Patent Document 1).
[0004]
FIG. 18 shows a cross-sectional structure of an integrated circuit according to the related art or another related art. As shown in FIG. 18, the oxide films 201a, 201b,
In the silicon single crystal island surrounded by 201c, n + Layers 202a, 202b, 202c and n − The layers 203a, 203b and 203c are provided. A substrate in which a single crystal island is surrounded by an oxide film in this manner is called a dielectric isolation substrate. n − A p-layer 204 is provided in the layer 203a, and n + A layer 205 is provided. n + Layer 205, p layer 204, n − A gate oxide film 206a is provided on the surface of the layer 203, and a gate electrode 207a is provided on the gate oxide film 206a. The gate electrode 207a is surrounded by the insulating film 208, and is insulated from the source electrode 210a.
n + Layer 202a, n − layer
203a, p layer 204, n + Layer 205a, gate oxide film 206a, gate electrode
The high breakdown voltage n-type MOSFET 31 is formed by 207a.
[0005]
Reference numeral 132 in FIG. 18 indicates a low withstand voltage n-type MOSFET of the upper arm drive circuit.
n − A p layer 213 is provided in the layer 203b, and two n layers are provided in the p layer 213. + A layer 212 is provided. n + A gate oxide film 206b is provided on the surface of the layer 212, the p-layer 213, and a gate electrode 207b is provided on the surface of the gate oxide film 206b. The high-breakdown-voltage n-type MOSFET 131 and the low-breakdown-voltage n-type MOSFET 132 are connected by an electrode 210b via an oxide film 208b. Reference numeral 133 indicates a resistor, and n − A p-layer 214 is provided in the layer 203c. The p-layer 214 is connected to the low breakdown voltage n-type MOSFET 132 via an electrode 210c disposed on the oxide film 208c.
[0006]
[Patent Document 1]
JP-A-5-316755
[Non-patent document 1]
Hitachi High Voltage Monolithic IC Data Book IC Series for Motor Driving, Hitachi, Ltd., March 2001, p. 113-116
[0007]
[Problems to be solved by the invention]
The prior art using the photocoupler is expensive because a compound semiconductor is used for the light emitting element of the photocoupler. In another conventional technique, a high-voltage n-type MOSFET is used to transmit a drive signal to a lower arm using a detection circuit. A high-voltage n-type MOSFET, a drive circuit, and a signal processing circuit are integrated into a single chip on a dielectric isolation substrate. When the breakdown voltage of the chip is increased for integration, for example, the high potential n shown in FIG. + It is necessary to increase the thickness of the oxide film 208a that insulates the layer 202a from the source electrode 210a. However, if the oxide film 208a is thickened, the time required for the oxidation process is increased and the production time is increased. There is a problem that warpage occurs, the wafer cracks, and the acquisition rate decreases.
[0008]
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems and to provide a highly reliable inverter device having a boost level shift circuit that transmits a control signal from a low voltage side circuit to a high voltage side circuit, and a control signal from the high voltage side circuit to the low voltage side circuit. An object of the present invention is to provide an inverter device having a step-down level shift circuit for transmitting.
[0009]
[Means for Solving the Problems]
The inverter device according to the present invention includes an upper arm drive circuit and a current detection circuit on one IC chip, a high breakdown voltage n-type MOSFET on one chip, and a lower arm drive circuit on a single IC chip. Then, these chips were arranged on an insulating substrate.
[0010]
In the inverter device of the present invention, the upper arm drive circuit and the current detection circuit are provided on one IC chip, the high voltage n-type MOSFET for set signal is provided on one chip, and the high voltage n-type MOSFET for reset signal is provided on one chip. Then, the lower arm drive circuit and the drive signal processing circuit were made into one IC chip, and these chips were arranged on an insulating substrate.
[0011]
Furthermore, the inverter device according to the present invention includes an upper arm drive circuit, a current detection circuit, an abnormality detection circuit, a single IC chip, a high voltage n-type MOSFET for a set signal, and a high voltage n-type MOSFET for a reset signal. One chip, high voltage p-type MOSFET for set signal on one chip, high voltage p-type MOSFET for reset signal on one chip, lower arm drive circuit, current detection circuit, and drive signal processing circuit as one IC chip Then, these chips were arranged on an insulating substrate.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, an IGBT is described as an example of a power switching element, but the same applies to a power MOSFET. In the following description, a high withstand voltage means a withstand voltage rated value of 100 V or more, and a low withstand voltage means a withstand voltage rated value of 20 V or less. In the embodiment of the present invention, a voltage of 100 V or more is applied to the main terminal of the inverter device, and a maximum main current of at least 10 A flows.
[0013]
(Example 1)
FIG. 1 is a block diagram of one arm of the inverter device of the present embodiment. As shown in FIG. 1, the collector of the first power switching element 1 is connected to the main power supply high voltage terminal 10, and the emitter of the first power switching element 1 and the collector of the second power switching element 2 are connected to the output terminal 11. I have. The emitter of the second power switching element 2 is connected to the main power ground terminal 12, and the main power ground terminal 12 is grounded. The upper arm drive circuit 20 is connected to the gate terminal 13 of the first power switching element 1, and the lower arm drive circuit 21 is connected to the gate terminal 14 of the second power switching element 2.
[0014]
Since the emitter of the first power switching element 1 is connected to the output terminal 11, the first power switching element 1 is driven with the potential floating with respect to the main power supply ground terminal 12. For this reason, the upper arm drive circuit 20 supplies electric power from the upper arm side power supply high voltage side terminal 15 insulated by a transformer or the like. Power is supplied to the lower arm drive circuit 21 from the power supply 7 connected to the main power supply ground terminal 12.
[0015]
A drive signal is sent from the drive signal processing circuit 8 to each of the upper and lower arms. The lower arm receives the signal of the drive signal processing circuit 8 by the lower arm drive circuit 21 and makes the second power switching element 2 conductive. The source of the high breakdown voltage n-type MOSFET 31 is connected to the main power supply ground terminal 12, and the drain of the high breakdown voltage n-type MOSFET 31 is connected to one terminal of the current detection circuit 30. The other terminal of the current detection circuit 30 is connected to the upper arm power supply high voltage side terminal 15, and the gate of the high breakdown voltage n-type MOSFET 31 is connected to the drive signal processing circuit 8. When an ON signal is applied from the drive signal processing circuit 8 to the gate of the high-breakdown-voltage n-type MOSFET 31, the high-breakdown-voltage n-type MOSFET 31 conducts, causing a current to flow. 20 and the upper arm drive circuit 20 conducts the first power switching element 1.
[0016]
FIG. 2 shows a schematic diagram of the mounting of this embodiment. In this embodiment, the upper arm drive circuit 20 and the current detection circuit 30 are a first IC chip 81, the lower arm drive circuit 21 and the drive signal processing circuit 8 are a second IC chip 82, and a high withstand voltage n-type The MOSFET 31 is used as a third chip of an individual component, and three chips of an IC chip 81, an IC chip 82, and a high withstand voltage n-type MOSFET 31 are arranged.
[0017]
The IC chip 82 is connected to the gate terminal 14 of the second power switching element 2 by wire bonding 50, connected to the lower arm side power supply high voltage side terminal 17 by wire bonding 51, and further connected to the lower arm side power supply ground by wire bonding 52. Side terminal
18.
[0018]
The source of the high breakdown voltage n-type MOSFET 31 is connected to the IC chip 82 by wire bonding 57, the gate is connected to the IC chip 82 by wire bonding 58, and the drain (back side) is connected to the wiring 70. The wiring 70 and the IC chip 81 are connected by a wire bonding 56.
[0019]
The IC chip 81 is connected to the gate terminal 13 of the first power switching element 1 by wire bonding 53, connected to the upper arm side power supply high voltage side terminal 15 by wire bonding 54, and connected to the upper arm side power supply ground side terminal by wire bonding 55. 16.
[0020]
In this embodiment, an IC chip 82 in which the lower arm drive circuit 21 and the drive signal processing circuit 8 are integrated, an IC chip 81 in which the upper arm drive circuit 20 and the current detection circuit 30 are integrated, and a high withstand voltage n-type MOSFET 31 Since the three chips are arranged on one surface of the insulating substrate 80 and each chip is arranged on the insulating substrate 80 while maintaining an appropriate distance (0.5 mm or more), the insulation between the upper arm and the lower arm is reduced. Can be easily secured. Further, in this embodiment, as shown in FIG. 2, the connection terminals drawn from the IC chip 81 and the connection terminals drawn from the IC chip 82 are arranged on two opposing sides of a substantially rectangular insulating substrate. Arm insulation is ensured. Further, in this embodiment, the IC chip 81, the IC chip 82, and the high breakdown voltage n-type MOSFET 31 are resin-molded in the same package, so that they are sufficiently protected from moisture from the outside. In addition, the resin to be molded may cover the entire front and back surfaces of the insulating substrate 80, or may cover only the IC chip and the wire bonding on the insulating substrate and expose the back surface of the insulating substrate without molding to promote heat radiation. You may leave it.
[0021]
In this embodiment, since the semiconductor device is constituted by the silicon semiconductor element and the insulating substrate without using a photocoupler, the device can be manufactured at a lower cost than when a photocoupler is used. Further, in this embodiment, since the high withstand voltage n-type MOSFET of the power switching element uses an individual high withstand voltage component, the thickness of the oxide film for increasing the withstand voltage of the inverter device, which is necessary when using the dielectric isolation substrate, is reduced. The withstand voltage can be easily increased without additional special manufacturing processes.
[0022]
(Example 2)
FIG. 3 shows a circuit configuration of the upper arm drive circuit 20 and the lower arm drive circuit 21 of the present embodiment. In the present embodiment, the upper arm drive circuit 20 includes a p-type MOSFET 22 and an n-type MOSFET.
The third embodiment is the same as the first embodiment except that the CMOSFET configuration including the MOSFET 23 and the CMOSFET configuration including the p-type MOSFET 24 and the n-type MOSFET 25 in the lower arm drive circuit 21 are used.
[0023]
In this embodiment, since the upper and lower arm driving circuits are of the CMOSFET configuration, the current flows only when the first power switching element 1 and the second power switching element 2 are turned on or off, and the upper arm driving circuit 20 and the lower arm driving circuit.
21, the generation of drive power can be suppressed.
[0024]
(Example 3)
FIG. 4 shows this embodiment. In the present embodiment, the current detection circuit 30 includes a resistor 32, and the rest is the same as the second embodiment. When an ON signal is transmitted from the drive signal processing circuit 8 to the gate of the high breakdown voltage n-type MOSFET 31, a current flows between the drain and the source, and a voltage drop occurs at the resistor 32 connected to the drain. This voltage drop causes the p-type MOSFET 22 to conduct, the n-type MOSFET 23 to become non-conducting, the high-potential of the upper arm drive power supply 6 to be applied to the gate of the first power switching element 1, and the first power switching element 1 Conduct.
[0025]
(Example 4)
FIG. 5 shows this embodiment. The present embodiment is different from the third embodiment in that the current detection circuit 30 includes a resistor 32 and a Zener diode 33 connected to both ends of the resistor 32. The current flowing through the high breakdown voltage n-type MOSFET 31 increases when the threshold voltage is lowered due to manufacturing variations or when the ambient temperature is low, the voltage generated across the resistor 32 increases, and the p-type MOSFET 22 and the n-type MOSFET 23 May be destroyed. The Zener diode 33 of this embodiment suppresses an excessive voltage generated at both ends of the resistor.
[0026]
FIG. 6 is a perspective view of the high breakdown voltage n-type MOSFET 31 of the present embodiment. As shown in FIG. + N on layer 90 − A layer 91 is formed, and this n − P layers 92a and 92b are formed in a layer 91. n in the p-layer 92a + Layer 93a is formed in p layer 92b by n + Forming a layer 93b; + Layer 93a, p layer 92a, n − Layer 91, p layer 92b, n + A gate oxide film 94 is provided on the surface over the layer 93b, and a gate electrode 95 is provided on the gate oxide film 94. p layers 92a and 92b and n + The layers 93a and 93b, the gate oxide film 94, and the gate electrode 95 constitute a MOSFET.
[0027]
p layers 92a and 92b and n + The layers 93a and 93b are in ohmic contact with the source electrode 100. Also, n − P layers 97a, 97b, 97c are arranged in a layer 91, and p layers 92b, n − An oxide film 99a is formed over the layer 91 and the p-layer 97a. − An oxide film 99b is provided over the layer 91 and the p layer 97b. Furthermore, the p layer
97b, n − An oxide film 99c is formed over the layer 91 and the p layer 97c, − Layer 91, n + An oxide film 99d is provided over the layer 98.
[0028]
Source electrode 100 is formed on oxide film 99a by n. + An electrode 101a that extends along the direction in which the layer 98 extends and is ohmic-connected to the p-layer 97a is formed on the oxide film 99b by n. + It extends along the direction in which the layer 98 extends. Further, an electrode 101b ohmic-connected to the p-layer 97b is formed on the oxide film 99c by n + An electrode 101c extending along the direction in which the layer 98 extends and being ohmic-connected to the p-layer 97c is formed on the oxide film 99d by n. + It extends along the direction in which the layer 98 extends. Also, n + The electrode 102 ohmic-connected to the layer 98 also extends along the direction in which the p-layer 92b extends. If the drain electrode 102 is n + Ohmic connection to layer 90.
[0029]
The high breakdown voltage n-type MOSFET 31 operates as follows. When a positive voltage is applied to the gate electrode 95 in a state where the source electrode 100 is grounded and a high voltage is applied to the drain electrode 102, the p-layers 92a and 92b are inverted to form a channel, and electrons pass through the channel to form n. − Flows into layer 91 and further electrons + It reaches the drain electrode 102 through the layer 90. The source electrode 100, the electrode 101a, the electrode 101b, and the electrode 101c are n + By extending the depletion layer in the direction of the layer 98, the breakdown voltage of the element is increased. Since the cut surface appears on the surface of the end portion, there are many recombination levels. When the depletion layer reaches the end portion, the leakage current increases. n + The layer 98 and the electrode 102 are made of oxide films 99a, 99b,
Due to the charge in 99c and 99d and the charge in the protective film not shown in the drawing, n − The layer 91 is inverted to p-type to prevent the depletion layer from reaching the end. n − By increasing the resistivity and thickness of the layer 91 and the number of the p-layers 97a, 97b, 97c, the breakdown voltage of the element can be easily increased without changing the manufacturing method.
[0030]
FIG. 7 shows the relationship between the width W of the gate electrode of the high-breakdown-voltage n-type MOSFET shown in FIG. FIG. 7 shows a case where the resistance 32 is 1 kΩ. When the gate width W is 10 μm or more, the horizontal axis is a logarithmic scale. When the gate width W is zero, no current flows and the voltage generated across the resistor 32 is 0 V. However, when the gate width W is increased, the current increases and the voltage across the resistor 32 increases. When the Zener diode 33 is connected to the resistor 32, as shown in FIG. 7, even when the current is increased by increasing the gate width W, the voltage generated across the resistor 32 is suppressed by the Zener voltage. However, when the gate width W exceeds 10,000 μm, the voltage across the resistor 32 increases again. This is because a Zener diode that can be integrated into an IC has a large resistance component, and a large current causes a large voltage drop. When the value of the resistor 32 is reduced, the voltage generated at both ends of the resistor 32 is suppressed, but the current flowing through the resistor 32 increases and the loss increases, which is not desirable. The gate width W is desirably 10000 μm or less for use at a Zener voltage or lower that does not damage the p-type MOSFET 22 and the n-type MOSFET 23. Further, in a region equal to or lower than the Zener voltage, the voltage across the resistor 32 fluctuates due to current fluctuations due to manufacturing variations and temperature changes. Therefore, the gate width W is desirably 10 μm or more. 10,000 μm is desirable.
[0031]
(Example 5)
FIG. 8 shows this embodiment. This embodiment is the same as the fourth embodiment except that a capacitor 34 is connected to both ends of the resistor 32. The upper ground potential (the potential between the output terminal 11 and the upper arm power supply ground terminal 16) is the main power supply voltage when the first power switching element 1 is conductive, and when the second power switching element 2 is conductive. Becomes the ground potential, and becomes approximately (main power supply voltage) / 2 when both the first power switching element 1 and the second power switching element 2 are non-conductive. In the process of conducting the first power switching element 1, the upper ground potential changes from (main power supply voltage) / 2 to the main power supply voltage, and in the process of conducting the second power switching element 2, the voltage becomes (main power supply voltage). ) / 2 to the ground potential. Due to the voltage fluctuation dV / dt and the source-drain capacitance Csd (not shown) of the high-breakdown-voltage n-type MOSFET 31, a current transiently flows with a magnitude of Csd × dV / dt. Are arranged at both ends of the resistor 32 and connected in series to the capacitance Cds between the source and the drain to reduce the apparent capacitance between the source and the drain and suppress this current.
[0032]
FIG. 9 shows a mounting diagram of the present embodiment. The capacitor 34 is connected to the wirings 71a and 71b, and is connected to the IC chip 81 by wire bonding 59 and 60. The upper limit of the capacitance of the capacitor formed on the semiconductor substrate is about 10 pF due to the limitation of the chip area. For this reason, in the present embodiment, the capacitor 34 is formed as a separate chip from the resistor 32 and the Zener diode 33, and is used as the fourth chip as an individual component. Of course, if the capacitor 34 can be manufactured on the same chip as the Zener diode 33, such a configuration is adopted. May be. In this embodiment, the four chips are mounted on one rectangular insulating substrate, and the insulating substrate and these chips are resin-molded in the same manner as in the first embodiment.
[0033]
(Example 6)
FIG. 10 shows this embodiment. In the present embodiment, two high-breakdown-voltage n-type MOSFETs 31 and 35 are provided, resistors 32 and 36 and zener diodes 33 and 37 are connected to the respective drains, and one terminal of the resistor 32 is connected to the set side of the RS flip-flop 38. Connected to S. The other terminal of the resistor 36 is connected to the reset side R of the RS flip-flop 38, and the output of the RS flip-flop 38 is connected to the input of the NOT circuit. The output of the NOT circuit is connected to the gate terminals of the p-type MOSFET 22 and the n-type MOSFET 23.
[0034]
In this embodiment, the p-type MOSFET 22, the n-type MOSFET 23, the NOT circuit 19, the RS flip-flop 38, the resistors 32 and 36, and the Zener diodes 33 and 37 are integrated on the first IC chip 81, The type MOSFET 24, the n-type MOSFET 25, and the drive signal processing circuit are integrated as a second IC chip 82. The high breakdown voltage n-type MOSFETs 31 and 35 are independent as a third chip and a fourth chip of the individual components, respectively.
[0035]
The operation of this embodiment will be described. When a short-time (about 1 μs) pulse is applied to the gate terminal of the high-breakdown-voltage n-type MOSFET 31 from the drive signal processing circuit 8, the high-breakdown-voltage n-type MOSFET 31 conducts for the time during which the pulse is being input. A voltage is generated, an input signal is applied to the set side S of the RS flip-flop 38, and the output of the RS flip-flop 38 becomes the upper arm power supply voltage. This output is inverted by the NOT circuit 19, and is applied to the gates of the p-type MOSFET 22 and the n-type MOSFET 23 as the ground potential of the upper arm side power supply.
The MOSFET 23 is turned off, and the first power switching element 1 is turned on.
[0036]
When the first power switching element 1 is turned off, a pulse is applied from the drive signal processing circuit 8 to the gate terminal of the high-withstand voltage n-type MOSFET 35 for a short time. Is conducted, a voltage is generated across the resistor 36, an input signal is applied to the reset side R of the RS flip-flop 38, and the output of the RS flip-flop 38 becomes the ground potential of the upper arm side power supply. This output is inverted by the NOT circuit 19, and the gates of the p-type MOSFET 22 and the n-type MOSFET 23 become the upper arm-side power supply potential.
The MOSFET 23 becomes conductive and the first power switching element 1 becomes non-conductive. In the present embodiment, the current flows only for a short time in a state where the power supply voltage is applied to the high breakdown voltage n-type MOSFETs 31 and 35, so that the loss in the high breakdown voltage n-type MOSFETs 31 and 35 can be greatly reduced.
[0037]
FIG. 11 is a mounting schematic diagram of the present embodiment. P-type on rectangular insulating substrate 80
MOSFET 24, n-type MOSFET 25 and drive signal processing circuit 8 are integrated
An IC chip 82 in which a p-type MOSFET 22, an n-type MOSFET 23, an RS flip-flop 38, resistors 32 and 36, and zener diodes 33 and 37 are integrated, and four chips of high withstand voltage n-type MOSFETs 31 and 35 Are placed.
[0038]
The IC chip 82 is connected to the gate terminal 14 of the second power switching element 2 by wire bonding 50, connected to the lower arm side power supply high voltage side terminal 17 by wire bonding 51, and further connected to the lower arm side power ground by wire bonding 52. It is connected to the side terminal 18.
[0039]
The source of the high breakdown voltage n-type MOSFET 31 is connected to the IC chip 82 by wire bonding 57, the gate is connected to the IC chip 82 by wire bonding 58, and the drain side (back side) is connected to the wiring 70. The wiring 70 and the IC chip 81 are connected by the wire bonding 56.
[0040]
The source of the high withstand voltage n-type MOSFET 35 is connected to the IC chip 82 by wire bonding 62, the gate is connected to the IC chip 82 by wire bonding 63, and the drain side (back side) is connected to the wiring 72. The wiring 72 and the IC chip 81 are connected by a wire bonding 61.
[0041]
The IC chip 81 is connected to the gate terminal 13 of the first power switching element 1 by wire bonding 53, connected to the upper arm side power supply high voltage side terminal 15 by wire bonding 54, and further connected to the upper arm side power supply ground by wire bonding 55. Side terminal
16.
[0042]
(Example 7)
FIG. 12 shows this embodiment. In this embodiment, the sources of the high-breakdown-voltage p-type MOSFETs 40 and 41 are connected to the upper arm power supply high voltage side terminal 15. The drain terminal of the high breakdown voltage p-type MOSFET 40 is connected to one terminal of the resistor 42, the cathode of the Zener diode 43, and the set terminal S of the RS flip-flop 46. The other terminal of the resistor 42 and the anode of the Zener diode 43 are grounded. The drain terminal of the high voltage p-type MOSFET 41 is connected to one terminal of the resistor 44, the cathode of the Zener diode 45, and the reset terminal R of the RS flip-flop 46. resistance
The other terminal of 44 and the anode of Zener diode 45 are grounded. The output signal of the abnormal signal detection circuit 39 is input to the gates of the high breakdown voltage p-type MOSFETs 40 and 41. The output of the RS flip-flop 46 is connected to the drive signal processing circuit 8.
[0043]
In this embodiment, the p-type MOSFET 22, the n-type MOSFET 23, and the NOT circuit
26, an RS flip-flop 38, resistors 32 and 36, zener diodes 33 and 37, and an abnormal signal detection circuit 39 are integrated as a first IC chip 81, and a p-type MOSFET 24, an n-type MOSFET 25, an RS flip-flop 46 and a resistor 42 are integrated. , 44, Zener diodes 43, 45, and a drive signal processing circuit are integrated as a second IC chip 82, the high-breakdown-voltage n-type MOSFETs 33, 31 are a third chip and a fifth chip, and the high-breakdown-voltage p-type MOSFETs 40, 41 are integrated. The sixth chip and the seventh chip are independent chips.
[0044]
This embodiment operates as follows. When the abnormal signal detecting circuit 39 detects abnormalities such as overcurrent, temperature abnormality, lower power supply voltage on the upper arm, and overvoltage of the main power supply, a short-time ON signal is input to the gate of the high-breakdown-voltage p-type MOSFET 40 to activate the step-down level shift circuit. The high withstand voltage p-type MOSFET 40 is turned on, and a current flows through the resistor 42.
The voltage signal generated at both ends is input to the set side S of the RS flip-flop 46, and the output signal of the RS flip-flop 46 is transmitted to the drive signal processing circuit 8.
[0045]
When the abnormal state is released, an ON signal is input for a short time from the abnormal signal detection circuit 39 to the gate of the high breakdown voltage p-type MOSFET 41, the high breakdown voltage p-type MOSFET 41 conducts, and a current flows through the resistor 44. At this time, a voltage is generated across the resistor 44, a signal is input to the reset side R of the RS flip-flop 46, and the output of the RS flip-flop 46 becomes the ground potential. Other operations are the same as in the sixth embodiment.
[0046]
FIG. 13 shows a mounting diagram of the present embodiment. On an insulating substrate 80, a p-type MOSFET 24, an n-type MOSFET 25, resistors 42 and 44, zener diodes 43 and 45,
An IC chip 82 in which the RS flip-flop 46 and the drive signal processing circuit 8 are integrated, the p-type MOSFET 22, the n-type MOSFET 23, the RS flip-flop 38, the resistors 32 and 36, the Zener diodes 33 and 37, and the abnormal signal detection circuit 39 Integrated IC chip 82, high-breakdown-voltage n-type MOSFETs 31, 35, and high-breakdown-voltage p-type
Six chips including MOSFETs 40 and 41 were arranged.
[0047]
The IC chip 82 is connected to the gate terminal 14 of the second power switching element 2 by wire bonding 50, connected to the lower arm side power supply high voltage side terminal 17 by wire bonding 51, and further connected to the lower arm side power supply ground by wire bonding 52. Side terminal
18.
[0048]
The source of the high breakdown voltage n-type MOSFET 31 is connected to the IC chip 82 by wire bonding 57, the gate is connected to the IC chip 82 by wire bonding 58, and the drain side (back side) is connected to the wiring 70. The wiring 70 and the IC chip 81 are connected by a wire bonding 56.
[0049]
The source of the high withstand voltage n-type MOSFET 35 is connected to the IC chip 82 by wire bonding 62, the high withstand voltage n gate is connected to the IC chip 82 by wire bonding 63, and the drain side (back side) is connected to the wiring 71.
[0050]
The source of the high-breakdown-voltage p-type MOSFET 40 is connected to the IC chip 81 by wire bonding 64a, the gate is connected to the IC chip 81 by wire bonding 64b, and the drain side (back side) is connected to the wiring 73. The wiring 73 and the IC chip 82 are connected by a wire bonding 66.
[0051]
The source of the high breakdown voltage p-type MOSFET 41 is connected to the IC chip 81 by wire bonding 65a, the gate is connected to the IC chip 81 by wire bonding 65b, and the drain side (back side) is connected to the wiring 74. The wiring 74 and the IC chip 82 are connected by a wire bonding 67.
[0052]
The IC chip 81 is connected to the gate terminal 13 of the first power switching element 1 by wire bonding 53, and the upper arm side power supply high voltage side terminal is connected by wire bonding 54.
15 and further to the upper arm side power supply ground side terminal 16 by wire bonding 55.
[0053]
FIG. 14 is an explanatory sectional view of the IC chips 81 and 82 of the present embodiment. An oxide film 151 is formed on a silicon single crystal 150, and n − The layers 152, 157, 162, 164 are insulated by the oxide film 151, respectively. n − The oxide film 151 between the layers is formed perpendicular to the silicon substrate surface. Such a substrate insulated by a substantially vertical oxide film is called an SOI (Silicon On Insulator) substrate. n − A p layer 153 is provided in the layer 152, and n + Layers 154a and 154b are provided. n + Layer 154a, p layer 153, n + A gate oxide film 155 was provided over the layer 154b, and a gate electrode 156 was provided on the gate oxide film 155. n + The layers 154a and 154b, the p layer 153, the gate oxide film 155, and the gate electrode 156 form the n-type MOSFET 23.
[0054]
n − An n-layer 158 is provided in the layer 157, and a p-layer is formed in the n-layer 158. + Layer 159a,
159b are provided. p + Layer 159a, n-layer 158, p + A gate oxide film 160 is provided over the layer 159b, and a gate electrode 161 is provided on the gate oxide film 160. p + The p-type MOSFET 22 is formed by the layers 159a and 159b, the n-layer 158, the gate oxide film 160, and the gate electrode 161. − A p-layer 163 is provided in the layer 162 to form the resistor 32, and n − P in layer 164 + Layer 165 and n + layer
166 are provided to form the Zener diode 33.
[0055]
In the dielectric isolation substrate, the distance between silicon single crystal islands cannot be reduced because the oxide film for insulation is inclined as shown in FIG. 18, for example. On the other hand, the SOI substrate has a vertical oxide film for insulation, so that the distance between silicon single crystals can be reduced and the element area can be reduced, so that the SOI substrate can be manufactured at low cost.
[0056]
(Example 8)
FIG. 15 shows a circuit of the three-phase motor drive device of the present embodiment. Driving circuits 83U, 83V and 83W surrounded by dotted lines are incorporated in the same package, and these are driving circuits similar to those of the first to seventh embodiments. The lower arm drive power source 7 is common to the U, V, and W phases. The upper arm drive power supplies 6U, 6V, and 6W are independent of the U, V, and W phases. The DC main power supply 500 is common to U, V, and W. The drive signal processing circuits 8U, 8V, 8W turn on and off the power switching elements 1U, 1V, 1W, 2U, 2V, 2W of the U, V, W phases by pulse width modulation (PWM) signals in accordance with commands from the microcomputer 300. The motor 400 is converted to a variable frequency alternating current, and the motor 400 is set to a predetermined rotational speed. When the abnormal signal detection circuits 39U, 39V, 39W operate, an abnormal signal is transmitted from the drive processing circuits 8U, 8V, 8W to the microcomputer to protect the power switching elements 1U, 1V, 1W, 2U, 2V, 2W.
[0057]
The microcomputer 300 receives a detection signal of a current value supplied from the main power supply 500 to the motor 400 and a detection signal of a rotor position of the motor 400, and controls the drive circuits 83U, 83V, and 83W based on the signals.
[0058]
【The invention's effect】
The inverter device of the present invention uses an upper arm drive circuit and a current detection circuit on one IC chip, a high withstand voltage n-type MOSFET on one chip, a lower arm drive circuit, and a drive signal without using a photocoupler or a dielectric separation substrate. Since the processing circuit is configured as one IC chip, the power switching elements are configured as individual components, and the IC chip is formed on an SOI substrate, a highly reliable high-voltage inverter device can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram of an inverter device according to a first embodiment.
FIG. 2 is a schematic diagram of the mounting of the first embodiment.
FIG. 3 is an explanatory diagram of a circuit configuration of an inverter device according to a second embodiment.
FIG. 4 is an explanatory diagram of a circuit configuration of an inverter device according to a third embodiment.
FIG. 5 is an explanatory diagram of a circuit configuration of an inverter device according to a fourth embodiment.
FIG. 6 is a perspective view of a high-breakdown-voltage n-type MOSFET according to a fourth embodiment.
FIG. 7 is an explanatory diagram illustrating a relationship between a gate width W and a voltage across a resistor of a high-breakdown-voltage n-type MOSFET according to a fourth embodiment.
FIG. 8 is an explanatory diagram of a circuit configuration of an inverter device according to a fifth embodiment.
FIG. 9 is a schematic view of the mounting of the fifth embodiment.
FIG. 10 is an explanatory diagram of a circuit configuration of an inverter device according to a sixth embodiment.
FIG. 11 is a schematic diagram of the mounting of the sixth embodiment.
FIG. 12 is an explanatory diagram of a circuit configuration of an inverter device according to a seventh embodiment.
FIG. 13 is a schematic diagram of the mounting of the seventh embodiment.
FIG. 14 is an explanatory sectional view of an IC chip according to a seventh embodiment.
FIG. 15 is a circuit configuration diagram of a three-phase motor drive device according to an eighth embodiment.
FIG. 16 is an explanatory diagram of a conventional inverter device using a photocoupler.
FIG. 17 is an explanatory diagram of another conventional inverter device using a boost level shift circuit.
FIG. 18 is a cross-sectional view of a prior art integrated circuit using a dielectric isolation substrate.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... 1st power switching element, 2 ... 2nd power switching element, 6 ... Upper arm drive power supply, 7 ... Lower arm drive power supply, 8 ... Drive signal processing circuit, 10 ... Main power supply high voltage terminal, 11 ... Output terminal, 12 ... Main power supply ground terminal, 13, 14 ... Gate terminal, 15 ... Upper arm side power supply high voltage side terminal, 16 ... Upper arm side power supply ground side terminal, 17 ... Lower arm power supply high voltage side terminal, 18 ... Lower arm side power supply ground Side terminal, 19 ... NOT circuit,
Reference numeral 20: upper arm drive circuit, 21: lower arm drive circuit, 22, 24: p-type MOSFET, 23, 25: n-type MOSFET, 30: current detection circuit, 31, 35: high withstand voltage n-type MOSFET, 32, 36, 42, 44: resistor, 33, 37, 43, 45: Zener diode, 34: capacitor, 38, 46: RS flip-flop, 39: abnormal signal detection circuit, 40, 41: high withstand voltage p-type MOSFET, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64a, 64b, 65a, 65b ... wire bonding, 70, 71a, 71b, 72, 73, 74 ... wiring, 80 ... insulating substrate, 81, 82 ... IC chip, 90, 93a, 93b, 98, 154a, 154b, 166 ... n + Layers, 91, 152, 157, 162, 164... N − Layers 92a, 92b, 97a, 97b, 97c, 153, 163 ... p layers, 94, 155, 160 ... gate oxide films, 95, 156, 161 ... gate electrodes, 96 ... insulating films, 100 ... source electrodes, 101a, 101b, 101c, 102: electrodes, 150: silicon single crystal, 151: oxide film, 158: n layer,
159a, 159b, 165 ... p + Layer, 300: microcomputer, 400: motor,
500: Main power supply.

Claims (15)

主端子間に上アーム半導体電力スイッチング素子と下アーム半導体電力スイッチング素子とを直列接続したアームと、該アームの駆動回路とを備えたインバータ装置において、
該インバータ装置が１つあるいは複数のアームを備え、
前記１アーム分の駆動回路が、圧側回路から高圧側回路に制御信号を伝達する昇圧レベルシフト回路と、上アーム駆動回路と、下アーム駆動回路と駆動信号処理回路とを備え、
該昇圧レベルシフト回路が電流検出回路と高耐圧ＭＯＳＦＥＴとを備えており、
上アーム駆動回路と電流検出回路とを含む第１の半導体チップと、下アーム駆動回路と駆動信号処理回路とを含む第２の半導体チップと、前記レベルシフト回路用高耐圧ＭＯＳＦＥＴを含む第３の半導体チップとを備えることを特徴とするインバータ装置。In an inverter device including an arm in which an upper arm semiconductor power switching element and a lower arm semiconductor power switching element are connected in series between main terminals, and a drive circuit for the arm,
The inverter device includes one or more arms,
A drive circuit for the one arm includes a boost level shift circuit that transmits a control signal from the pressure side circuit to the high voltage side circuit, an upper arm drive circuit, a lower arm drive circuit, and a drive signal processing circuit;
The boost level shift circuit includes a current detection circuit and a high voltage MOSFET,
A first semiconductor chip including an upper arm drive circuit and a current detection circuit; a second semiconductor chip including a lower arm drive circuit and a drive signal processing circuit; and a third semiconductor chip including the high voltage MOSFET for the level shift circuit. An inverter device comprising a semiconductor chip. 請求項１において、前記第１の半導体チップと、第２の半導体チップと、第３の半導体チップとが同一の絶縁基板に配置されていることを特徴とするインバータ装置。2. The inverter device according to claim 1, wherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are arranged on the same insulating substrate. 請求項２において、前記絶縁基板に搭載した３個の半導体チップを同一パッケージに樹脂モールドしたことを特徴とするインバータ装置。3. The inverter device according to claim 2, wherein three semiconductor chips mounted on the insulating substrate are resin-molded in the same package. 請求項２において、前記上アーム駆動回路と下アーム駆動回路とが、何れも
ＣＭＯＳＦＥＴであること特徴とするインバータ装置。3. The inverter device according to claim 2, wherein both the upper arm drive circuit and the lower arm drive circuit are CMOSFETs. 請求項２において、前記電流検出回路が電流を電圧に変換する抵抗を備えていることを特徴とするインバータ装置。3. The inverter device according to claim 2, wherein the current detection circuit includes a resistor that converts a current into a voltage. 請求項５において、前記電流検出回路の前記抵抗にツェナーダイオードが並列に接続していることを特徴とするインバータ装置。The inverter device according to claim 5, wherein a Zener diode is connected in parallel to the resistor of the current detection circuit. 請求項６において、前記電流検出回路の並列接続した抵抗とツェナーダイオードに、コンデンサを並列に接続したことを特徴とするインバータ装置。7. The inverter device according to claim 6, wherein a capacitor is connected in parallel to the resistor and the Zener diode of the current detection circuit connected in parallel. 請求項７において、前記電流検出回路の抵抗とツェナーダイオードとに並列接続するコンデンサを、第４のチップとして前記絶縁基板に搭載したことを特徴とするインバータ装置。8. The inverter device according to claim 7, wherein a capacitor connected in parallel with the resistance of the current detection circuit and the Zener diode is mounted on the insulating substrate as a fourth chip. 請求項２において、前記高耐圧ｎ型ＭＯＳＦＥＴのゲート幅が１０μｍ〜
１００００μｍであることを特徴とするインバータ装置。3. The high-breakdown-voltage n-type MOSFET according to claim 2, wherein the gate width is 10 μm or more.
An inverter device having a size of 10,000 μm. 主端子間に上アーム半導体電力スイッチング素子と下アーム半導体電力スイッチング素子とを直列接続したアームと、該アームの駆動回路とを備えたインバータ装置において、
該インバータ装置が１つあるいは複数のアームを備え、
前記１アーム分の駆動回路が、圧側回路から高圧側回路に制御信号を伝達する昇圧レベルシフト回路と、上アーム駆動回路と、下アーム駆動回路と駆動信号処理回路とを備え、
該昇圧レベルシフト回路が電流検出回路と高耐圧ＭＯＳＦＥＴとを備えており、
前記上アーム駆動回路が、セット信号を受けて前記半導体電力スイッチング素子を導通保持し、リセット信号を受けて前記半導体電力スイッチング素子を非導通に保持する回路を備えていて、
前記上アーム駆動回路と電流検出回路とを含む第１の半導体チップと、下アーム駆動回路と駆動信号処理回路とを含む第２の半導体チップと、前記セット信号をレベルシフトする高耐圧ＭＯＳＦＥＴを含む第５の半導体チップと、前記リセット信号をレベルシフトする高耐圧ＭＯＳＦＥＴを含む第６の半導体チップと、を備えることを特徴とするインバータ装置。In an inverter device including an arm in which an upper arm semiconductor power switching element and a lower arm semiconductor power switching element are connected in series between main terminals, and a drive circuit for the arm,
The inverter device includes one or more arms,
A drive circuit for the one arm includes a boost level shift circuit that transmits a control signal from the pressure side circuit to the high voltage side circuit, an upper arm drive circuit, a lower arm drive circuit, and a drive signal processing circuit;
The boost level shift circuit includes a current detection circuit and a high voltage MOSFET,
The upper arm drive circuit includes a circuit that receives the set signal, holds the semiconductor power switching element conductive, receives the reset signal, and holds the semiconductor power switching element non-conductive,
A first semiconductor chip including the upper arm drive circuit and the current detection circuit; a second semiconductor chip including the lower arm drive circuit and a drive signal processing circuit; and a high voltage MOSFET for level shifting the set signal. An inverter device comprising: a fifth semiconductor chip; and a sixth semiconductor chip including a high breakdown voltage MOSFET for shifting the level of the reset signal. 請求項１０において、前記第１の半導体チップと、第２の半導体チップと、第５の半導体チップと、第６の半導体チップとが同一の絶縁基板に配置されていることを特徴とするインバータ装置。11. The inverter device according to claim 10, wherein the first semiconductor chip, the second semiconductor chip, the fifth semiconductor chip, and the sixth semiconductor chip are arranged on the same insulating substrate. . 主端子間に上アーム半導体電力スイッチング素子と下アーム半導体電力スイッチング素子とを直列接続したアームと、該アームの駆動回路とを備えたインバータ装置において、
該インバータ装置が１つあるいは複数のアームを備え、
前記１アーム分の駆動回路が、圧側回路から高圧側回路に制御信号を伝達する昇圧レベルシフト回路と、上アーム駆動回路と、下アーム駆動回路と、駆動信号処理回路と、異常検出手段とを備え、
前記昇圧レベルシフト回路が電流検出回路と高耐圧ＭＯＳＦＥＴとを備え、
前記異常検出手段が異常検出回路と異常信号伝達手段とを有し、該異常信号伝達手段が高耐圧ＭＯＳＦＥＴと電圧信号発生手段とを備えていて、
上アーム駆動回路と電流検出回路と異常検出回路とを含む第１の半導体チップと、下アーム駆動回路と駆動信号処理回路とを含む第２の半導体チップと、前記レベルシフト回路用高耐圧ＭＯＳＦＥＴを含む第３の半導体チップと、前記異常信号伝達手段の高耐圧ＭＯＳＦＥＴを含む第７の半導体チップとを備えることを特徴とするインバータ装置。In an inverter device including an arm in which an upper arm semiconductor power switching element and a lower arm semiconductor power switching element are connected in series between main terminals, and a drive circuit for the arm,
The inverter device includes one or more arms,
A drive circuit for the one arm includes a boost level shift circuit that transmits a control signal from the pressure side circuit to the high voltage side circuit, an upper arm drive circuit, a lower arm drive circuit, a drive signal processing circuit, and abnormality detection means. Prepare,
The boost level shift circuit includes a current detection circuit and a high withstand voltage MOSFET,
The abnormality detection means has an abnormality detection circuit and an abnormality signal transmission means, and the abnormality signal transmission means has a high breakdown voltage MOSFET and a voltage signal generation means,
A first semiconductor chip including an upper arm drive circuit, a current detection circuit, and an abnormality detection circuit, a second semiconductor chip including a lower arm drive circuit and a drive signal processing circuit, and the high voltage MOSFET for the level shift circuit. An inverter device, comprising: a third semiconductor chip including a third semiconductor chip including a high breakdown voltage MOSFET of the abnormal signal transmission means. 請求項１２において、前記異常信号伝達手段が、異常セット信号用高耐圧ｎ型ＭＯＳＦＥＴと、異常リセット信号用高耐圧ｎ型ＭＯＳＦＥＴとを備え、前記第７の半導体チップを複数個備えることを特徴とするインバータ装置。13. The device according to claim 12, wherein the abnormal signal transmitting means includes a high voltage n-type MOSFET for an abnormal set signal, a high voltage n-type MOSFET for an abnormal reset signal, and a plurality of the seventh semiconductor chips. Inverter device. 請求項１において、前記第１の半導体チップと第２の半導体チップがＳＯＩ
（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板に半導体回路を形成したことを特徴とするインバータ装置。2. The semiconductor device according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are formed of SOI.
(Silicon On Insulator) An inverter device wherein a semiconductor circuit is formed on a substrate. 直流をインバータ装置で周波数可変の交流に変換してモータを駆動するモータ駆動装置において、
前記インバータ装置が主端子間に上アーム半導体電力スイッチング素子と下アーム半導体電力スイッチング素子とを直列接続した１つあるいは複数のアームと、該アームの駆動回路とを備え、
前記１アーム分の駆動回路が、圧側回路から高圧側回路に制御信号を伝達する昇圧レベルシフト回路と、上アーム駆動回路と、下アーム駆動回路と駆動信号処理回路とを備え、
該昇圧レベルシフト回路が電流検出回路と高耐圧ＭＯＳＦＥＴとを備えており、
上アーム駆動回路と電流検出回路とを含む第１の半導体チップと、下アーム駆動回路と駆動信号処理回路とを含む第２の半導体チップと、前記レベルシフト回路用高耐圧ＭＯＳＦＥＴを含む第３の半導体チップとを備えることを特徴とするモータ駆動装置。In a motor drive device that drives a motor by converting DC to AC with variable frequency by an inverter device,
The inverter device includes one or more arms in which an upper arm semiconductor power switching element and a lower arm semiconductor power switching element are connected in series between main terminals, and a drive circuit for the arm.
A drive circuit for the one arm includes a boost level shift circuit that transmits a control signal from the pressure side circuit to the high voltage side circuit, an upper arm drive circuit, a lower arm drive circuit, and a drive signal processing circuit;
The boost level shift circuit includes a current detection circuit and a high voltage MOSFET,
A first semiconductor chip including an upper arm drive circuit and a current detection circuit; a second semiconductor chip including a lower arm drive circuit and a drive signal processing circuit; and a third semiconductor chip including the high voltage MOSFET for the level shift circuit. A motor drive device comprising: a semiconductor chip.
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