JP3201991B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an interlayer insulating film having a property of flowing on a substrate by heat treatment and a method of manufacturing the same, and more particularly to a semiconductor device having a nitride film provided on the interlayer insulating film. The present invention relates to measures for preventing deformation of a nitride film.

[0002]

2. Description of the Related Art In a conventional semiconductor device, the number of wiring layers formed on a semiconductor substrate is increasing with the increase in integration. Therefore, after forming the first BPSG film on the first wiring layer and performing heat treatment, the first BPSG film is planarized, and then the second wiring layer and the second BPSG film are formed on the first BPSG film. A second BPSG film is formed, and the second BPSG film is planarized. In this case, during the heat treatment of the second BPSG, there may be a problem that the first BPSG film also flows and the second wiring layer moves. As a method of preventing this, a method of forming a silicon nitride film on the first BPSG film is disclosed in Japanese Patent Application Laid-Open No. 5-160276.

FIG. 16 is a cross-sectional view showing an example of a conventional semiconductor device provided with such a silicon nitride film for preventing flow. As shown in FIG. 16, the first
A gate electrode 47 of a transistor which is a wiring layer is formed, a first BPSG film 48 which is a first interlayer insulating film is formed on the gate electrode 47, and then a first BPSG film 48 is formed on the first BPSG film 48. A polycide wiring 49 is formed as a second wiring layer. Then, after a silicon nitride film 50 for protection is formed on the first BPSG film 48 in order to prevent flow and oxidation of the first BPSG film 48,
On the silicon nitride film 50, a second interlayer insulating film
Of the BPSG film 51 is formed. This method uses a second B
Even if heat treatment is performed in a water vapor atmosphere to planarize the PSG film 51, the flow of the first BPSG film 48 is prevented by blocking the water vapor by the silicon nitride film 50,
This is to prevent a defect caused by the movement of the polycide wiring 49.

In a method of forming a stacked DRAM cell, a silicon nitride oxide film is often used as a capacitance insulating film that satisfies required characteristics such as refresh characteristics and insulation resistance. The base of the capacitor electrode is BPS
In many cases, planarization is performed using a G film.

Hereinafter, the structure of a conventional stacked DRAM will be schematically described with reference to FIG. In the stacked DRAM structure, as shown in FIG. 17, BPSG flowing on the silicon substrate 1 by heat treatment at a low temperature is used.
A film 52, a capacitor electrode 54 including a contact portion 53 connected to an impurity diffusion layer in the silicon substrate 1, a silicon oxynitride film 55 functioning as a capacitor insulating film, and a plate electrode 56 are provided. In the structure having such a structure, the silicon oxynitride film 55 as a capacitance insulating film exists on a part of the BPSG film 52.

In the stacked DRAM structure,
A structure in which a cylindrical capacitor electrode is provided to increase the surface area of the capacitor electrode has also been proposed.

In this case, as shown in FIG. 18, a silicon substrate 1 and BPSG flowing by heat treatment at a low temperature are used.
A film 57, a silicon nitride film 58 as a wet etching stopper, and a cylindrical capacitor electrode 60 including a contact portion 59 and connected to an impurity diffusion layer in the silicon substrate 1.
And a silicon oxynitride film 61 functioning as a capacitive insulating film
And a plate electrode 62. Even in the structure having such a structure, the silicon oxynitride film 61 as a capacitive insulating film exists on a part of the BPSG film 57.

[0008]

However, the above-mentioned conventional semiconductor device has the following problems.

Recently, the demand for lowering the heat treatment temperature of the BPSG film has arisen with the demand for lowering the temperature of the semiconductor device manufacturing process. Therefore, in order to obtain the same flow shape as before even when the temperature is lowered, the concentration of boron and phosphorus in the BPSG film is increased. When such a high-concentration BPSG film is used, FIG.
In the step of depositing and oxidizing the silicon nitride film to form the silicon oxynitride films 55 and 61 shown in FIG. 18, the first BPSG film 63 is formed as shown in FIG.
Flow easily, and the silicon nitride film 64 may be wrinkled. The inventor of the present invention has experimentally confirmed that the wrinkles tend to occur in a wide area where the memory cells are not densely packed, and that they tend to occur in a place where there is a step in the underlying first BPSG film 63. I found it. However, the silicon nitride film 64 as a capacitance insulating film
It was also found that wrinkling was more likely to occur as the thickness became thinner.

As a result of examining the cause, it was presumed to be due to the following effects. In general, it is known that a silicon oxide film such as a BPSG film and a silicon nitride film have different coefficients of thermal expansion, crystallographic structures, and the like. Therefore, it is known that when they are laminated, a high stress is generated at the interface between them. . In reality, the silicon nitride film is being pulled by the thick BPSG film. Therefore, when the BPSG film flows, the BPSG film which has been acting on the silicon nitride film until then is
Since the tensile stress by the G film is released, the silicon nitride film tries to shrink. As a result, it is considered that wrinkles and cracks occur in the silicon nitride film.

Further investigations show that when the silicon nitride film is thick, especially when the cylindrical capacitor electrode 60 shown in FIG. 18 is formed and the silicon nitride film 58 is used as a wet etching stopper, 19 (B)
As shown in FIG. 7, cracks may occur in the silicon nitride film 66.

Further, even in the case where the silicon nitride film 50 as shown in FIG. 16 is provided, in the heat treatment step for planarizing the second BPSG film 51, the first BPSG film 51 is partially formed.
It has been found that the G film 48 may be fluidized and the wrinkles and cracks of the silicon nitride film may occur as described above. This is presumably because the presence of the silicon nitride film 51 does not completely block the passage of water vapor downward, but rather a certain amount of gas such as water vapor passes through the silicon nitride film.

In the prior art, however, various processes are performed so that the semiconductor substrate must be kept at a high temperature in a process after the interlayer insulating film such as a BPSG film having the property of being flattened by heat treatment is flattened. For example, when heat treatment or thermal oxidation treatment for planarizing the upper interlayer insulating film is performed, it is difficult to prevent wrinkles, cracks, and the like of the silicon nitride film from being generated even in a part.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a BP doped with a high concentration of impurities.
When an SG film or the like is used, a semiconductor device capable of preventing wrinkles or cracks in a silicon nitride film even when a flow of the BPSG film occurs to some extent when a process involving high-temperature holding in a later process is required, and manufacturing thereof It provides a method.

[0015]

A first semiconductor device according to the present invention is provided.
The device is formed on a substrate having a semiconductor region, a first insulating film formed on the semiconductor region and having a characteristic of flowing by heat treatment under predetermined conditions, and formed on the first insulating film ; A film containing at least silicon nitride or silicon
A second insulating film made of any of a silicon nitride oxide film ;
It is formed above the first insulating film, and is formed under the predetermined condition.
Insulating film having the property of flowing due to heat treatment in the third insulating film
And an interposition between the first insulating film and the second insulating film.
And a supporting film having a function of giving a stress against the deformation of the second insulating film due to the heat treatment to the second insulating film.

Thus, when a semiconductor device is formed,
Even after the second insulating film is formed, even if the lower first insulating film may flow due to heat treatment under predetermined conditions, a stress against deformation is given to the second insulating film by the support film. In addition, no wrinkles or cracks occur in the second insulating film. Therefore, occurrence of a defect due to wrinkles or cracks in the second insulating film can be prevented, and the yield and reliability of the semiconductor device are improved. In addition, since the first insulating film can be planarized at a low temperature, the performance of the semiconductor device can be improved.

Further , it is possible to prevent the deformation of the second insulating film during the second heat treatment for fluidizing the third insulating film.

Since the support film is patterned so as to occupy at least a region including the formation region of the second insulating film on a common projection plane, the formation region of the support film is kept in a narrow range. Deformation of the second insulating film can be prevented.

According to a second aspect of the present invention, there is provided a semiconductor device comprising: a gate electrode formed on a semiconductor region; and an impurity diffusion layer formed in a region of the semiconductor region located on a side of the gate electrode. An interlayer insulating film formed on the gate electrode and the semiconductor region; a capacitor electrode that fills an opening formed in the interlayer insulating film and extends over a part of the interlayer insulating film; the interlayer and the capacitor insulating film formed over the insulating film, a stacked DRAM cell and a plate electrode formed so as to face the capacitor electrodes through the capacitor insulating film and said semiconductor
A substrate having a region, formed on the semiconductor region,
Has the property of flowing due to heat treatment under specified conditions
A first insulating film, formed on the first insulating film;
At least a film containing silicon nitride or a silicon oxynitride film
A second insulating film made of any one of the above, and the first insulating film
Between the first insulating film and the second insulating film.
Stress against the deformation of the second insulating film,
A support film having a function of providing an edge film, wherein the first insulating film is the interlayer insulating film, the second insulating film is the capacitor insulating film, and the support film is the interlayer insulating film. An insulating film interposed between the insulating film and the capacitor insulating film.

As a result, the function of the first semiconductor device can be obtained in the stacked DRAM cell, so that a stacked DRAM cell having high performance without wrinkles and cracks in the capacitance insulating film and high reliability can be obtained.

In the case where the capacitor electrode is a cylindrical capacitor electrode, the capacitor electrode is interposed below the capacitor electrode and the capacitor insulating film on the support film to form an etching stopper film when the cylindrical capacitor electrode is formed. more and this further comprising a,
It is possible to obtain a cylindrical stack type DRAM cell having high performance and high reliability without wrinkles and cracks in the capacitance insulating film.

The lower surface of the cylindrical portion of the cylindrical capacitor electrode is separated from the upper surface of the etching stopper film,
The capacitor insulating film, is formed along the surface between the cylindrical capacitor electrode and the etching stopper film Ri by <br/> in the Okuko, since the total area of the capacitor insulating film becomes wider, the dielectric breakdown voltage A cylindrical stacked DRAM cell having a good refresh characteristic can be obtained without lowering.

[0023] The etching stopper film is more that it is a silicon nitride film, a silicon nitride film by utilizing the etching selectivity with respect to both the polysilicon film and the silicon oxide film is large, low is easy to manufacture A semiconductor device with low cost can be obtained.

[0024] and the capacitor electrode a cylindrical capacitor electrode, the supporting film, constituted by a TEOS film, and more and this function as an etching stopper film when forming a cylindrical capacitor electrode, a TEOS film is a polysilicon film And BP
By utilizing the fact that the etching selectivity is high with respect to both of the SG films, a semiconductor device which is easy to manufacture and can be manufactured at low cost can be obtained.

[0025] More and child composed of silicon oxide film the supporting film, it easy to form a silicon oxide film, by using, for example it does not adversely affect the properties of the semiconductor device, a high performance and reliability A semiconductor device can be obtained at low cost.

[0026] More and child composed of the second insulating film a silicon nitride oxide film, in the manufacture of semiconductor devices, a silicon nitride film by oxidizing the silicon nitride oxide film constituting the second insulating film Since wrinkles and the like do not occur in the second insulating film even when the formation process is performed, a semiconductor device with good flatness and high performance and reliability as a whole semiconductor device can be obtained. In particular, when the capacitor insulating film of the DRAM cell is formed of a silicon nitride oxide film, a capacitor insulating film having good dielectric properties and good compatibility with the plate electrode can be obtained, so that the performance of the semiconductor device is improved.

According to a third aspect of the present invention, there is provided a semiconductor device comprising: a gate electrode formed on a semiconductor region; and an impurity diffusion layer formed in a region of the semiconductor region which is located on a side of the gate electrode. An interlayer insulating film formed on the gate electrode and the semiconductor region; a capacitor electrode that fills an opening formed in the interlayer insulating film and extends over a part of the interlayer insulating film; the interlayer and the capacitor insulating film formed over the insulating film, a stacked DRAM cell and a plate electrode formed so as to face the capacitor electrodes through the capacitor insulating film and said semiconductor
A substrate having a region, formed on the semiconductor region,
Has the property of flowing due to heat treatment under specified conditions
A first insulating film, formed on the first insulating film;
At least a film containing silicon nitride or a silicon oxynitride film
A second insulating film made of any one of the above, and the second insulating film
On the second insulating film formed by the heat treatment.
It has a function of applying a stress against deformation to the second insulating film.
And a supporting film formed above the first insulating film.
Has the property of flowing due to heat treatment under the specified conditions
A third insulating film, wherein the supporting film has a common projection plane.
The region including the region where the second insulating film is formed is reduced
It is patterned so that it occupies at least
The area other than below the coated support film is the second
Is not present, the first insulating film is the interlayer insulating film, the second insulating film is the capacitive insulating film, and the support film is the plate electrode.

Thus, even if a support film is not separately provided,
The plate electrode has a structure capable of preventing deformation of the capacitor insulating film during heat treatment.

[0029] The capacitive insulating film is formed of a silicon nitride oxide film formed by oxidizing the silicon nitride film, the interlayer insulating film does not flow by a heat treatment at the time of oxidizing the silicon nitride oxide film Preferably, it has properties.

The performance with the first insulating film more and configuration child by BPSG film, BPSG film by utilizing the fact that have the property of flowing at low temperatures, more flatness good first insulating film And a highly reliable semiconductor device can be obtained.

The first method of manufacturing a semiconductor device according to the present invention comprises:
Performing a first step of depositing a first insulating film having a property of flowing on a semiconductor substrate by heat treatment under predetermined conditions and a first heat treatment under the predetermined conditions;
A second step of flattening by flowing the first insulating film, over the first insulating film, the third forming the support film having a characteristic that does not flow by heat treatment in the predetermined conditions Process and silicon nitride on the support film.
Or a silicon nitride oxide film
A fourth step of forming a second insulating film;
A fifth step of depositing a third insulating film having a property of flowing by heat treatment under the above predetermined conditions on the film ;
Performing a second heat treatment under the predetermined condition to flow and planarize the third insulating film. In the sixth step, the second film is formed by the support film by the second film. In this method, a stress against deformation of the insulating film is applied to the second insulating film.

According to this method, when the first insulating film flows at least partially during the heat treatment under the predetermined condition, the second insulating film including the silicon nitride film or the silicon nitride oxide film is formed .
When the stress that has been acting on the first insulating film is released, the second insulating film attempts to deform. At this time, since a stress against the deformation of the second insulating film is applied by the support film, wrinkles and cracks do not occur in the second insulating film. Therefore, a semiconductor device with high performance and high reliability can be formed.

After the fourth step and before the fifth step, the support film is formed so as to occupy at least a region including a formation region of the second insulating film on a common projection plane. The method may further include a step of patterning the second insulating film and the support film.

According to this method, since the supporting film always exists in the portion where the second insulating film exists, the deformation of the second insulating film during the manufacturing process can be surely prevented. Become.

The second insulating film in the fourth step
In the forming process, a silicon nitride film is formed on the support film.
After form, perform the third heat treatment in the given conditions, to oxidize the surface of the silicon nitride film further comprises a step of forming a silicon nitride oxide film, in the step of performing the third heat treatment, the With the support film, a stress against the deformation of the second insulating film can be applied to the second insulating film.

According to this method, even when a heat treatment is performed under predetermined conditions in the step of flattening the third insulating film, wrinkles and cracks are generated in the second insulating film by the function of the above-mentioned supporting film. There is no. Therefore, a semiconductor device with high performance and high reliability can be formed.

According to a second method of manufacturing a semiconductor device of the present invention,
Manufacturing of semiconductor devices that function as stacked DRAM cells
Manufacturing method, on a semiconductor substrate, under predetermined conditions
Depositing a first insulating film having a property of flowing by heat treatment
A first heat treatment under the predetermined conditions.
The first insulating film is flowed and planarized by
A second process, and a silicon nitride film on the first insulating film.
Film containing silicon or silicon oxynitride film
A third step of forming a second insulating film,
Depending on the heat treatment under the above predetermined conditions,
Fourth Step of Forming Support Film Having Non-Flowing Characteristics
After the fourth step, on the substrate under the predetermined condition
Insulation having characteristics of flowing by heat treatment in
A fifth step of depositing a film;
Heat treatment 2 to flow the third insulating film,
After the sixth step of flattening and the fourth step,
Before the fifth step, the supporting film is placed on a common projection plane.
And at least a region including a region where the second insulating film is formed is reduced.
So that the second insulating film and the supporting film are the same.
Sometimes, the capacitor is patterned by the second insulating film.
Forming a plate electrode consisting of an insulating film and the above supporting film
In the patterning step, the patterned
In the area other than below the plate electrode, the second
The second insulating film is removed so that the insulating film does not exist.
In the sixth step, the plate electrode
The stress against the deformation of the capacitive insulating film
This is a method of giving a film.

According to a third method of manufacturing a semiconductor device of the present invention ,
A method of manufacturing a semiconductor device that functions as a stack-type DRAM cell, on a semiconductor substrate having an impurity diffusion layer, a first depositing a first insulating film having the property of flowing through the heat treatment in predetermined conditions A step of performing a first heat treatment under the above-described predetermined conditions to flow and planarize the first insulating film, and a heat treatment under the above-mentioned predetermined conditions after the second step. A third step of forming a support film having a property of not flowing, a fourth step of forming a contact hole reaching the impurity diffusion layer in the support film and the first insulating film, and including the contact hole A fifth step of depositing a first capacitor electrode conductor film on a substrate, and patterning the first capacitor electrode conductor film to form a capacitor electrode connected to the impurity diffusion layer; Step 7 and after the sixth step, depositing a second insulating film made of a silicon nitride film along the surface of the capacitor electrode and the exposed surface of the support film. Performing a second heat treatment under the predetermined condition after the step and the seventh step, thereby oxidizing a surface of the second insulating film to form a capacitive insulating film made of a silicon nitride oxide film. And a ninth step of forming a plate electrode conductive film on the substrate after the eighth step. In the eighth step, the second heat treatment is performed by the second heat treatment using the support film. In this method, a stress against the deformation of the second insulating film is applied to the second insulating film.

According to this method, there is a possibility that the first insulating film flows when the silicon nitride film is thermally oxidized in the step of forming the silicon nitride oxide film constituting the capacitive insulating film of the stacked DRAM cell. At that time, since the support film is interposed between the silicon nitride film and the first insulating film,
No wrinkles or cracks occur in the silicon nitride film. Therefore, a highly reliable stacked DRAM cell having good memory characteristics can be formed.

After the ninth step, a step of forming a third insulating film having a property of flowing on the substrate by the heat treatment under the above-mentioned predetermined condition, and then, a third heat treatment under the above-mentioned predetermined condition And flattening the third insulating film by fluidizing the third insulating film. In the flattening step, the supporting film prevents the second insulating film from being deformed by the third heat treatment. the stress more and this given to the second insulating film, even when the fluidizing the third insulating film, it is possible to reliably prevent deformation of the capacitor insulating film.

In the third step, a support film made of a TEOS film is formed, and after the fifth step and before the sixth step, a BPSG film is formed on the first capacitor electrode conductor film. Forming a core of a cylindrical capacitor electrode made of a film, and subsequently forming a second conductive film for a capacitor electrode on a substrate including on the core of the cylindrical capacitor electrode, In a sixth step, the first and second conductive films for a capacitor electrode are patterned to form a cylindrical capacitor electrode composed of the first and second conductive films for a capacitor electrode. After the step (c) and before the seventh step, the method further comprises the step of removing the nucleus of the cylindrical capacity electrode by etching, and removing the support film from the sixth step and the nucleus of the cylindrical capacity electrode. more and this function as an etching stopper film in a step TEOS film is a polysilicon film and B
Utilizing the fact that the etching selectivity with respect to the PSG film is high, the capacitance insulating film formed by the heat treatment under a predetermined condition can be formed while forming the cylindrical capacitance electrode without providing a step of separately forming a film dedicated to the etching stopper. Can be prevented from being deformed.

After the third step and before the fourth step, a step of forming a gap-forming film on the support film is further provided. In the fourth step, the gap-forming film is formed. In the step of removing the nucleus of the cylindrical capacitor electrode, the contact hole is also formed so as to penetrate the cylindrical capacitor electrode, and the gap forming film is also removed to form the gap forming film in the cylindrical capacitor electrode. The contacted surface is exposed, and in the seventh step, the second insulating film is deposited along the exposed surface of the cylindrical capacitor electrode and the exposed surface of the support film. more and child, insulation without reducing the breakdown voltage, with long retention time it is possible to form a good cylindrical stacked DRAM cell, such as a refresh characteristics.

After the second step and before the third step, the method further comprises the step of depositing an edge-holding insulating film having a high etching selectivity with respect to the first insulating film on the substrate. in a third step, the child form the contact hole to also penetrate the edge retaining insulating film
More, in the step of forming a contact hole, it is possible to reliably prevent the size of the contact hole will be enlarged broken edge of the contact hole.

According to a fourth method of manufacturing a semiconductor device of the present invention ,
A method of manufacturing a semiconductor device that functions as a circularly cylindrical stack DRAM cells, on a semiconductor substrate having an impurity diffusion layer, the depositing a first insulating film having the property of flowing through the heat treatment in predetermined conditions 1 Performing a first heat treatment under the predetermined conditions to flow the first insulating film and planarize the first insulating film;
A third step of forming a support film having a property of not flowing due to heat treatment under the above-mentioned predetermined conditions after the step of;
A fourth step of forming an etching stopper film at the time of forming the cylindrical capacitor electrode on the support film; and a contact hole reaching the impurity diffusion layer in the etching stopper film, the support film, and the first insulating film. Forming a first conductive film for a capacitor electrode on the substrate including the contact hole, and forming the first conductive film for the first capacitor electrode after the sixth process. A seventh step of forming a core of the cylindrical capacitor electrode on the conductive film; and after the seventh step, a second step is performed on a substrate including the core of the cylindrical capacitor electrode.
An eighth step of forming the capacitor electrode conductive film,
A ninth step of patterning the second conductive film for a capacitor electrode and the second conductive film for a capacitor electrode to form a cylindrical capacitor electrode composed of the first and second conductive films for a capacitor electrode; and etching after the ninth step. To remove the core of the cylindrical capacitor electrode
After the step 0 and the tenth step, a second insulating film made of a silicon nitride film is deposited along the surface of the cylindrical capacitor electrode and the exposed surface of the support film. After the eleventh step and the eleventh step, a second heat treatment is performed under the above-mentioned predetermined condition, whereby the second heat treatment is performed.
A twelfth step of oxidizing the surface of the insulating film to form a capacitive insulating film made of a silicon oxynitride film, and a thirteenth step of forming a plate electrode conductor film on the substrate after the twelfth step The twelfth step is a method in which the supporting film applies a stress against both the deformation of the second insulating film and the etching stopper film by the second heat treatment to the both.

According to this method, a cylindrical stack type DRAM is used.
In the step of forming the silicon oxynitride film forming the capacitor insulating film of the cell, wrinkles and cracks are formed in the silicon nitride film serving as the etching stopper film and the capacitor insulating film by the same operation as the above-described method for manufacturing the second semiconductor device. Does not occur. Therefore, the cylindrical capacitor electrode can be easily formed due to the presence of the etching stopper film, and the cylindrical stack type DRAM having good memory characteristics and high reliability is provided.
Cells can be formed.

After the thirteenth step, a step of forming a third insulating film having a property of flowing on the substrate by the heat treatment under the above-mentioned predetermined condition, followed by a third heat treatment under the above-mentioned predetermined condition And fluidizing and planarizing the third insulating film.
In the step of flattening the insulating film, the support film can apply to both the stress against the deformation of the second insulating film and the etching stopper film due to the third heat treatment.

The method further comprises forming a gap forming film on the etching stopper film. In the fifth step, the contact hole is formed so as to penetrate the gap forming film, and the cylindrical shape is formed. In the step of removing the nucleus of the capacitor electrode, the gap forming film is also removed to expose a surface of the cylindrical capacitor electrode that is in contact with the gap forming film. In the eleventh step, The second insulating film can be deposited along the exposed surface of the cylindrical capacitor electrode and the exposed surface of the support film.

After the second step and before the third step, the method further comprises the step of depositing an edge-holding insulating film having a high etching selectivity with respect to the first insulating film on the substrate. In the fifth step, the contact hole can be formed so as to penetrate the edge holding insulating film.

According to a fifth method of manufacturing a semiconductor device of the present invention ,
A first step of depositing a first insulating film having a property of flowing by heat treatment under predetermined conditions on a semiconductor substrate having an impurity diffusion layer;
A second process of flowing the first insulating film to make it flat by performing the heat treatment described above, and depositing a second insulating film made of a silicon nitride film on the substrate after the second process. A third heat treatment is performed after the third step and under the condition that the first insulating film does not flow, so that the surface of the second insulating film is oxidized to perform silicon nitride oxidation. Forming a capacitive insulating film made of a film.

According to this method, since the first insulating film does not flow in the step of thermally oxidizing the silicon nitride film, wrinkles and cracks of the silicon nitride film during thermal oxidation can be eliminated without providing a support film separately. It can be reliably prevented.

In the first step, the fluidizing temperature is 8
A first insulating film composed of a BPSG film at 30 ° C. or higher is deposited, and in the fourth step, thermal oxidation can be performed at a temperature of 820 ° C. or lower.

In the first step, B containing 2.0 to 6.0% by weight of phosphorus and 1.0 to 4.0% by weight of boron
A first insulating film made of a PSG film can be deposited.

[0053] In the fourth step, more and this performing thermal oxidation under a dry atmosphere, by utilizing the fact that the first insulating film is less likely to flow than in the case of Pyro atmosphere in the case of a dry atmosphere Even when the temperature of the thermal oxidation step is increased, the flow of the first insulating film can be reliably prevented.

[0054] Prior to the third step, and this further comprising a step of nitriding the exposed surface of the first insulating film
More nitride start timing for forming the silicon nitride film on the first insulating film is faster, the thickness of the silicon nitride film is increased. Therefore, the amount of oxygen and the like passing through the silicon nitride film in the subsequent process involving high-temperature holding is reduced, and the first insulating film becomes less likely to flow, so that a stacked DRAM cell having a wrinkle-free or crack-free capacitive insulating film. Can be formed.

In the nitriding step, it is preferable to perform a heat treatment in a nitrogen or ammonia atmosphere.

After the second step and before the third step, a step of forming a contact hole reaching the impurity diffusion layer in the first insulating film; Depositing a conductive film for a capacitor electrode, and patterning the conductive film for a capacitor electrode to form a capacitor electrode connected to the impurity diffusion layer. Depositing the second insulating film on the substrate including the surface of the capacitor electrode, and forming a plate electrode conductor film on the substrate after the fourth step;
Patterning the plate electrode conductive film and the second insulating film;
To form a plate electrode and a capacitive insulating film
And an area other than below the plate electrode.
The pass more that there are no the capacitor insulating film, together with the thermal oxidation process for forming a capacitor insulating film made of a silicon nitride oxide film even without the support film can be smoothly carried out, followed by When flattening the upper interlayer insulating film and the like, the plate electrode can be used as a supporting film for the capacitive insulating film.

A cylindrical capacitor electrode can be formed as the capacitor electrode.

[0058]

(First Embodiment) FIG. 1 is a sectional view showing a part of a semiconductor device according to a first embodiment. For simplicity, FIG. 1 shows only the step of the gate electrode, but the semiconductor device of the present embodiment has a LOC
This is a semiconductor device in which a plurality of steps such as a step due to OS isolation and a step due to a gate electrode are formed. This semiconductor device includes a silicon substrate 1, a gate electrode 2 as a first wiring layer, and a first BPSG as a first insulating film (lower interlayer insulating film) having a property of flowing by heat treatment under predetermined conditions. (Boro-Phosph-Silicate
Glass film 3, a polycide wiring 4 as a second wiring layer composed of a laminated film of a silicide film and a polysilicon film, and a support film having a property that the first BPSG film 3 does not flow under the above-mentioned predetermined conditions. A silicon oxide film 5, a silicon nitride film 6 as a second insulating film, and a second BPSG film 7 as a third insulating film (upper interlayer insulating film) flowing by the heat treatment under the above-mentioned predetermined conditions. Have.

Next, a method of manufacturing the semiconductor device having the structure shown in FIG. 1 will be described with reference to FIGS.

First, in the step shown in FIG. 2A, a gate electrode 2 is formed on a silicon substrate 1, and then a first BPSG film 3 is deposited on the substrate. At this time, the first B
The impurity concentration in the PSG film 3 is such that the phosphorus concentration is 3.0 wt%.
As described above, the boron concentration is 3.0% by weight or more. Further, it is preferable that the thickness of the first BPSG film 3 be twice or more the thickness of the gate electrode 2. In that case, the flatness of the first BPSG film 3 by the subsequent heat treatment is improved.

Next, in the step shown in FIG. 2B, a heat treatment for flattening the first BPSG film 3 is performed. For example,
The first BPSG film 3 is planarized by performing a heat treatment at 850 ° C. in a nitrogen atmosphere for 30 minutes. When the atmosphere during the heat treatment is an oxidizing atmosphere, the same flatness can be obtained even when the heat treatment temperature is set to 800 ° C. However, in that case, a nitride film as an antioxidant film is required under the first BPSG film 3.

Next, as shown in FIG. 2C, a polycide wiring 4 as a second wiring layer is formed. After that, a silicon oxide film 5 and a silicon nitride film 6 as support films are deposited on the substrate. At this time, the thickness of the silicon oxide film 5 is 50 nm, and the thickness of the silicon nitride film 6 is 50 n.
m. Note that the second wiring layer does not necessarily need to be formed of a polycide film, and if the film is sufficiently resistant to a heat treatment for flattening the first BPSG film 3, it may be formed of polysilicon. It may be a film or a silicide film.

Next, in the step shown in FIG. 2D, a second BPS as a third insulating film (upper interlayer insulating film) is formed on the substrate.
A G film 7 is deposited. At this time, the addition amount of impurities in the second BPSG film 7 is such that the phosphorus concentration is 3.0 wt% or more and the boron concentration is 3.0 wt% or more. Also, the second BPS
It is preferable that the thickness of the G film 7 be twice or more the thickness of the polycide wiring 4. As described above, the flatness of the second BPSG film 7 is improved by the subsequent heat treatment. Then, a heat treatment for planarization is performed with the second BPSG film 7 deposited. For example, 85
By performing a heat treatment for 30 minutes in an oxidizing atmosphere at 0 ° C.,
The second BPSG film 7 is flattened. After that, desired wiring is performed by a general process to complete the semiconductor device shown in FIG.

In this embodiment, in the step of flattening the second BPSG film 7 by heat treatment, even if the already flattened first BPSG film 3 flows, the silicon nitride film 6 and the first BPSG film A silicon oxide film 5 which does not flow due to the heat treatment at this temperature is interposed between the film 3 and the film 3.
The silicon oxide film 5 applies a stress against the shrinkage of the silicon nitride film 6, that is, a tensile stress to the silicon nitride film 6. As described above, in the conventional structure, when the lower BPSG film flows,
Since the tensile stress acting on the silicon nitride film until then is released, the silicon nitride film contracts, resulting in wrinkles and cracks in the silicon nitride film. On the other hand, in the case of the present embodiment, since a stress against shrinkage of the silicon nitride film 6 is given to the silicon nitride film 6 by the silicon oxide film 5, cracks or wrinkles are generated in the silicon nitride film 6. Can be reliably prevented.

Also, the presence of the silicon nitride film 6 that prevents the passage of oxygen allows the polycide wiring 4 to be formed even in an oxidizing atmosphere.
Since the gate electrode 2 is not oxidized, heat treatment for planarization can be performed in an oxidizing atmosphere. That is, the heat treatment for planarization can be performed at a lower temperature than the heat treatment in a nitrogen atmosphere, so that a high-performance and highly reliable device can be obtained.

Here, in the present embodiment, the lower interlayer insulating film as the first insulating film has a phosphorus concentration of 3.0 wt% or more.
Although the BPSG film having a boron concentration of 3.0 wt% or more was formed, the material forming the lower interlayer insulating film is not limited to this embodiment, and another material having the same fluidity in the heat treatment step. Even if the lower interlayer insulating film is configured by, the silicon oxide film is interposed between the silicon nitride film and the lower interlayer insulating film,
As in the present embodiment, the effect of preventing cracks or wrinkles in the silicon nitride film can be exhibited.

In the present embodiment, it is important that the thickness of the silicon oxide film 5 is set so that cracks or wrinkles do not occur in the silicon nitride film 6.
It depends on the impurity concentration in the first BPSG film 3, that is, the flow temperature, the thickness of the silicon nitride film 6, and the heat treatment conditions after the formation of the silicon nitride film 6. The lower the impurity concentration in the first BPSG film 3 and the lower the heat treatment temperature in the step after the formation of the silicon nitride film 6, that is, the lower the first BPSG film 3,
The thickness of the silicon oxide film 5 can be made thinner so that the flow of the first BPSG film 3 is less likely to flow. Conversely, the thickness of the silicon oxide film 5 needs to be thicker under the condition that the first BPSG film 3 easily flows.
Further, as the thickness of the silicon nitride film 6 increases, the stress generated in the silicon nitride film 6 also increases.
Need to be thick.

The thickness of the silicon nitride film 6 is determined by the heat treatment in an oxidizing atmosphere in a later step.
Alternatively, it may be in a range where the polycide wiring 4 is not oxidized.

In the present embodiment, the supporting film interposed between the lower interlayer insulating film and the silicon nitride film is constituted by a silicon oxide film, but the present invention is not limited to such an embodiment. That is, the support film of the present invention may be any film as long as it has a function of giving a stress against the contraction of the nitride film, that is, a tensile stress, to the nitride film. However, specifically, it is preferable that the support film of the present invention is made of a material having a thermal expansion coefficient and a crystallographic structure close to that of the BPSG film and giving the same stress to the nitride film as the BPSG film. .

In this embodiment, the heat treatment after forming the silicon nitride film is performed at 850 ° C. in an oxidizing atmosphere.
Although the heat treatment is performed for 0 minutes, the effect of the present invention can be obtained even when the heat treatment is performed at a temperature lower than this temperature as long as the lower interlayer insulating film flows. However, when the heat treatment at a higher temperature is performed, the effect of the present invention appears more remarkably.

In this embodiment, the case where the first insulating film is the first interlayer insulating film on the semiconductor substrate has been described, but the present invention is not limited to such an embodiment. The present invention is generally applied to a semiconductor device having a multilayer wiring structure in which the first insulating film is a second or third interlayer insulating film.

(Second Embodiment) FIG. 3 is a sectional view of a stacked DRAM cell which is a semiconductor device according to a second embodiment. In FIG. 3, the gate electrode and the LOCO
Illustration of S separation and bit lines is omitted. This semiconductor device comprises a silicon substrate 1 and a BPSG film 8 as a first insulating film flowing by heat treatment under predetermined conditions.
A silicon oxide film 9 serving as a support film for applying a stress against deformation of the nitride film without flowing in the heat treatment under the above-mentioned predetermined conditions, and a capacitor electrode including a contact portion 10 connected to an active region in the silicon substrate 12 and a silicon oxynitride film 1 as a second insulating film functioning as a capacitive insulating film
4 and a plate electrode 15.

Next, a method of manufacturing the semiconductor device shown in FIG. 3 will be described with reference to FIGS.
However, in FIGS. 4A and 4B, the gate electrode, the LOCOS isolation, and the bit line are not shown for easy understanding of the characteristic portion.

In the step shown in FIG. 4A, the first flow, which flows on the silicon substrate 1 by heat treatment under predetermined conditions, is performed.
A BPSG film 8 is deposited as an insulating film. At this time, B
The impurity concentration in the PSG film 8 is such that the phosphorus concentration is 3.0 wt%.
As described above, the boron concentration is 3.0% by weight or more. Next, B
Heat treatment for planarizing the PSG film 8 is performed. For example,
By performing a heat treatment at 850 ° C. in a nitrogen atmosphere for 30 minutes, the BPSG film 8 is planarized. Thereafter, a silicon oxide film 9 is deposited on the BPSG film 8 as a support film which does not flow due to the heat treatment under the above-mentioned predetermined conditions. next,
After opening a contact hole for a capacitor electrode in the silicon oxide film 9 and the BPSG film 8, polysilicon is deposited on the substrate including the contact hole, and the contact portion 10 and the polysilicon film 11 on the silicon oxide film 9 are separated. Form. Normally, N-type impurities are added to this polysilicon.

In the step shown in FIG. 4B, the capacitor electrode 12 integrated with the contact portion 10 is formed by etching the polysilicon film 11 into a desired pattern.
Next, a silicon nitride film 13 is deposited on the substrate to a thickness of about 8 nm.

Although illustration of subsequent steps is omitted, the silicon nitride film 13 is oxidized to form the silicon nitride oxide film 14 shown in FIG. The oxidation conditions at that time are, for example, a temperature of 850 ° C. in a dry oxidation atmosphere.
And the time is 30 minutes. After that, a general process is performed to form the plate electrode 15 shown in FIG. 3 and perform desired wiring, thereby completing the semiconductor device. Generally, an upper interlayer insulating film having a property of flowing by heat treatment, that is, a second interlayer insulating film, a third interlayer insulating film, and the like are further formed thereon.

In the present embodiment, a silicon oxide film which does not flow between the silicon nitride film 13 and the BPSG film 8 shown in FIG. Since the silicon nitride film 9 is interposed, even if the BPSG film 8 flows in the process of forming the silicon nitride oxide film 14 by thermally oxidizing the silicon nitride film 13, cracks or wrinkles occur in the formed silicon nitride oxide film 14. do not do.

In this embodiment, the lower interlayer insulating film as the first insulating film has a phosphorus concentration of 3.0 wt% or more.
Although the BPSG film having a boron concentration of 3.0 wt% or more was formed, the material forming the lower interlayer insulating film is not limited to this embodiment, and another material having the same fluidity in the heat treatment step. Even if the lower interlayer insulating film is configured by, the silicon oxide film is interposed between the silicon nitride film and the lower interlayer insulating film,
As in the present embodiment, the effect of preventing cracks or wrinkles in the silicon oxynitride film can be exhibited.

In the present embodiment, it is important that the thickness of the silicon oxide film 9 is set so as not to cause cracks or wrinkles in the silicon nitride oxide film 14, and the value is determined by the impurity concentration in the BPSG film 8. , Silicon nitride film 1
3 and the oxidation conditions after the formation of the silicon nitride film 13. The lower the impurity concentration in the BPSG film 8 and the lower the oxidation temperature after the formation of the silicon nitride film 13, that is, the more difficult the BPSG film 8 is to flow, the thinner the silicon oxide film 9 can be. In a case where the silicon oxide film 9 easily flows, it is necessary to make the silicon oxide film 9 thick. Further, as the thickness of the silicon nitride film 13 increases, the stress generated in the silicon nitride film 13 also increases, so that the thickness of the silicon oxide film 9 needs to be increased.

The thickness of the silicon nitride film 13 may be within a range that does not oxidize the underlying capacitor electrode 12 during the oxidation process in the subsequent step.

In the present embodiment, the supporting film interposed between the lower interlayer insulating film and the silicon nitride film is constituted by the silicon oxide film. However, the present invention is not limited to such an embodiment. The object of the present invention can be achieved even if any material is used as long as it does not flow in a heat treatment step under predetermined conditions and gives a stress against deformation of the nitride film.

In this embodiment, the silicon nitride film 1
Oxidation conditions of 3 are 850 ° C., 30 min.
Although the oxidation treatment was performed for a minute, the effect of the present invention can be obtained even under a condition lower in temperature than the condition in the present embodiment as long as the condition is such that the lower interlayer insulating film flows. Further, when the oxidation treatment is performed at a higher temperature, the effect of the present invention is more remarkably exhibited.

Third Embodiment FIG. 5 is a sectional view of a cylindrical stacked DRAM cell which is a semiconductor device according to a third embodiment. In FIG. 5, the gate electrode,
LOCOS isolation and bit lines are not shown. This semiconductor device comprises a silicon substrate 1 and a first insulating film B which flows by heat treatment under predetermined conditions.
A PSG film 16, a silicon oxide film 17 as a support film that does not flow by the heat treatment under the above-mentioned predetermined conditions, a silicon nitride film 18 as a wet etching stopper film when forming a cylindrical stack cell, and an active region in the silicon substrate. A cylindrical capacitor electrode 24 including a contact portion 19 connected to the region, a silicon oxynitride film 23x as a second insulating film functioning as a capacitor insulating film, and a plate electrode 25 are provided.

Next, a method of manufacturing the semiconductor device shown in FIG. 5 will be described with reference to FIGS.
However, in FIGS. 6A to 6D, the gate electrode, the LOCOS isolation, and the bit line are not shown for easy understanding of the characteristic portion.

In the step shown in FIG. 6A, the first fluid flowing on the silicon substrate 1 by heat treatment under predetermined conditions is formed.
A BPSG film 16 is deposited as an insulating film. At this time,
The impurity concentration in the BPSG film 16 is such that the phosphorus concentration is 3.0 w
t% or more, and boron concentration is 3.0 wt% or more. Next, a heat treatment for planarizing the BPSG film 16 is performed.
For example, by performing a heat treatment at 850 ° C. in a nitrogen atmosphere for 30 minutes, the BPSG film 16 is planarized. afterwards,
A silicon oxide film 17 is deposited on the BPSG film 16 as a support film that does not flow due to heat treatment under predetermined conditions. Next, a silicon nitride film 18 is formed as a wet etching stopper for forming a cylindrical stack cell. Thereafter, a contact hole for a capacitor electrode is opened in the silicon nitride film 18, the silicon oxide film 17, and the BPSG film 16, and then polysilicon is deposited on the substrate including the contact hole. A polysilicon film 20 is formed. afterwards,
A silicon oxide film 21 is formed on the polysilicon film 20.

In the step shown in FIG. 6B, the silicon oxide film 21 is patterned so as to have a desired cell shape.
A polysilicon film 22 is deposited on the substrate. At this time, before depositing the polysilicon film 22, the natural oxide film formed on the polysilicon film 20 is removed.

In the step shown in FIG. 6C, the polysilicon film 22 is anisotropically etched to form the silicon oxide film 2.
The polysilicon film 22 is removed while leaving only the side surface of the polysilicon film 1,
The cylindrical capacitance electrode 24 including the contact portion 19 is formed.

In the step shown in FIG. 6D, wet etching is performed using the silicon nitride film 18 as a wet etching stopper to remove only the silicon oxide film 21. Next, a silicon nitride film 23 is deposited on the substrate, and the exposed surfaces of the silicon nitride film 18 and the cylindrical capacitor electrode 24 are covered with the silicon nitride film 23.

Although illustration of the subsequent steps is omitted, the silicon nitride film 23 is oxidized to form a silicon nitride oxide film 23x shown in FIG. Thereafter, a general process is performed to form the plate electrode 25 shown in FIG.
By performing desired wiring, a semiconductor device is completed.

In this embodiment, the silicon nitride film 18 and B
Since the silicon oxide film 17 that does not flow due to the heat treatment under the predetermined conditions and gives a stress against the deformation of the nitride film is interposed between the PSG films 16, the silicon nitride film 23 is oxidized and the silicon nitride oxide film 23 x Even if the BPSG film 16 flows in the heat treatment step for forming the silicon nitride film, no cracks or wrinkles are generated in the silicon nitride film 18 or the silicon nitride oxide film 23x.

In this embodiment, the lower interlayer insulating film as the first insulating film has a phosphorus concentration of 3.0 wt% or more.
Although the BPSG film having a boron concentration of 3.0 wt% or more was formed, the material forming the lower interlayer insulating film is not limited to this embodiment, and another material having the same fluidity in the heat treatment step. Even if the lower interlayer insulating film is configured by, the silicon oxide film is interposed between the silicon nitride film and the lower interlayer insulating film,
As in the present embodiment, the effect of preventing the generation of cracks or wrinkles in the silicon nitride film 18 or the silicon nitride oxide film 23x can be exhibited.

In this embodiment, the silicon oxide film 17
It is important to set the thickness of the BPSG film 16 so that cracks or wrinkles do not occur in the silicon nitride film 18 or the silicon nitride oxide film 23x.
And the oxidation conditions after the formation of the silicon nitride film 23. BPSG film 1
The lower the impurity concentration in the silicon nitride film 6 and the lower the oxidation temperature after the formation of the silicon nitride film 23, that is, the more difficult the BPSG film 16 is to flow, the thinner the silicon oxide film 17 can be. In the case of easy conditions, it is necessary to make the silicon oxide film 17 thick. Further, as the thickness of the silicon nitride film 18 or the silicon nitride oxide film 23x increases, the stress generated in the silicon nitride film 18 also increases. Therefore, the thickness of the silicon oxide film 17 needs to be increased.

The thickness of the silicon nitride film 18 may be in such a range that the lower BPSG film 16 is not wet-etched during the later wet etching.

In the present embodiment, the supporting film interposed between the lower interlayer insulating film and the silicon nitride film is constituted by the silicon oxide film. However, the present invention is not limited to such an embodiment. The object of the present invention can be achieved even if it is made of any other material that does not flow in a later heat treatment step and gives a stress against deformation of the nitride film.

The silicon oxide film 2 shown in FIG.
In the step of patterning the polysilicon film 1 into a desired cell shape, as shown in FIG. 7, a first modification is employed in which the polysilicon film 20 is simultaneously etched and then the polysilicon film 22 is deposited on the entire surface. You can also. However,
Also in this case, it is preferable to remove the natural oxide film formed on the polysilicon film 20 before depositing the polysilicon film 22, as in the above embodiment.

Further, after a silicon nitride film 18 as a wet etching stopper shown in FIG. 6B is formed, a second silicon oxide film 27 is formed thereon.
Can be modified. Hereinafter, FIG.
A method according to a second modification of the third embodiment will be described with reference to FIG.

First, in the step shown in FIG. 8A, a BPSG film 16 serving as a lower interlayer insulating film is formed on the silicon substrate 1.
Is deposited, the BPSG film 16 is planarized by heat treatment, and then a silicon oxide film 17 and a silicon nitride film 18 as a wet etching stopper are sequentially stacked thereon. Then, after further forming a silicon oxide film 27 on the silicon nitride film 18, the silicon oxide film 27, the silicon nitride film 18, the silicon oxide film 17, and the BPSG film 16 are formed.
After opening a contact hole for a capacitor electrode, a polysilicon film is deposited on the substrate including the contact hole, and a contact portion 19 and a polysilicon film 20 on the silicon nitride film 27 are formed. Thereafter, a silicon oxide film 21 is deposited on the polysilicon film 20.

Next, in the step shown in FIG.
As in the step shown in FIG. 1B, after patterning the silicon oxide film 21 into a desired cell shape, a polysilicon film 22 is deposited on the substrate. At this time, the polysilicon film 22
Before depositing, a native oxide film formed on the polysilicon film 20 is removed.

In the step shown in FIG. 8C, the polysilicon film 22 is anisotropically etched to form the silicon oxide film 2.
The polysilicon film 22 is removed while leaving only the side surface of the polysilicon film 1,
The cylindrical capacitance electrode 24 including the contact portion 19 is formed.

In the step shown in FIG. 8D, the silicon oxide film 21 and the silicon oxide film 27 are removed by performing wet etching using the silicon nitride film 18 as a wet etching stopper. In this state, the cylindrical capacitor electrode 2
A gap is formed between the cylindrical portion 4 and the silicon nitride film 18. Next, a silicon nitride film 23 is deposited on the substrate,
The exposed surfaces of the silicon nitride film 18 and the cylindrical capacitor electrode 24 are covered with the silicon nitride film 23.

In the step shown in FIG. 8E, the silicon nitride film 23 is oxidized to form a silicon nitride oxide film 23x. Thereafter, a general process is performed to form the plate electrode 25, and a desired wiring is performed, thereby completing the semiconductor device.

In the case of the semiconductor device having the structure of the present modified embodiment, even in the void formed below the cylindrical portion of the cylindrical capacitor electrode 24, silicon nitride oxide as a capacitor insulating film is formed on the surface of the cylindrical capacitor electrode 24. Since the film 23x is formed,
There is an effect that the area of the cell increases and the cell capacity can be increased accordingly.

(Fourth Embodiment) Next, a description will be given of a fourth embodiment relating to the structure of a stacked DRAM cell in which a nitride film is provided only below a plate electrode.

FIG. 9 is a sectional view of a stacked DRAM cell which is a semiconductor device according to the fourth embodiment. In FIG. 9, the gate electrode, the LOCOS isolation, and the bit line are not shown for easy understanding of the characteristic portion. This semiconductor device includes a silicon substrate 1, a first BPSG film 28 as a first insulating film flowing by heat treatment under predetermined conditions, and a capacitor electrode 31 including a contact portion 29 connected to an active region of the substrate. A silicon oxynitride film 33 serving as a second insulating film functioning as a capacitive insulating film, a plate electrode 34, and a second BPSG serving as a third insulating film flowing by heat treatment under predetermined conditions.
And a film 35.

Next, a method of manufacturing the semiconductor device shown in FIG. 9 will be described with reference to FIGS. However, in FIGS. 10A and 10B, illustration of a gate electrode, LOCOS isolation, and a bit line is omitted for easy understanding of a characteristic portion.

In the step shown in FIG. 10A, a first BPSG film 28 is deposited on the silicon substrate 1 as a first insulating film flowing by heat treatment under predetermined conditions. At this time, the impurity concentration in the BPSG film 28 is such that the phosphorus concentration is 5.0 wt% or less and the boron concentration is 6.0 wt% or less. Next, a heat treatment for planarizing the first BPSG film 28 is performed. For example, by performing a heat treatment at 850 ° C. for 30 minutes in a nitrogen atmosphere, the first BPSG film 28 is planarized. Next, after opening a contact hole for a capacitor electrode, polysilicon is deposited on the substrate including the contact hole, and a contact portion 29 filling the contact hole is formed.
And a polysilicon film 30 on the first BPSG film 28. Normally, N-type impurities are added to this polysilicon.

In the step shown in FIG. 10B, the capacitor electrode 31 including the contact portion 29 is formed by etching the polysilicon film 30 into a desired pattern.
Next, a silicon nitride film 32 is deposited on the substrate to a thickness of about 8 nm.

Although illustration of subsequent steps is omitted, the silicon nitride film 32 is oxidized to form a silicon nitride oxide film 33 shown in FIG. The oxidation conditions at that time are, for example, in a dry atmosphere, at a temperature of 850 ° C. and for a time of 30 minutes.
Minutes. Thereafter, a polysilicon film is formed on the substrate, and is etched into a desired pattern to form a plate electrode 34.
To form At this time, in the portion where the plate electrode 34 has been removed, the underlying silicon nitride oxide film 33 is also removed at the same time. Thereafter, a second BPSG film 35 as a third insulating film which flows by heat treatment under predetermined conditions is deposited, and is subjected to a heat treatment at, for example, 850 ° C. in a nitrogen atmosphere for 30 minutes. 35 is flattened. Thereafter, by performing desired wiring, a semiconductor device is completed.

The semiconductor device according to the present embodiment provides the second
When performing the heat treatment for planarizing the BPSG film 35, the silicon nitride oxide film 33 does not exist in a region other than below the plate electrode 34. That is, the upper surface of the silicon oxynitride film 33 is covered with the plate electrode 34 made of the polysilicon film. Therefore, in the flattening step of the upper interlayer insulating film, even if the lower interlayer insulating film is fluidized, the stress against the deformation of the silicon oxynitride film 35 is applied by the plate electrode 34, so that the silicon oxynitride film 33 is wrinkled. Alternatively, no crack occurs.

As described above, regardless of whether the supporting film is provided above or below the nitride film, the supporting film occupies at least the region including the region where the nitride film is formed on the common projection plane, that is, the supporting film. Is formed in the same planar shape as the nitride film or wider than the nitride film, it is possible to prevent generation of wrinkles or cracks in the nitride film during heat treatment under predetermined conditions.

In this embodiment, the silicon nitride film 3
When the silicon nitride oxide film 33 is formed by thermally oxidizing 2, the plate electrode 34 does not yet exist, and the silicon oxide film 9 as in the second embodiment is not formed below the silicon nitride film 33. However, no wrinkles or cracks occur in the silicon nitride film 32 in this oxidation step. Unlike the second embodiment, the first BP
This is because the upper limit of the impurity concentration in the SG film 28 is low, and the heat treatment temperature in the step of oxidizing the silicon nitride film 32 is also low. According to the experiment of the inventor, the first BPSG
If the impurity concentration in the film 28 is not more than 5.0 wt% of phosphorus and not more than 6.0 wt% of boron, the first B
It has been found that wrinkles or cracks in the silicon nitride film 32 can be prevented while the silicon nitride film 32 is dry-oxidized at a temperature lower than the heat treatment temperature for planarizing the PSG film 28. However, the first BPSG
Since the impurity concentration in the film 28 is low, the flatness after the heat treatment for flattening is slightly inferior to that of the second embodiment.

FIG. 11 is a cross-sectional view showing a structure of a semiconductor device according to a modification for avoiding such a problem. In this modification, the first BPSG film 28 has a high impurity concentration in the film to improve its flatness, and furthermore, the first BPSG film 28 and the silicon oxynitride film 33 have The same silicon oxide film 9 as in the second embodiment is interposed as a support film that does not flow due to heat treatment under predetermined conditions. Due to the presence of the silicon oxide film 9, even in the step of oxidizing the silicon nitride film 32 from the state shown in FIG. 10B, cracks or wrinkles of the silicon nitride film 32 can be prevented. The structure of the semiconductor device shown in FIG. 11 is the same as the structure of the above-described semiconductor device shown in FIG. 9 except that a silicon oxide film 9 is provided.

Further, the influence of the oxidation condition of the silicon nitride film 32 on the fluidity of the first BPSG film 28 is that it is less likely to occur in a dry atmosphere than in a pyro atmosphere. Has been confirmed by experiments. This is because the water vapor passing through the silicon nitride film 32 in the pyro atmosphere is more likely to be the first water vapor than the oxygen passing through the silicon nitride film 32 in the dry atmosphere.
This seems to make the BPSG film 28 flow more easily.

The effect of the method of depositing the silicon nitride film 32 on the silicon nitride film is as follows: before the deposition, heat treatment (pretreatment) of the underlayer in a nitrogen or ammonia atmosphere.
It was confirmed that cracks or wrinkles could be more reliably prevented by performing the above. This is because, by performing the pretreatment in a nitrogen or ammonia atmosphere, the silicon nitride film 32 on the first BPSG film 28 becomes thicker than when the pretreatment is not performed, so that the amount of oxygen passing through the silicon nitride film 32 is reduced. The first BPSG film 28
This is probably due to the difficulty of flowing. The reason why the thickness of the silicon nitride film varies depending on whether or not the pretreatment is performed is that a difference occurs in a timing at which the deposition starts depending on a difference in the state of the base. In this case, the deposition of the silicon nitride film is started on the BPSG film that has not been subjected to any pretreatment, while the deposition of the silicon nitride film is started on the BPSG film that has been pretreated in the nitriding atmosphere. Timing is delayed.

(Fifth Embodiment) Next, the structure of a DRAM cell in which a nitride film is provided only below a plate electrode as in the fourth embodiment is applied to a cylindrical stacked DRAM cell structure. An embodiment will be described.

FIG. 12 is a sectional view of a cylindrical stacked DRAM cell which is a semiconductor device according to the fifth embodiment. In FIG. 12, the gate electrode, the LOCOS isolation, and the bit line are not shown for easy understanding of the characteristic portion. This semiconductor device has a silicon substrate 1
And a first BPSG film 37 as a first insulating film flowing by heat treatment under predetermined conditions, a silicon nitride film 38 as a wet etching stopper, and a contact portion 39 connected to an active region in the silicon substrate. A cylindrical capacitor electrode 44, a silicon oxynitride film 43x as a second insulating film functioning as a capacitor insulating film, a plate electrode 45 also functioning as a supporting film, and a third fluidized by heat treatment under predetermined conditions. Second as insulating film
Of the BPSG film 46.

Next, a method of manufacturing the semiconductor device shown in FIG. 12 will be described with reference to FIGS. However, in FIGS. 13A to 13D, illustration of a gate electrode, LOCOS isolation, and a bit line is omitted for easy understanding of a characteristic portion.

First, in the step shown in FIG. 13A, a first BPSG film 37 is deposited on the silicon substrate 1 as a first insulating film flowing by heat treatment under predetermined conditions. At this time, the impurity concentration in the first BPSG film 37 is such that the phosphorus concentration is 5.0 wt% or less and the boron concentration is 6.0%.
wt% or less. Next, a heat treatment for planarizing the first BPSG film 37 is performed. For example, by performing a heat treatment at 850 ° C. in a nitrogen atmosphere for 30 minutes, the first BPS
The G film 37 is flattened. Next, a silicon nitride film 38 as a wet etching stopper for forming a cylindrical stack cell is formed. Then, after opening a contact hole in the silicon nitride film 38 and the first BPSG film 37, polysilicon is deposited on the substrate including the contact hole, and a contact portion 39 and the silicon nitride film 3 are formed.
8 and a polysilicon film 40 are formed. Next, a silicon oxide film 41 is formed on the polysilicon film 40.

In the step shown in FIG. 13B, after patterning the silicon oxide film 41 into a desired cell shape, a polysilicon film 42 is deposited on the substrate. At this time, before depositing the polysilicon film 42, the natural oxide film formed on the polysilicon film 40 is removed.

In the step shown in FIG. 13C, the polysilicon film 42 is anisotropically etched to remove the polysilicon film except on the side surface of the silicon oxide film 41, and the cylindrical capacitor including the contact portion 39 is removed. An electrode 44 is formed.

In the step shown in FIG. 13D, wet etching is performed using the silicon nitride film 38 as a wet etching stopper to form a silicon oxide film 41 as a cylindrical nucleus.
Remove only Next, a silicon nitride film 43 is deposited on the substrate to a thickness of about 8 nm, and the exposed surfaces of the silicon nitride film 38 and the cylindrical capacitor electrode 44 are covered with the silicon nitride film 43.
Cover with.

Although illustration of the subsequent steps is omitted, the silicon nitride film 43 is oxidized to form a silicon nitride oxide film 43x shown in FIG. The oxidation conditions at that time are, for example, a temperature of 800 ° C. and a time of about 30 minutes in a pyro atmosphere. Thereafter, a plate electrode 45 shown in FIG. 12 is formed by depositing a polysilicon film on the substrate and etching it into a desired pattern. This plate electrode 45
When etching is performed, in a region other than below the plate electrode 45, the underlying silicon nitride oxide film 43x and the silicon nitride film 38 as a wet etching stopper are formed.
Is also removed at the same time. Thereafter, a second BPSG film 46 as a third insulating film shown in FIG.
The second BPSG film 46 is planarized by performing a heat treatment at 850 ° C. in a nitrogen atmosphere for 30 minutes. Thereafter, by performing desired wiring, a semiconductor device is completed.

According to the semiconductor device of this embodiment, the second B
When performing a heat treatment for planarizing the PSG film 46, the silicon nitride oxide film 43x and the silicon nitride film 38 as a wet etching stopper do not exist in a region other than below the plate electrode 45. Similar to the embodiment, no wrinkles or cracks occur in the silicon nitride film 38 and the silicon nitride oxide film 43x.

In the present embodiment, when the silicon nitride film 43 is thermally oxidized to form the silicon nitride oxide film 43x, the plate electrode 45 does not yet exist, and the plate electrode 45 does not exist below the silicon nitride film 43 and the silicon nitride film 38. Although the silicon oxide film 17 is not formed as in the third embodiment, wrinkles or cracks do not occur in the silicon nitride film 38 and the silicon nitride oxide film 43x in this oxidation step. Unlike the third embodiment, the first BPS
This is because the upper limit of the impurity concentration in the G film 37 is low, and the heat treatment temperature for oxidizing the silicon nitride film 43 is also low. The conditions for preventing the BPSG film from flowing in the thermal oxidation process will be described in detail below.

Table 1 below shows the results of examining the state of wrinkling of the silicon nitride film when the silicon nitride film was thermally oxidized while changing the phosphorus concentration and boron concentration in the BPSG film and the thermal oxidation temperature. Is shown. Here, 〇 indicates a condition in which no wrinkle occurred, X indicates a condition in which wrinkle occurred, and Δ indicates a critical condition in which wrinkle occurred.

[0126]

[Table 1]

In the above experiments, the fluidization temperature of the BPSG film was 850 ° C. When the concentration of phosphorus or boron decreases, the degree of fluidization of the BPSG film deteriorates, and the flatness deteriorates. Therefore, when fluidization by heat treatment at 850 ° C. occurs, the concentration of phosphorus is 5.5% by weight. Therefore, the composition having a boron concentration of 3.8% by weight is the limit, and it seems that the concentration cannot be lower than this. At this time, no wrinkles were generated by the heat treatment at 820 ° C.

As can be seen from the above experiment, the temperature at which the BPSG film is fluidized is 830 ° C. or higher (for example, 850 ° C.).
° C), if the thermal oxidation temperature is 820 ° C or lower (eg, 800 ° C), the silicon nitride film can be thermally oxidized without fluidizing the BPSG film. Deformation of the silicon nitride film in the thermal oxidation step can be prevented.

However, depending on the adjustment of the concentration of phosphorus and boron, if the concentration of phosphorus is 2.0 to 6.0% by weight and the concentration of boron is 1.0 to 4.0% by weight, the present invention can be used. The effect is obtained to some extent.

Such a method is suitable for forming a DRAM cell in which the supporting film is constituted by a plate electrode and a separate supporting film made of a silicon oxide film is not provided, and is shown in FIG. This is a method applicable to the fourth embodiment.

When oxidizing the silicon nitride film 43, for example, in order to improve the flatness of the first BPSG film 37, a heat treatment is performed under conditions such that the first BPSG film 37 is fluidized. If it has to be performed, a silicon oxide film may be formed below the silicon nitride film 38.

FIG. 14 is a cross-sectional view showing the structure of a semiconductor device according to such a modification. In this variant, the first B
The PSG film 37 has a high impurity concentration in the film in order to improve its flatness. Further, the PSG film 37 does not flow between the first BPSG film 37 and the silicon nitride film 38 due to heat treatment under predetermined conditions. The same silicon oxide film 17 as in the third embodiment is interposed as a film. Due to the presence of the silicon oxide film 17, cracks or wrinkles of the silicon nitride film 38 and the silicon nitride oxide film 43x can be prevented even in the step of oxidizing the silicon nitride film 43 from the state shown in FIG. FIG.
The structure of the semiconductor device shown in FIG. 12 is the same as the structure of the semiconductor device shown in FIG. 12 except that a silicon oxide film 17 is provided. In this modification, a more stable process can be realized by adding the silicon oxide film 17.

(Modifications of Each of the Above Embodiments) In each of the above embodiments related to the cylindrical stack type DRAM cell, the etching stopper films are all made of silicon nitride films, but the present invention is limited to such embodiments. It is not something to be done. Ethyl tetrasilicate (Tetra-Ethyl-
Oxy-Silane TEOS) is a silicon oxide film formed by thermal decomposition.
Since a large etching selectivity with respect to the PSG film can be exhibited, for example, as shown in FIG. 5, FIG. 7, FIG. 12, FIG.
TEO instead of the silicon nitride films 18 and 38 in
An S film may be used. However, when the TEOS film is used as the etching stopper film, the film (the film 21 shown in FIG. 6A) serving as the nucleus of the cylindrical capacitor electrode is formed of the BPSG film. In that case, the TEOS film can exhibit a function as a supporting film, that is, a function of preventing deformation of the capacitor insulating film, and thus does not require a separate supporting film.

In the second to fifth embodiments, a film having an etching selectivity with respect to an oxide film is deposited on the substrate before opening the contact hole, and then the contact hole is opened. Does not increase after etching.

FIGS. 15A and 15B show a polysilicon film which is an edge-holding film having a high etching selectivity with an oxide film in the step of forming a contact hole in the manufacturing process of the second embodiment. FIG. 11 is a diagram showing a difference in the shape of a contact hole between a case where a 47 is formed and a case where a polysilicon film is not formed (second embodiment). FIG.
As shown in (A), when the polysilicon film 47 having a high etching selectivity with respect to the oxide film is formed on the silicon oxide film 9, the etching condition is reduced due to the presence of the polysilicon film 47. Fig. 15
The spread of the upper part of the contact hole as shown in FIG.

Further, in each of the above embodiments, the first insulating film having the property of flowing by the heat treatment under the predetermined condition is formed of the BPSG film, but the present invention is not limited to such an embodiment. For example, it is needless to say that the present invention can be applied to an insulating film to which arsenic is added instead of phosphorus or an insulating film having a characteristic of flowing at a lower temperature by adding fluorine.

Furthermore, in each of the above embodiments, the supporting film is
Although the first insulating film is provided between the lower interlayer insulating film and the silicon nitride film, the present invention is not limited to such an embodiment. For example, the silicon nitride film and the upper insulating Even if a silicon oxide film or the like is formed as a support film between the film and the film, it is necessary to surely prevent wrinkles and cracks in the silicon nitride film during the planarization of the upper interlayer insulating film. Can be.

In each of the embodiments relating to the DRAM cell, the first insulating film is a so-called first interlayer insulating film immediately above the substrate. However, the present invention is not limited to such an embodiment. Absent. Depending on the type of the DRAM cell, the capacitor electrode may be formed on the second interlayer insulating film or an interlayer insulating film further above the second interlayer insulating film. In such a case, the first insulating film is defined as the interlayer insulating film immediately below. Alternatively, it means all the lower interlayer insulating films.

[0139]

According to the semiconductor device of the present invention, there is provided a semiconductor device comprising a first insulating film having reflow characteristics and a second insulating film containing silicon nitride provided thereon. A support film having a property of giving a stress against the deformation of the nitride film without flowing in the heat treatment under predetermined conditions is provided above or below, so that in the subsequent process, the heat treatment under the predetermined conditions is performed. Even if the first insulating film flows, the deformation of the second insulating film is hindered by the supporting film, so that wrinkles and cracks in the second insulating film can be reliably prevented. The yield, reliability, and performance of the device can be improved.

In the case where the semiconductor device is a stacked DRAM cell provided with a capacitive insulating film made of a silicon oxynitride film, between the lower interlayer insulating film as the first insulating film and the second insulating film. Since a supporting film is provided on the substrate or a function as a supporting film is provided by a plate electrode, the capacitance insulating in the step of oxidizing the silicon nitride film for the capacitive insulating film and the step of flattening the upper interlayer insulating film. The occurrence of wrinkles and cracks in the film can be prevented, and
The yield, reliability, and performance of a semiconductor device functioning as a stacked DRAM cell can be improved.

Further, in the case where the semiconductor device is a cylindrical stack type DRAM cell provided with a capacitor insulating film made of a silicon nitride oxide film and an etching stopper film, the silicon nitride for the capacitor insulating film is formed by the same means as described above. A semiconductor device that can prevent wrinkles and cracks in a capacitive insulating film and an etching stopper film in a step of oxidizing a film and a step of planarizing an upper interlayer insulating film, and thus function as a cylindrical stacked DRAM cell Yield, reliability and performance can be improved.

The structure of these semiconductor devices can be easily realized by the method of manufacturing a semiconductor device according to the present invention .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device having a polycide wiring according to a first embodiment.

FIG. 2 is a sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment;

FIG. 3 is a cross-sectional view illustrating a structure of a stacked DRAM cell according to a second embodiment.

FIG. 4 is a cross-sectional view showing a step of manufacturing the stacked DRAM cell according to the second embodiment.

FIG. 5 shows a cylindrical stack type DRA according to a third embodiment.
It is sectional drawing which shows the structure of M cell.

FIG. 6 shows a cylindrical stack type DRA according to a third embodiment.
It is sectional drawing which shows the manufacturing process of M cell.

FIG. 7 is a cross-sectional view showing only one of manufacturing steps of a cylindrical stacked DRAM cell according to a first modification of the third embodiment;

FIG. 8 is a cross-sectional view showing a step of manufacturing a cylindrical stacked DRAM cell according to a second modification of the third embodiment.

FIG. 9 is a cross-sectional view illustrating a structure of a stacked DRAM cell according to a fourth embodiment.

FIG. 10 is a sectional view illustrating a manufacturing process of the stacked DRAM cell according to the fourth embodiment;

FIG. 11 is a sectional view showing the structure of a stacked DRAM cell according to a modification of the fourth embodiment.

FIG. 12 shows a cylindrical stack type DR according to a fifth embodiment.
It is sectional drawing which shows the structure of an AM cell.

FIG. 13 shows a cylindrical stack type DR according to a fifth embodiment.
It is sectional drawing which shows the manufacturing process of an AM cell.

FIG. 14 is a cross-sectional view illustrating a structure of a cylindrical stacked DRAM cell according to a modification of the fifth embodiment.

FIG. 15 is a cross-sectional view for explaining a modification for preventing an increase in the size of a contact hole in another embodiment.

FIG. 16 is a sectional view showing a structure of a conventional semiconductor device having a polycide structure.

FIG. 17 is a sectional view showing the structure of a conventional stacked DRAM cell.

FIG. 18 is a cross-sectional view showing a structure of a conventional cylindrical stack type DRAM cell.

FIG. 19 is a cross-sectional view showing a state in which wrinkles or cracks have occurred in a silicon nitride film in a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 gate electrode 3 first BPSG film 4 polycide wiring 5 silicon oxide film 6 silicon nitride film 7 second BPSG film 8 BPSG film 9 silicon oxide film 10 contact portion 11 polysilicon film 12 capacitance electrode 13 silicon nitride film Reference Signs List 14 silicon nitride oxide film 15 plate electrode 16 BPSG film 17 silicon oxide film 18 silicon nitride film 20 polysilicon film 21 silicon oxide film 22 polysilicon film 23 silicon nitride film 23x silicon nitride oxide film 24 cylindrical capacity electrode 25 plate electrode 26 BPSG Film 27 silicon oxide film 28 first BPSG film 29 contact part 30 polysilicon film 31 capacitance electrode 32 silicon nitride film 33 silicon nitride oxide film 34 plate electrode 35 second BPSG film 37 first BPSG film 38 Silicon nitride film 39 contact portion 40 polysilicon film 41 silicon oxide film 42 polysilicon film 43 silicon nitride film 44 cylindrical capacitor electrode 45 plate electrode 46 second BPSG film 47 polysilicon film

──────────────────────────────────────────────────の Continuation of front page (51) Int.Cl. ⁷ Identification symbol FI H01L 27/04 H01L 27/10 621B 27/108 621C 651 (56) References JP-A-6-188239 (JP, A) JP JP-A-61-81657 (JP, A) JP-A-63-126251 (JP, A) JP-A-3-220725 (JP, A) JP-A-11-74480 (JP, A) JP-A-6-21393 (JP) JP-A-10-223897 (JP, A) JP-A-8-204147 (JP, A) JP-A-11-195713 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H01L 21/312 H01L 21/314 H01L 21/316 H01L 21/318 H01L 21/3205 H01L 21/768 H01L 21/8242 H01L 27/108

Claims (35)

(57) [Claims] A substrate having a semiconductor region, a first insulating film formed on the semiconductor region and having a property of flowing by heat treatment under predetermined conditions, and a first insulating film formed on the first insulating film. is, film containing at least silicon nitride, or any one of a silicon nitride oxide film
Ranaru a second insulating film formed above the first insulating film, the predetermined conditions
Insulating film having the property of flowing due to heat treatment in the third insulating film
And an intervening member between the first insulating film and the second insulating film.
And a support film having a function of applying a stress against the deformation of the second insulating film due to the heat treatment to the second insulating film. 2. The semiconductor device according to claim 1 , wherein the support film is patterned so as to occupy at least a region including a formation region of the second insulating film on a common projection plane. Semiconductor device. A gate electrode formed on the semiconductor region ; an impurity diffusion layer formed in a region of the semiconductor region on a side of the gate electrode; The formed interlayer insulating film, a capacitor electrode that fills an opening formed in the interlayer insulating film and extends over a part of the interlayer insulating film, and is formed astride the capacitor electrode and the interlayer insulating film. A stack type DR having a capacitance insulating film and a plate electrode formed to face the capacitance electrode with the capacitance insulating film interposed therebetween.
An AM cell, comprising: a substrate having the semiconductor region; and a heat source formed on the semiconductor region under a predetermined condition.
A first insulating film having a property of flowing by processing , and at least a silicon nitride film formed on the first insulating film;
Either a film containing silicon or a silicon oxynitride film
A second insulating film formed between the first insulating film and the second insulating film.
Resists deformation of the second insulating film due to the heat treatment.
A supporting film having a function of applying stress to the second insulating film;
Comprising a said first insulating film is the interlayer insulating film, said second insulating film is the capacitor insulating film, the support film is between the interlayer insulating film and the capacitor insulating film A semiconductor device, wherein the semiconductor device is an insulating film interposed therebetween. 4. The semiconductor device according to claim 3, further comprising a third insulating film formed above the first insulating film and having a characteristic of flowing by heat treatment under the predetermined condition. Characteristic semiconductor device. 5. The semiconductor device according to claim 3 , wherein the support film is patterned so as to occupy at least a region including a formation region of the second insulating film on a common projection plane. Characteristic semiconductor device. 6. The semiconductor device according to claim 3 , wherein said capacitor electrode is a cylindrical capacitor electrode, and said capacitor electrode is provided below said capacitor electrode and said capacitor insulating film on said support film. A semiconductor device, further comprising an etching stopper film interposed over the substrate and forming a cylindrical capacitor electrode. 7. The semiconductor device according to claim 6 , wherein a lower surface of the cylindrical portion of the cylindrical capacitor electrode is separated from an upper surface of the etching stopper film, and the capacitor insulating film is formed between the cylindrical capacitor electrode and the cylindrical capacitor electrode. A semiconductor device formed along a surface of an etching stopper film. 8. The semiconductor device according to claim 6 , wherein said etching stopper film is a silicon nitride film. 9. The semiconductor device according to claim 3 , wherein said capacitance electrode is a cylindrical capacitance electrode, said support film is made of a TEOS film, and said cylindrical capacitance electrode is A semiconductor device which functions as an etching stopper film when forming the semiconductor device. The semiconductor device according to any one of 10. The system of claim 8, said support membrane, a semiconductor device which is a silicon oxide film. 11. A semiconductor device comprising : a gate electrode formed on a semiconductor region ; an impurity diffusion layer formed in a region of the semiconductor region which is located on a side of the gate electrode; The formed interlayer insulating film, a capacitor electrode that fills an opening formed in the interlayer insulating film and extends over a part of the interlayer insulating film, and is formed astride the capacitor electrode and the interlayer insulating film. A stack type DR having a capacitance insulating film and a plate electrode formed to face the capacitance electrode with the capacitance insulating film interposed therebetween.
An AM cell, comprising: a substrate having the semiconductor region; and a heat source formed on the semiconductor region under a predetermined condition.
A first insulating film having a property of flowing by processing , and at least a silicon nitride film formed on the first insulating film;
Film containing silicon or silicon oxynitride film.
And a second insulating film formed on the second insulating film and formed by the heat treatment.
The stress that resists the deformation of the second insulating film is applied to the second insulating film.
A supporting film having a function of providing the first insulating film;
A third insulating film having a property of flowing by heat treatment
And the support film is provided on the common projection plane.
At least the region including the region where the rim is formed is
The above-mentioned turned and patterned support film
If the second insulating film exists in a region other than below the
The semiconductor device according to claim 1 , wherein the first insulating film is the interlayer insulating film, the second insulating film is the capacitor insulating film, and the support film is the plate electrode. 12. The semiconductor device according to claim 11 , wherein said capacitive insulating film is constituted by a silicon nitride oxide film formed by oxidizing a silicon nitride film, and said interlayer insulating film is formed by said silicon nitride oxide film. A semiconductor device having a characteristic of not flowing due to heat treatment for oxidizing a film. The semiconductor device according to any one of 13. The method of claim 1 to 11, said second Ru insulating film, a semiconductor device which is a silicon nitride oxide film. The semiconductor device according to any one of 14. The method of claim 1 to 13, said first insulating film, a semiconductor device which is a BPSG film. 15. A first step of depositing a first insulating film having a property of flowing on a semiconductor substrate by heat treatment under a predetermined condition; and performing the first heat treatment under the predetermined condition. A second step of flowing and flattening the first insulating film; and forming a support film having a characteristic of not flowing by the heat treatment under the predetermined condition on the first insulating film.
Third step, a film containing silicon nitride or a silicon nitride film is formed on the support film.
Form a second insulating film made of any of the nitrided oxide films
A fourth step of depositing, a fifth step of depositing a third insulating film having a property of flowing by the heat treatment under the predetermined condition on the second insulating film; Performing a heat treatment to flow and flatten the third insulating film. In the sixth step, the supporting film resists deformation of the second insulating film. A method for manufacturing a semiconductor device, wherein a stress is applied to the second insulating film. 16. The method of manufacturing a semiconductor device according to claim 15 , wherein the supporting film is formed on a common projection plane after the fourth step and before the fifth step. A method of patterning the second insulating film and the supporting film so as to occupy at least a region including the formation region of the semiconductor device. 17. The method of manufacturing a semiconductor device according to claim 15 , wherein the forming of the second insulating film in the fourth step is performed.
, After forming a silicon nitride film is formed on the support film, by performing third heat treatment in the prescribed conditions, the nitrogen
Silicon film by oxidizing the surface of a step of forming a silicon nitride oxide film, in the third step of performing heat treatment, the above support film, the stress against the deformation of the second insulating film A method for manufacturing a semiconductor device, wherein the method is applied to a second insulating film. 18. Function as a stacked DRAM cell
A method for manufacturing a semiconductor device, comprising the steps of:
First step of depositing a first insulating film having the following characteristics:
Performing a first heat treatment under the above-mentioned predetermined conditions,
A second step of flowing and planarizing the first insulating film, and a film containing silicon nitride on the first insulating film;
Is a second insulating film made of any one of a silicon oxynitride film
A third step of forming a film, and a heat treatment under the predetermined condition on the second insulating film
To form a supporting membrane having the property of not flowing
Step 4 and after the fourth step, on the substrate under the above-mentioned predetermined conditions.
A third insulating film having the property of flowing by heat treatment
Performing a fifth step of depositing, and a second heat treatment under the predetermined conditions,
A sixth step of flowing and planarizing the third insulating film, and the supporting step after the fourth step and before the fifth step.
Forming the second insulating film on a common projection plane with the film
So as to occupy at least the region including the region on SL second
Simultaneously patterning the insulating film and the supporting film,
A capacitor insulating film composed of a second insulating film and the support film
A step of forming a plate electrode, wherein in the patterning step, the patterned
The second insulating film exists in a region other than below the rate electrode.
The second insulating film has been removed so as not to be present, and in the sixth step, the capacitor is formed by the plate electrode.
Applying a stress against the deformation of the insulating film to the capacitive insulating film
A method for manufacturing a semiconductor device, comprising: 19. A method for manufacturing a semiconductor device functioning as a stacked DRAM cell, comprising: depositing, on a semiconductor substrate having an impurity diffusion layer, a first insulating film having a property of flowing by heat treatment under predetermined conditions. A first step of performing a first heat treatment under the above-described predetermined conditions to flow and flatten the first insulating film; and a step of performing the above-mentioned predetermined conditions after the second step. A third step of forming a support film having a property of not flowing due to a heat treatment below; a fourth step of forming a contact hole reaching the impurity diffusion layer in the support film and the first insulating film; A fifth step of depositing a first capacitor electrode conductor film on a substrate including a contact hole, and patterning the first capacitor electrode conductor film to be connected to the impurity diffusion layer A sixth step of forming a capacitor electrode; and, after the sixth step, a second insulating film made of a silicon nitride film along a surface of the capacitor electrode and an exposed surface of the support film. Performing a second heat treatment under the predetermined conditions after the seventh step, thereby oxidizing the surface of the second insulating film to form a capacitor made of a silicon oxynitride film. An eighth step of forming an insulating film; and a ninth step of forming a plate electrode conductor film on the substrate after the eighth step. In the eighth step, the supporting film A method for manufacturing a semiconductor device, wherein a stress against deformation of the second insulating film due to the second heat treatment is applied to the second insulating film. 20. The method of manufacturing a semiconductor device according to claim 19 , wherein after the ninth step, a third insulating film having a property of flowing by heat treatment under the predetermined condition is formed on the substrate. And a step of performing a third heat treatment under the predetermined condition to fluidize and planarize the third insulating film. In the planarizing step, the support film forms the third insulating film. 3. A method for manufacturing a semiconductor device, wherein a stress against deformation of the second insulating film due to the heat treatment of 3 is applied to the second insulating film. 21. The method for manufacturing a semiconductor device according to claim 19 , wherein in the third step, a supporting film made of a TEOS film is formed, and after the fifth step, the supporting film is formed in the sixth step. Before the first
Forming a nucleus of a cylindrical capacitor electrode made of a BPSG film on the conductor film for a capacitor electrode, and then forming a second conductor film for a capacitor electrode on the substrate including the core of the cylindrical capacitor electrode Forming a cylindrical capacitor comprising the first and second capacitor electrode conductor films by patterning the first and second capacitor electrode conductor films. Forming an electrode, after the sixth step and before the seventh step, further comprising a step of removing a nucleus of the cylindrical capacitor electrode by etching; A method of manufacturing a semiconductor device, wherein the method functions as an etching stopper film in the step of removing a nucleus of the cylindrical capacitor electrode. 22. The method of manufacturing a semiconductor device according to claim 21 , further comprising, after the third step and before the fourth step, a step of forming a gap forming film on the support film. In the fourth step, the contact hole is formed so as to penetrate the gap forming film, and in the step of removing the core of the cylindrical capacitor electrode, the gap forming film is also removed. Exposing a surface of the cylindrical capacitor electrode which is in contact with the gap forming film, and in the seventh step, exposing the surface of the cylindrical capacitor electrode and the support film. A method of manufacturing a semiconductor device, comprising: depositing the second insulating film along a surface. 23. The method of manufacturing a semiconductor device according to claim 20 , wherein the first step is performed on a substrate after the second step and before the third step. Depositing an edge-holding insulating film having a high etching selectivity with respect to the insulating film, and forming the contact hole so as to penetrate the edge-holding insulating film in the third step. Manufacturing method of a semiconductor device. 24. A method for manufacturing a semiconductor device functioning as a cylindrical stack type DRAM cell, comprising: forming a first insulating film having a property of flowing by heat treatment under predetermined conditions on a semiconductor substrate having an impurity diffusion layer. A first step of depositing, a second step of performing a first heat treatment under the above-mentioned predetermined conditions to flow and planarize the first insulating film, and after the second step, A third step of forming a support film having a property of not flowing due to heat treatment under the conditions; a fourth step of forming an etching stopper film for forming a cylindrical capacitor electrode on the support film; A fifth step of forming a contact hole reaching the impurity diffusion layer in the film, the support film, and the first insulating film; A sixth step of depositing a conductor film for a capacitor electrode; a seventh step of forming a core of a cylindrical capacitor electrode on the first conductor film for a capacitor electrode after the sixth step; After the seventh step, an eighth step of forming a second conductor film for the capacitor electrode on the substrate including the nucleus of the cylindrical capacitor electrode, and the first and second conductor films for the capacitor electrode Ninth step of forming a cylindrical capacitor electrode composed of the first and second capacitor electrode conductor films by patterning, and after the ninth step, the core of the cylindrical capacitor electrode is etched by etching. After the tenth step of removing, and after the tenth step, a second insulating film made of a silicon nitride film is formed along the surface of the cylindrical capacitor electrode and the exposed surface of the support film. An eleventh step of depositing, and, after the eleventh step,
A twelfth step of oxidizing the surface of the second insulating film to form a capacitive insulating film made of a silicon oxynitride film by performing a heat treatment of A thirteenth step of forming a conductor film for use. In the twelfth step, the support film applies stress against deformation of the second insulating film and the etching stopper film due to the second heat treatment. A method for manufacturing a semiconductor device, wherein the method is applied to both. 25. The method of manufacturing a semiconductor device according to claim 24 , wherein after the thirteenth step, a third insulating film having a property of flowing by heat treatment under the predetermined condition is formed on the substrate. And a step of performing a third heat treatment under the predetermined condition to fluidize and planarize the third insulating film. The step of planarizing the third insulating film further comprises: A method of manufacturing a semiconductor device, wherein a stress against deformation of the second insulating film and the etching stopper film by the third heat treatment is applied to both the support film and the support film. 26. The method of manufacturing a semiconductor device according to claim 24 , further comprising a step of forming a gap forming film on the etching stopper film, wherein in the fifth step, the gap forming film is formed. In the step of removing the nucleus of the cylindrical capacitor electrode, the gap forming film is also removed, and the gap forming film is removed from the cylindrical capacitor electrode. In the eleventh step, the second insulating film is deposited along the exposed surface of the cylindrical capacitor electrode and the exposed surface of the support film. A method of manufacturing a semiconductor device. 27. The method of manufacturing a semiconductor device according to claim 24 , wherein after the second step and before the third step, the first A step of depositing an edge-holding insulating film having a high etching selectivity with respect to the insulating film, wherein in the fifth step, the contact hole is formed to penetrate the edge-holding insulating film. Manufacturing method of a semiconductor device. 28. A first step of depositing a first insulating film having a property of flowing on a semiconductor substrate having an impurity diffusion layer by heat treatment under predetermined conditions; and a first heat treatment under the predetermined conditions. A second step of flowing the first insulating film to planarize it, and a third step of depositing a second insulating film made of a silicon nitride film on the substrate after the second step. And after the third step, by performing a second heat treatment under the condition that the first insulating film does not flow, thereby oxidizing the surface of the second insulating film to remove the surface of the silicon nitride oxide film. And a fourth step of forming a capacitive insulating film. 29. The method of manufacturing a semiconductor device according to claim 28, wherein in the first step, a first insulating film made of a BPSG film having a fluidizing temperature of 830 ° C. or higher is deposited, In the process, a method for manufacturing a semiconductor device, wherein thermal oxidation is performed at a temperature of 820 ° C. or lower. 30. The method of manufacturing a semiconductor device according to claim 28, wherein in the first step, 2.0 to 6.0% by weight of phosphorus is added;
A method for manufacturing a semiconductor device, comprising: depositing a first insulating film made of a BPSG film containing 1.0 to 4.0% by weight of boron. 31. The method of manufacturing a semiconductor device according to claim 28, wherein in the fourth step, thermal oxidation is performed in a dry atmosphere. 32. The method of manufacturing a semiconductor device according to claim 28 , further comprising, before said third step, a step of nitriding an exposed surface of said first insulating film. Manufacturing method of a semiconductor device. 33. The method of manufacturing a semiconductor device according to claim 32, wherein in the nitriding step, a heat treatment is performed in a nitrogen or ammonia atmosphere. 34. The method of manufacturing a semiconductor device according to claim 28 , wherein the first insulating film has a contact reaching the impurity diffusion layer after the second step and before the third step. Forming a hole; depositing a conductive film for a capacitor electrode on a substrate including the contact hole; patterning the conductive film for a capacitor electrode to form a capacitor electrode connected to the impurity diffusion layer In the third step, the second insulating film is deposited on a substrate including the surface of the capacitor electrode, and after the fourth step, a conductive film for a plate electrode is formed on the substrate. Forming a conductive film for the plate electrode and
By patterning the second insulating film, a plate electrode and a capacitor are formed.
Forming a capacitive insulating film in a region other than below the plate electrode.
A method of manufacturing a semiconductor device, wherein the semiconductor device does not exist . 35. The method of manufacturing a semiconductor device according to claim 34 , wherein a cylindrical capacitor electrode is formed as the capacitor electrode.