JP3199997B2 - Multi-chip module and production method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module comprising a multi-layered circuit board on which a three-dimensional circuit is formed and a number of chip components such as LSI chips mounted thereon, and a method for producing the same.

[0002]

2. Description of the Related Art For example, a thin film circuit layer is formed on a surface of a ceramic multilayer wiring circuit board, and an LSI (large scale integrated circuit) chip is connected and mounted on the surface wiring of the thin film circuit layer by face-down bonding. A multi-chip module of a flip-chip mounting type is known. In this type of multi-chip module, the number of input terminals of each LSI chip increases and the number of signal wirings in the multilayer wiring circuit board increases due to the high integration of the LSI.
The multi-layer wiring circuit board on which the SI is mounted also needs to be multi-terminal and multi-layered, and the scale is inevitably increased. In such a large-scale multilayer wiring circuit board, defects (defects caused by the manufacturing process) in the manufacturing process of the fine wiring pattern are inevitably generated, and the yield is reduced. Therefore, it becomes difficult to avoid technology, and disposal of defective products becomes an issue. Therefore, in order to address this problem, it is difficult to improve the conventional technology described below.

One of them is that, as shown in Japanese Patent Application Laid-Open No. 4-102395, when manufacturing a multilayer wiring circuit board, inspection and correction are carefully performed for each layer, and the next layer is formed. An attempt is made to improve the yield and the reliability by stacking the multilayer wiring circuit boards with no defect by using a method for minimizing defective products. However, this method is a method based on the premise that the previous layer is stacked without any defect and that no defect occurs in the previous layer due to the influence of the steps after the formation of the next layer, and in the case of ultra-high density mounting, Not only is it impractical, but also a process of collectively laminating and firing multi-layer green sheets each printed with a circuit pattern, such as a ceramic multi-layer circuit board, that is, a process of collectively manufacturing a multi-layer circuit board There was a drawback that could not be applied to those containing. Japanese Patent Application Laid-Open No. 63-2133 discloses a method for compensating for this disadvantage.
As described in JP-A-99-99, a remodeling pattern is provided in advance on an inner layer of a multilayer wiring circuit board such as a printed circuit board, and when remodeling becomes necessary, the inner layer is removed from the surface of the multilayer wiring circuit board. In some cases, the remodeling pattern of the inner layer is accessed to cut or connect the remodeling pattern of the inner layer, thereby directly correcting and processing a wiring defective portion such as a short circuit portion or an open circuit portion of the inner layer. However, this method also has a drawback that it cannot be applied to a method in which access to an inner wiring pattern is extremely difficult or impossible once firing is performed, like a ceramic multilayer wiring circuit board.

Conventionally, it is necessary to slightly change the function of a multi-chip module constructed using a large-scale multilayer wiring circuit board as described above. Even if it is necessary to change the wiring, it is not possible to process the change at the required location. There was a drawback that required time. That is, although there is a strong need to reduce the development period of a multi-chip module, there has been no effective method that can meet the need.

[0005]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an original (same type as the original) without recreating a new multilayer wiring circuit board when it becomes necessary to relieve a manufacturing process defect or change a function. It is an object of the present invention to provide a multi-chip module and a method for producing the multi-chip module capable of developing and producing a multi-chip module achieving a predetermined quality and a required function in a short time by effectively utilizing a multilayer wiring circuit board. Another object of the present invention is to make effective use of an original (same type as the original) multilayer wiring circuit board without recreating a new multilayer wiring circuit board when it becomes necessary to relieve a manufacturing process defect or change a function. In order to increase the yield of development and production, it is possible to produce the required number and types of multi-chip modules with the minimum number and types of multilayer wiring circuit boards, It is an object of the present invention to provide a multi-chip module that minimizes or drastically reduces unnecessary waste and a method for producing the same.

[0006]

SUMMARY OF THE INVENTION The features of the present invention for achieving the above objects and objects are summarized as follows. The most significant feature of the present invention is that, in a multi-chip module, if a portion requiring correction such as a defective portion due to a manufacturing process or a change due to a function change can be directly corrected, the portion requiring correction is corrected. If it is not possible to make the correction directly, it is indirectly corrected at the place where the correction is required, which is electrically connected to the part requiring the correction and which is provided on the upper layer or on the chip component. The point is that it is processed. The case where the portion requiring correction can be directly corrected is the case where the portion requiring correction can be exposed, for example, when the portion requiring correction is located on the surface of the multilayer wiring circuit board or a layer near the surface. The case where the portion cannot be directly corrected is a case where the portion requiring correction cannot be exposed, such as when it is located in an inner layer of the ceramic multilayer wiring circuit board.

According to the present invention, in a multi-chip module, a portion requiring correction such as a defective portion associated with a manufacturing process or a changed portion associated with a function change is basically either open (open) or short (short). Focusing on a certain point,
Even if the above-mentioned non-exposed necessary correction portion is left unmodified or unmodified in the inner layer of the multilayer wiring circuit board, the correction is performed at the upper layer of the multilayer wiring circuit board or at the repaired portion provided on the chip component. That is, the present invention is characterized by adopting a new finding that a portion requiring correction and a portion to be corrected may be physically or geometrically separated from each other. On the other hand, in the conventional technology, the defect correction or the wiring change in a certain layer is performed by directly performing a correction process on the layer. Therefore, correction of a defective portion or a wiring change portion that cannot be directly corrected cannot be dealt with. The present invention provides a multi-chip module including not only a multilayer wiring circuit board but also a chip component by using the above two correction methods, that is, a correction required portion / correction location matching correction method and a correction required portion / correction location separation / correction method. By applying the invention comprehensively, waste such as disposal of defective products can be eliminated, and a target product can be provided to a user in a short time.

[0008] Means for solving the object of the present invention are as follows. That is, the present invention is a multi-chip module in which a plurality of chip components are mounted and connected on the surface of a multilayer three-dimensional circuit board. For the first type parts that can be directly corrected,
For a second type portion that is directly corrected at or near the type portion and cannot be directly corrected, an upper layer correction portion electrically connected to the second type portion or indirectly in the chip component. A multi-chip module, characterized in that it has been modified to: The present invention also relates to a multi-chip module in which a plurality of chip components are mounted and connected on the surface of a multilayer three-dimensional circuit board. Possible first type places are directly changed at or near the first type places, and second type places that cannot be directly changed are electrically connected to the second type places. A multi-chip module characterized by being changed indirectly in an upper layer change portion or the chip component.

The present invention is also a multi-chip module in which a plurality of chip components are mounted and connected on a surface of a multilayer three-dimensional circuit board formed by connecting a second multilayer three-dimensional circuit on a first multilayer three-dimensional circuit. A multi-chip module characterized in that a modified wiring circuit in which a wiring defective part in the inner layer of the first multilayer three-dimensional circuit due to a manufacturing process is indirectly corrected is formed in the second multilayer three-dimensional circuit. The present invention also provides a multi-chip module in which a plurality of chip components are mounted and connected on a surface of a multilayer three-dimensional circuit board having a second multilayer three-dimensional circuit connected and formed on a first multilayer three-dimensional circuit. A first repair wiring circuit that indirectly corrects a wiring defect caused by a manufacturing process existing in an inner layer of a multi-layer three-dimensional circuit, and a wire correction defect directly generated by the manufacturing process generated in the second multi-layer three-dimensional circuit. And a second modified wiring circuit formed in the second multilayer three-dimensional circuit.

The present invention is also a multi-chip module in which a plurality of chip components are mounted and connected on a surface of a multilayer three-dimensional circuit board having a second multilayer three-dimensional circuit connected and formed on a first multilayer three-dimensional circuit. A multi-chip module, wherein a wiring change circuit in which a wiring change portion accompanying a function change in an inner layer of the first multilayer three-dimensional circuit is indirectly changed is formed in the second multilayer three-dimensional circuit. The present invention also provides a multi-chip module in which a plurality of chip components are mounted and connected on a surface of a multilayer three-dimensional circuit board having a second multilayer three-dimensional circuit connected and formed on a first multilayer three-dimensional circuit. A first wiring change circuit that indirectly changes a wiring change location due to a function change in an inner layer of a multi-layer three-dimensional circuit, and a second wiring change circuit that directly changes a wiring change location due to a function change in the second multilayer three-dimensional circuit. The wiring change circuit and the second
A multi-chip module characterized by being formed in a multi-layer three-dimensional circuit.

The present invention is also an electronic circuit module device (multi-chip module mounting structure), wherein the multi-chip module is electrically connected to a printed circuit board and mounted. Further, the present invention provides a multilayer three-dimensional circuit board manufacturing process for manufacturing a multilayer three-dimensional circuit board, and a chip component mounting connection process for mounting and connecting a plurality of chip components on a surface of the multilayer three-dimensional circuit manufactured in the multilayer three-dimensional circuit board manufacturing process. A method of producing a multi-chip module having a multilayer three-dimensional circuit board manufactured in the multi-layer three-dimensional circuit board manufacturing process, wherein a defect caused by a manufacturing process occurring in a wiring of a multi-layer three-dimensional circuit can be directly corrected. It is determined whether or not the first type portion that can be directly corrected is directly corrected at or near the first type portion, and the second type portion that cannot be directly corrected is the second type portion. A multi-chip module having a wiring correction step of indirectly correcting an upper-layer correction portion electrically connected to the portion or the chip component. It is a method.

The present invention also provides a multi-layer three-dimensional circuit board manufacturing process for manufacturing a multi-layer three-dimensional circuit board, and a chip component for mounting and connecting a plurality of chip components on a surface of the multi-layer three-dimensional circuit manufactured in the multi-layer three-dimensional circuit board manufacturing process. A method for producing a multi-chip module having a mounting and connecting step, wherein a change in the wiring of the multilayer three-dimensional circuit of the multilayer three-dimensional circuit board manufactured in the multilayer three-dimensional circuit board manufacturing step is directly changeable. It is determined whether or not the first type portion that can be directly changed is directly changed at or near the first type portion, and the second type portion that cannot be directly changed is the second type portion. A multi-chip module having a wiring change step of indirectly changing an upper layer change portion or the above-mentioned chip component electrically connected to the above-mentioned portion. It is a method of production. The present invention also provides
A first multi-layer three-dimensional circuit manufacturing process for manufacturing a first multi-layer three-dimensional circuit, a first multi-layer three-dimensional circuit manufacturing process;
Inspecting the multi-layer three-dimensional circuit of (i) to detect a defective portion in the inner layer of the first multi-layer three-dimensional circuit due to the manufacturing process.
Correcting a defective portion detected in the inspection process of the first multilayer three-dimensional circuit on the first multilayer three-dimensional circuit manufactured in the inspection process of the multilayer three-dimensional circuit and the first multilayer three-dimensional circuit manufacturing process A second multilayer three-dimensional circuit forming step of connecting and forming a second multilayer three-dimensional circuit by incorporating a correction circuit;
A multi-layer three-dimensional circuit board manufacturing process for manufacturing a multi-layer three-dimensional circuit board including a second multi-layer three-dimensional circuit, and mounting and connecting a plurality of chip components on a surface of the multi-layer three-dimensional circuit board manufactured in the multi-layer three-dimensional circuit board manufacturing process. And a chip component mounting connection step of obtaining a multi-chip module by using the above method.

The present invention also provides a first multi-layer three-dimensional circuit manufacturing step for manufacturing a first multi-layer three-dimensional circuit, and inspecting the first multi-layer three-dimensional circuit manufactured in the first multi-layer three-dimensional circuit manufacturing step. Inspection step of the first multi-layer three-dimensional circuit for detecting a defective part in the inner layer of the first multi-layer three-dimensional circuit due to the manufacturing process, and first multi-layer three-dimensional circuit manufactured in the first multi-layer three-dimensional circuit manufacturing step A second multi-layer three-dimensional circuit forming step of connecting and forming a second multi-layer three-dimensional circuit by incorporating a correction circuit for correcting a defective portion detected in the first multi-layer three-dimensional circuit inspection step; A multi-layer three-dimensional circuit board manufacturing process for manufacturing a multi-layer three-dimensional circuit board including the first and second multi-layer three-dimensional circuits, and mounting and connecting a plurality of chip components on a surface of the multi-layer three-dimensional circuit board manufactured in the multi-layer three-dimensional circuit board manufacturing process Multi chip model Chip component mounting connection step for obtaining a module, a multi chip module function inspection step for performing a function inspection of the multi chip module obtained in the chip component mounting connection step, and a multi chip module obtained in the multi chip module function inspection step Directly modifying or changing a corresponding portion of the second multilayer three-dimensional circuit based on the function test described above.

Further, the present invention provides a multi-layer three-dimensional circuit board lower layer manufacturing step for manufacturing a lower layer part of a multi-layer three-dimensional circuit board, and a multi-layer three-dimensional circuit board manufactured in the lower layer part manufacturing step. A first inspection step of inspecting a defective wiring by a manufacturing process to be performed, and a defect detected in the first inspection step on a lower layer portion of the multilayer three-dimensional circuit board manufactured in the lower layer part manufacturing step of the multilayer three-dimensional circuit board. A multilayer three-dimensional circuit board upper layer forming step of connecting and forming an upper layer part of the multilayer three-dimensional circuit board by incorporating a correction circuit for correcting wiring, and a surface of the multilayer three-dimensional circuit board manufactured in the multilayer three-dimensional circuit board upper layer forming step. A chip component mounting connection step of mounting and connecting a plurality of chip components to obtain a multi-chip module. Further, according to the present invention, there is provided a lower layer manufacturing step for manufacturing a lower layer of a multilayer three-dimensional circuit board, and a first step of inspecting a defective wiring in the lower layer of the multilayer three-dimensional circuit board manufactured in the lower layer manufacturing step. And a correction circuit for correcting the defective wiring detected in the first inspection step is mounted on the lower layer of the multilayer three-dimensional circuit board manufactured in the lower layer part manufacturing step of the multilayer three-dimensional circuit board manufacturing step. An upper layer portion forming step of connecting and forming an upper layer portion of the circuit board, a second inspection step of inspecting wiring in the upper layer portion of the multilayer three-dimensional circuit board manufactured in the upper layer portion forming step, and a second inspection step. An upper layer wiring correction step of correcting wiring in an upper layer part of the multilayer three-dimensional circuit board according to the inspection result, and mounting and connecting a plurality of chip components on the surface of the multilayer three-dimensional circuit board corrected in the upper layer wiring correction step A method for producing a multi-chip module and having a chip component mounting connection to obtain a multi-chip module Te.

According to the present invention, a multi-chip module is characterized in that the logic-changed chip parts are mounted and connected on the surface of a multilayer three-dimensional circuit board to fulfill / change (logic change) the function of the multi-chip module. Is the way.
Further, the present invention is characterized in that the function of the multi-chip module is satisfied / changed (logic change) by mounting and connecting the chip component whose logic has been changed using the empty pad of the chip component on the surface of the multilayer three-dimensional circuit board. This is a method for producing a multi-chip module. Also, the present invention provides a multi-chip module in which a logic-changed chip component is mounted and connected to the surface of a multilayer three-dimensional circuit board, and the multilayer three-dimensional circuit board is provided with a through-line that is a conductor extending from the front side to the back side. This is a method for producing a multi-chip module, which performs function fulfillment / change (logic change).

As described above, according to the present invention, when it becomes necessary to relieve a manufacturing process defect or change a function,
Multi-chip modules that achieve the required quality and required functions can be developed and manufactured in a short period of time by effectively utilizing the original (same type as the original) multilayer wiring circuit board without recreating a new multilayer wiring circuit board. It can be. Further, according to the present invention, when it becomes necessary to relieve a manufacturing process defect or change a function, the original (same type) multilayer wiring circuit board can be effectively utilized without recreating a new multilayer wiring circuit board. , Increasing the yield of development and production, enabling the production of the required number and types of multi-chip modules with the required minimum number and types of multilayer wiring circuit boards, and the defective and unnecessary multilayer wiring circuit boards and multi-chip modules Waste can be reduced or reduced as much as possible.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Several embodiments of a multi-chip module and a method for producing the same according to the present invention will be specifically described below with reference to the drawings. FIG. 1 is a perspective view showing one embodiment of an electronic circuit module device in which a multi-chip module according to the present invention is mounted on a printed circuit board 5. FIG. 2 is a sectional view showing one embodiment of the multichip module according to the present invention. 1 and 2
As shown in the figure, a multilayer wiring circuit board 31 is a ceramic circuit board (basic multilayer wiring circuit board) 1 manufactured by printing, laminating and sintering by a thick film process, and a thin film wiring having a thin film wiring and a pad. It is obtained by forming a layer 2. A large number of LSI chip components (electronic components such as LSI) 14 are mounted and connected to terminal connection pads 12 formed on the surface of the thin film wiring layer 2 by a bonding material 13 such as a solder ball, thereby forming a multi-chip module. . That is, the multi-chip module is configured by mounting and connecting a large number of LSI chip components 14 on the surface of the multilayer wiring circuit board 31. In the large-scale electronic circuit module device, the electrical connection is established by inserting the input / output pins 33 implanted on the back surface of each of the plurality of multilayer wiring circuit boards 31 into the connectors 34 provided on the printed circuit board 35. Composed of

The first circuit wiring group 16a is formed by printing and laminating and sintering a ceramic circuit board (basic multilayer wiring circuit board) 1 by a thick film process, and the surface (final end face) of the ceramic circuit board 1 ) And has a thick film connection pad 4a normally connected to the inner layer wiring. And the first circuit wiring group 16a is
The thick film connection pad 4a on the final end face connected to the normal inner layer wiring is provided with a conductive material such as Cr formed by sputtering or the like in the contact hole 5a formed in the first insulating layer 10 as the thin film wiring layer 2. The connection is made by an intermediate pad 7a formed of a film, and the second pad which is the thin film wiring layer 2 is connected to the intermediate pad 7a.
The contact holes formed in the insulating layer 11 are formed by applying Ni plating to a base formed by electroless plating or the like, applying Au plating thereon, and connecting the terminal connection pads 12a. The thick film connection pads 4a, the intermediate pads 7a, and the terminal connection pads 12a need to be all concentrically overlapped to enable high-density mounting.

The second circuit wiring group 16b is formed by printing a ceramic circuit board (basic multilayer wiring circuit board) 1 by a thick film process, laminating and sintering the ceramic circuit board (basic multilayer wiring circuit board). 1) A short-circuit defect (short defect: a defective defect caused by short-circuiting at a position that must be separated between wirings) 9 occurs in the wiring layer which is an inner layer of 1), and corresponds to the position. That is, when the ceramic circuit board 1 is manufactured, a short-circuit defect 9 occurs in the wiring layer as an inner layer, and the thick film connection pads 4d and 4e formed on the surface (final end face) of the ceramic circuit board 1 Is short-circuited in the ceramic circuit board 1. This short-circuit defect 9 can be detected by <SC8> electrical circuit inspection at the stage when the ceramic circuit board 1 is completed as shown in FIG. However, the ceramic circuit board 1 is shown in FIG.
As shown in the steps 1) to (SC7), since a large number of green sheets formed by printing high-density wiring are laminated and sintered, the ceramic circuit board 1 is in a single state. In addition, it is impossible to cut the short-circuit defect 9 without digging and damaging the inner wiring.
Therefore, the short-circuit defect 9 generated in the ceramic circuit board 1 is repaired while forming the thin film wiring layer 2 on the surface of the ceramic circuit board 1. However,
Also in the second circuit wiring group 16b, the thick film connection pad 4d, the intermediate pad 7d, and the terminal connection pad 12
In order to enable high-density mounting, d needs to be arranged almost concentrically. In order to realize these, the contact holes 5d formed in the first insulating layer 10 which is the thin film wiring layer 2 formed on the surface of the ceramic circuit board 1 are the same as those used in the first insulating layer 10 or the same. The intermediate pad 7d is formed by covering with a similar insulator a6 and forming a conductive film such as Cr on the insulator 6 by sputtering or the like in the same manner as the intermediate pad 7a. Thereby, the intermediate pad 7d is connected to the thick film connection pad 4e via the short-circuit defect 9.
Can be separated from the thick film connection pad 4d which is short-circuited. However, simply removing the intermediate pad 7d from the thick film connection pad 4d does not mean that the correction has been made. That is, it is necessary to connect the intermediate pad 7d to the other party to which the thick film connection pad 4d is originally connected.

Therefore, when the intermediate pads 7 are formed, a correction line pattern (lead line pattern) 8 extending in one direction is formed between all the intermediate pads 7 on the surface of the first insulating layer 10. As shown in FIG. 1, the extending direction of the correction line pattern (leading line pattern) 8 may be changed, for example, by 90 degrees between the LSI chip components 14 so as not to cross each other. In any case, a first insulating layer 10 is formed on the surface of the ceramic circuit board 1, a contact hole 5 is formed in the first insulating layer 10 by a photolithography process, and the first insulating layer 10 is formed on the first insulating layer 10. A conductive film of Cr or the like is formed by sputtering, a resist is applied, and the pattern of the intermediate pad 7 and the pattern of the repair line pattern (lead line pattern) 8 in the pattern arrangement determined by exposure using a mask are determined. In addition to forming the pattern, a pattern (conductive film pattern of Cr or the like) of the repair conductor line 15 that connects between the intermediate pad 7d and the repair line pattern 8d or 8e by spot exposure of a laser beam is formed and etched. All the intermediate pads 7 and the repair line pattern (lead-out line pattern) 8 are formed, and the intermediate pad 7d is connected to the repair conductor line. It is connected to the modified line pattern 8d or 8e by 5. If the partner connected to the intermediate pad 7d is an intermediate pad, the repairing conductor line 15 is used to connect to the correction line pattern 8n formed close to the partner intermediate pad 7n. And these modified line patterns 8d or 8e
And the correction line pattern 8n of the other party. Therefore, conductor lines are formed by laser beam spot exposure while leaving a conductive film of Cr or the like, and these repair line patterns 8d or 8e are connected to the repair line patterns 8n. However, if the correction line pattern 8d or 8e and the correction line pattern 8n are not connected to another correction line pattern, it is not possible to irradiate a laser beam focused on a desired portion of the other correction line pattern. Then, the other corrected line pattern may be evaporated and cut. Then, the second insulating layer 1 is formed on the intermediate pad 7 and the repair line pattern 8 in which a conductive film such as Cr is patterned.
1 and a contact hole is formed by a photolithography process.
A terminal connection pad 12 made of u is formed. Thereby, the intermediate pad 7d and the terminal connection pad 12d are connected concentrically, and the thick film connection pad 4e, the intermediate pad 7e and the terminal connection pad 12e are stacked and connected concentrically.

In the state of the conductive film such as Cr, a repair line pattern (lead line pattern) 8d or 8e
If it is not possible to connect (8 ′) and the correction line pattern 8n (8 ″) of the other party, thereafter, as shown in FIG. Correction line patterns (drawing line patterns) 8d or 8e to be connected by making holes in
(8 ′), 8n (8 ″) end (pad) is exposed,
The correction can also be performed by bonding between these two ends (pads) with a correction wire 32 and sealing the ends with an insulator. As the correction wire 32, a polyurethane-coated Au wire in which the coating is removed only at the joints at both ends is desirable. As described above, the short-circuit defect 9 generated in the ceramic circuit board 1 is such that the thick film connection pad 4d leading to the short-circuit defect 9 is separated from the intermediate pad 7d by the insulator 6, and the terminal connection pad 12d is changed to the intermediate pad 7
The correction is made by connecting to the correction line pattern 8 via d. That is, the short-circuit defect 9 generated in the ceramic circuit board 1 is corrected while forming the thin film wiring layer 2 on the surface of the ceramic circuit board 1.

Since a disconnection defect generated in the ceramic circuit board 1 cannot be repaired in the ceramic circuit board 1 like the short-circuit defect 9, the thin film wiring layer 2 is formed on the surface of the ceramic circuit board 1. It will be corrected while. That is, in the ceramic circuit board 1,
For example, if there is a disconnection between the thick film connection pad 4b and the thick film connection pad 4e, the intermediate pad 7b and the repair line pattern 8b are connected by the repair conductor line 15 in the same manner as described above, and the intermediate pad 7e And correction line pattern 8
e is connected by the repair conductor line 15 in the same manner as described above. Then, it is necessary to connect these correction line patterns 8b and the other party's correction line patterns 8e. Accordingly, conductor lines are formed by spot exposure of a laser beam while leaving a conductive film such as Cr, and these modified line patterns 8b are formed.
And the correction line pattern 8e. However, in a case where the correction line pattern 8b and the correction line pattern 8e are not connected to another correction line pattern, it is impossible to irradiate a laser beam focused on a desired portion of the other correction line pattern. It is only necessary to evaporate the corrected line pattern and perform cutting. As described above, the second pad is formed on the intermediate pad 7 and the correction line pattern 8.
Is formed, a contact hole is formed by a photolithographic process, and the underlying Ni is formed by an electroless plating technique.
And a terminal connection pad 12 made of Au on the surface. Thus, the thick film connection pad 4, the intermediate pad 7, and the terminal connection pad 12 are stacked and connected concentrically. If it is not possible to connect the correction line pattern (lead-out line pattern) 8b (8 ') and the partner's correction line pattern 8e (8 ") in the state of the conductive film such as Cr, As shown in FIG. 1, two correction extraction patterns 8b (8 ') to be connected by making a hole in the insulating layer 11 by irradiating a focused excimer laser beam,
The end (pad) of 8e (8 ") is exposed, the two ends (pads) are connected by bonding with a correction wire 32, and the ends are sealed with an insulator to thereby form a ceramic circuit board. It is also possible to correct a disconnection defect that has occurred within 1.

Next, the multilayer wiring circuit board 31 according to the present invention
Will be described with reference to FIG.

(1) First, as shown in FIG. 3A, in a ceramic circuit board (basic multilayer wiring circuit board) 1 in which some of the internal wiring patterns 3a and 3b have a short circuit failure 9 in the manufacturing process. Then, a thin film wiring layer 2 is formed on the ceramic circuit substrate 1 serving as the base substrate by using a thin film forming technique. That is, a first insulating layer 10 is formed of, for example, a polyimide resin on the thick film connection pads 4a to 4f of the ceramic circuit board 1, and the first insulating layer 10 is electrically connected to the thick film connection pads 4a to 4f. Contact holes 5a to 5c, which are substantially concentric with the thick film connection pads 4a to 4f,
5f is formed using a photolithographic process. Note that a technique such as photoetching can be used to form the contact hole 5.

(2) Next, as shown in FIG. 3B, of the contact holes 5a to 5f, the thick film connection pads 4 connected to the internal wiring 3b causing the short-circuit failure 9.
An extremely small amount of insulating resin such as polyimide resin is supplied to the inside of the contact hole 5d corresponding to d by an insulating resin minute supply machine configured so that the injection nozzle can be finely moved in the xyz direction by a manipulator. The thick film connection pad 4d is separated (separated) from an upper layer wiring (intermediate pad 7d) formed in the next step by filling the insulator 6 with local heat by laser light and solidifying it. In the above embodiment, the formed contact hole 5d
In the above description, a very small amount of insulating resin is supplied and filled with the insulator 6, but the contact hole 5d is not formed by spot exposure (the contact hole 5d is not drilled). It can be separated from the upper layer wiring (intermediate pad 7d) formed in the next step.

(3) Thereafter, as shown in FIG.
C is formed on the first insulating layer 10 including the inside of the contact hole 5.
A conductive film such as r is formed by sputtering or the like. And this Cr
A resist is applied on a conductive film such as
The correction line patterns 8a to 8f extending in substantially one direction so as not to intersect with each other between the 7f and the intermediate pad are exposed with a predetermined pattern, and a portion where the repair conductor line 15 is formed is spot-exposed, and thereafter, By performing the etching, the intermediate pads 7a to 7f and the correction line pattern (leading line pattern) 8a to
8f is formed, and the repair conductor 15 is connected (connected) between the intermediate pad 7d and the repair line pattern 8d or 8e by remaining without being etched. That is, the intermediate pad 7d separated from the thick film connection pad 4d of the ceramic circuit board 1 by the insulator 6.
And the correction line pattern 8d or 8e to be connected to a desired wiring pattern later by performing spot exposure together with, for example, negative resist exposure on the intermediate pad 7 and the correction line pattern 8, thereby forming the intermediate pad 7 and the correction And the repair conductor line 15 made of the same conductive film as Cr as the line pattern 8 for use. In the case where there is a thick film connection pad 4n which is originally connected to the thick film connection pad 4d in the ceramic circuit board 1, this thick film connection pad 4n is also separated by the insulator 6, and the intermediate pad 7n thereon It is necessary to connect between the repair conductor line 15 and the repair line pattern 8n. Therefore, spot exposure of laser light
The conductor lines are formed while leaving the conductive film such as above, and these repair line patterns 8d or 8e are connected to the partner repair line pattern 8n. However, if the correction line pattern 8d or 8e and the correction line pattern 8n are not connected to another correction line pattern, it is not possible to irradiate a laser beam focused on a desired portion of the other correction line pattern. Then, the other corrected line pattern may be evaporated and cut.

(4) Further, as shown in FIG.
Intermediate pads 7a to 7f and correction line pattern 8a
A second insulating layer 11 is formed of, for example, a polyimide resin on the second insulating layer 11 and the intermediate pads 7a to 7f.
In order to make a conductive connection with the intermediate pads 7a to 7f, contact holes substantially concentric with the intermediate pads 7a to 7f are formed using a photolithographic process. Then, the terminal connection pads 12a to 12f for making a conductive connection with the intermediate pads 7a to 7f are formed by electroless plating with Ni plating on the base and Au plating thereon. As described above, a multilayer wiring circuit board 31 including the ceramic circuit board 1 and the thin film wiring layer 2 formed thereon and having a modified circuit is formed.

When the short circuit defect and the disconnection defect are detected by inspection after the completion of the multilayer wiring circuit board 31, it is corrected as follows. For example, when a disconnection defect occurs between the terminal connection pad 7a and the terminal connection pad 7d, as shown in FIG. 13, first, a part of the insulating layer 11 is removed around the terminal connection pad 7a by laser processing. A part of the pattern of the terminal connection pad 7a and the correction line pattern 8a.
And, for example, metallurgical bonding of metal foil such as gold foil using an ultrasonic chip and a heating chip, and metallurgical bonding. Is formed, and the insulating resin 109 ′ is filled and solidified. And about the other party terminal connection pad 7d,
Around the terminal connection pad 7d, a part of the insulating layer 11 is removed by excimer laser processing.
A part of the pattern d and a part of the correction line pattern 8d are exposed, and both are metallurgically bonded using, for example, a metal foil such as a gold foil using an ultrasonic chip and a heating chip. Dam 121 to prevent brazing material spread and gold diffusion
Is formed, and the insulating resin 109 ′ is filled and solidified. After that, as shown in FIG. 1, the ends of two correction lead patterns 8a (8 ') and 8d (8 ") to be connected by making a hole in the insulating layer 11 by irradiating the focused excimer laser beam. The pad (pad) is exposed, the two ends (pads) are connected by bonding with a correction wire 32, and the ends are sealed with an insulator, so that a disconnection defect can be corrected. As the use wire 32, a polyurethane-coated Au wire in which the coating is removed only at the joint portions at both ends is desirable.

As for the short-circuit defect, a part of the insulating layer 11 is removed by excimer laser processing to expose a short-circuit defect portion thereunder, and the exposed short-circuit defect portion is irradiated with a laser beam to form a conductive material such as Cr. The line pattern formed by the film is cut, and thereafter, this portion is filled with the insulating resin 109 ′,
It can be corrected by solidification. FIGS. 4 and 5 are diagrams for briefly showing the features and effects of the present invention. FIG.
FIG. 5 is a partial cross-sectional view of the multilayer printed circuit board provided with the thin film layer, and FIG. 5 is a partial plan view of the thin film layer when the present invention is implemented, and a portion of the multilayer printed circuit board provided with the thin film layer. FIG. In the manufacturing process of the ceramic circuit board (thick film circuit board) 1 serving as a base, it is inevitable that short-circuit defects occur at a certain frequency. In that case, the ceramic circuit board 1 is shown in FIG. As shown in the step (SC7), a large number of green sheets formed by printing high-density wiring are laminated and manufactured by sintering. The short-circuit defect 9 is performed without damaging the
It is impossible to cut. Therefore, the defect of the wiring pattern in the ceramic circuit board (thick film circuit board) 1 is
It is necessary to modify the upper thin film wiring layer 2.

In this case, according to the conventional concept, as shown in FIG. 4, a lead-out pad 27 is formed through a contact hole 25 formed on the thick film connection pad 4, and the lead-out pad 27 is , Upper layer terminal connection pad 12
An intermediate pad 28 for making a connection with the pattern 23 and a pattern 23 which is also used for connection between the intermediate pad 28 and the lead-out pad 27 and for circuit isolation are provided at different positions in plan view. When the circuit needs to be corrected, a part 24 of the pattern 23 is cut and removed at the cut position to separate the circuit, and the other part is repaired by the repair conductor 22 at the repair wiring position. 2
Connect to 1. The correction line 21 is connected to a desired circuit (not shown). As described above, according to the related art, the thick film connection pad leading to the short-circuit failure and the position p1 of the lead-out pad for electrically drawing out the short-circuit failure, the wiring cut position p2 for separating the short-circuit failure from the circuit, and Since all of the intermediate pad positions p3 for connecting the terminal connection pads 12 in the upper layer were located at different positions, the mounting efficiency of the circuit and the modified production efficiency were extremely undesirable.

On the other hand, according to the present invention, as shown in FIG. 5, the contact hole 5 formed on the thick film connection pad 4 leading to the short-circuit failure is filled with the insulator 6, and the contact hole 5 is formed thereon. The intermediate pad 7 and the terminal connection pad 12 in the upper layer are further formed thereon at the unique position p1. That is, the thick film connection pad 4, the contact hole 5 filled with the insulator 6, the intermediate pad 7, and the terminal connection pad 12 in the upper layer are located at the same position in plan view and substantially linearly in the stacking direction (substantially concentric). The insulating separation between the intermediate pad 7 and the thick film connection pad 4 is performed by the insulator 6, and the connection with the terminal connection pad 12 in the upper layer is performed by the connection pad 7.
It is done directly from. All the intermediate pads 7 have a pattern 7 ′ for connection with a repair line pattern 8 formed extending in substantially one direction between the intermediate pads 7, and the repair conductor 15 is used for repair wiring. At the position p3, it can be connected to the correction line pattern 8. As described above, according to the present invention, when the circuit needs to be repaired, the insulation is secured by the insulator 6 in the contact hole 5 and the repair conductor 1 is connected to the pattern 7 ′ and the repair line 8.
5, and the correction line pattern is connected to a desired circuit. Therefore, the part 24 of the pattern 23 for pattern cutting and the pattern cutting position and the operation thereof in the conventional device become unnecessary, and the connection pad 28 for connection to the upper-layer terminal connection pad 12 in the conventional device is eliminated. Since it is not necessary to provide the connection pads at different positions, the area of the connection pads 28 is not required, so that the number of connection pads can be increased and high-density mounting can be achieved, and all pads can be formed at the same position. This is very advantageous in the production process.

Further, the present invention will be described with reference to FIG. It is configured by incorporating a plurality of multilayer wiring circuit boards 31 on which a large number of LSI chips 14 are mounted into a printed circuit board 35. The multilayer wiring circuit board 31 is formed by forming the thin film wiring layer 2 on the ceramic circuit board 1. The correction wire 32 (for example, a polyurethane-coated Au wire in which only the joints at both ends are removed) is provided between the two correction lead patterns 8 ′ and 8 ″ on the thin film wiring layer 2 of the multilayer wiring circuit board 31. It can be corrected by circuit bonding, and the open circuit defect pattern 36 on the printed circuit board 35 can be corrected.
In the case where a and 36b are present, a disconnection has occurred, and a wire for correction (a polyurethane-coated Au wire in which the coating is removed only at the joints at both ends) is provided between the open circuit defect pattern 36a and the open circuit defect pattern 36b. It can be corrected by joining at 37. Further, in the printed circuit board 35, the short circuit defect portion 41 in which excess metal exists between the circuit patterns 39 and 40 can be removed and corrected by irradiating a laser beam or the like. In this regard, the short-circuit defect (short-circuit defect) due to excess metal is similarly removed and corrected in the conductive film such as the intermediate pad 7 in the thin film wiring layer 2 formed on the ceramic circuit board 1 (step shown in FIG. 7). SPn +
2) Can be. Also, for defects such as pinholes in the insulating layers 10 and 11, a small amount of insulating resin is applied,
It can be corrected by solidification. Each of the above-mentioned corrections shows an embodiment of the correction in which the correction required portion and the correction execution portion match.

Next, a specific rescue method for the ceramic circuit board 1 will be described with reference to FIGS. 6 and 7 show a production flow of the entire electronic circuit module device shown in FIG. 1, and FIG. 6 shows a process until a multi-chip module in which a large number of LSI chips are mounted on a ceramic circuit board. FIG. 7 shows a process for producing an electronic circuit module device by mounting a multichip module on a printed circuit board.

In the production flow of the ceramic circuit board 1 shown in FIG. 6, the steps from the production of the green sheet (SC1) to the firing of (SC7) are performed by the ceramic circuit board 1 serving as the base substrate of the multilayer circuit board shown in FIG. Be produced. That is, the step (SC1) indicates a green sheet manufacturing step. The step (SC2) shows a step in which a hole is formed in the green sheet manufactured in the step (SC1) by a pin press for forming a large number of through holes. Process <SC
3> indicates a step of inspecting a through hole or the like drilled in the step (SC2). Step (SC4) is an inspection step (S
A metal paste printing step of embedding a conductor in a through hole formed in a green sheet determined to be non-defective in C3) and forming a wiring pattern on the surface of the green sheet is shown. In this step (SC4), a thick film connection pad (having a shape close to a rectangular shape) 4 is printed on the uppermost green sheet, and a metal pattern connected to the input / output pins 33 is printed on the lowermost green sheet. 101 is printed. Step <SC5> indicates a step of inspecting the metal paste or the like printed in step (SC4). If it is determined in the inspection step <SC5> that the metal paste is defective, it is necessary to correct the printed metal paste. The step (SC6) shows a lamination / connection step of stacking a number of green sheets determined to be non-defective in the metal paste or the like printed in the inspection step <SC5> and connecting desired through holes. The step (SC7) shows a step of forming the ceramic circuit board 1 by firing a number of green sheets laminated and bonded in the step (SC6).

The ceramic circuit board 1 manufactured as described above is subjected to the electrical circuit inspection process of <SC8>, such as a short-circuit failure and a disconnection failure of a wiring pattern including through holes inside the fired ceramic circuit board 1. Is inspected. That is, in this electric circuit inspection step <SC8>, short-circuit defects, disconnection defects, and the like of the wiring pattern including through holes inside the fired ceramic circuit board 1 are inspected. However, as described above, since a large number of green sheets formed by printing high-density wirings are manufactured by laminating and sintering, drilling is performed in the state of the ceramic circuit board 1 alone. It is impossible to correct the short-circuit defect 9 or the disconnection defect without damaging the inner wiring by performing the process. From the insulating material application step (SC9) to the electric circuit detection inspection step <SC22> shown in FIG. This is a correction execution process, the detailed flow of which is shown in FIGS.
Is shown in

FIG. 10 shows a step G1 shown in FIG. 8 and FIG.
7 shows the transition of the cross section of an example of the multilayer wiring circuit board produced through the steps of forming and repairing the thin film wiring layer 2 from step G6 to step G6. That is, the step (S
C9) shows an insulating material applying / baking step of applying and baking the insulating layer 102 and the insulating layer 103 in order to protect the metal pattern 101 formed on the back surface of the ceramic circuit board 1. Next, step <SC10> in step G1
Is a pattern inspection including a short / open inspection of the thick film connection pad 4 on the surface and a pinhole inspection of the insulating layers 102 and 103. Relief correction process [SC10-
1] is to fill the pinholes of the insulating layers 102 and 103 and to relieve the short / open of the thick film connection pad 4 on the surface. The pattern inspection step <SC10-2> is a confirmation inspection after the above-described rescue.

Next, step (SC11) in step G2
Is an insulating material applying / baking step in which the first insulating layer 10 is formed on the surface of the ceramic circuit board 4 having the thick film connection pads 4 by applying the insulating layer 104 and the insulating layer 105 in two separate steps, followed by baking. Is shown. Thus, the first insulating layer 10
Is formed twice to prevent pinholes. Thereafter, the step (SC12) in the step G2
3 shows an insulating layer pattern forming step of forming concentric contact holes 5 in the first insulating layer 10 so as to correspond to the thick film connection pads 4 by a photolithographic process. Thereafter, a step <SC13> in the step G2 shows a pattern inspection step of inspecting the contact hole 5 and inspecting a pinhole on the first insulating layer 10. As shown in FIG. 2, FIG. 3, and FIG. 11, the remedy repair (a small amount of insulating resin) step [SC13-1] is performed to connect the thick film connected to the internal wiring 3b causing the short-circuit failure (short-circuit defect) 9. Pad 4
An extremely small amount of an insulating resin such as a polyimide resin is supplied to the inside of the contact hole 5d corresponding to d by an insulating resin minute feeder configured so that the injection nozzle can be finely moved in the xyz direction by a manipulator. The thick film connection pad 4d is cut off from the upper layer wiring (intermediate pad 7d) to be formed in the next step by burying as an insulator 6 and solidifying (heating cure) by local heating with a laser beam. FIG.
In order to insulate the inside of the contact hole 5k corresponding to the thick film connection pad 4k, the injection nozzle can be finely moved in the xyz direction by a manipulator by an insulating resin micro-feeder for insulating polyimide resin or the like. A very small amount of resin is supplied to bury the insulator 6 and solidified (heat-cured) by local heating with a laser beam to form the upper layer wiring (intermediate pad 7) for forming the thick film connection pad 4k in the next step.
The case of disconnecting from k) is also shown. That is, FIG. 11 shows a case where there are two thick film connection pads that need to be corrected. In this step [SC13-1], the contact hole 5d is not formed by spot exposure (the contact hole 5d is not drilled), so that the thick film connection pad 4d is formed in the next step. It can be separated from the pad 7d). Pattern inspection process <S
C13-2> is a step of checking whether or not the contact hole 5d corresponding to the thick film connection pad 4d is filled with the insulator 6.

Next, the step (SC14) in the step G3
Is to form a conductive film such as Cr on the surface of the contact hole 5 and the first insulating layer 10 which are not filled with the insulator 6 by a sputtering method, and then to form an intermediate pad (rectangular shape) which is a predetermined circuit pattern. And a correction line pattern 8 extending between the intermediate pads so as not to intersect with each other. Exposure is performed using a pattern determined using a mask or the like. The repair conductor line 15 is subjected to spot exposure, and then developed and etched to form the intermediate pad 7 and the repair line pattern (lead line pattern) 8 and to form the intermediate pad 7d and the repair line pattern. The repair conductor line 15 is left unetched between 8d and 8e. Showing the connection to) the circuit pattern formation step. In the circuit pattern forming step (SC14), the intermediate pad (the one having a shape close to a rectangular shape and the one close to a circular shape) 7 has a pattern 7 'as shown in FIG. Pad 7 is thick film connection pad 4
And are basically formed concentrically. That is, in the circuit pattern forming step (SC14), the intermediate pad 7 is formed at all the positions of the contact holes 5 by the thin film process, and the correction line pattern 8 and the connection conductor line 15 are formed. Defects can be corrected. 12, a repair conductor line (metal pattern such as Cr) 15 is used between the intermediate pad 7d separated from the thick film connection pad 4d by the insulator 6 and the repair line pattern 8e corresponding to FIG. A repair conductor line 15 is used to connect between the intermediate pad 7k separated from the thick film connection pad 4k by the insulator 6 and the repair line pattern 8e 'by using the repair conductor line 15 and the repair line pattern 8e and the repair line. The correction line pattern 8e and the correction line pattern 8e 'are separated by irradiating a slit-like laser beam focused between the correction line pattern 8e' and the correction line pattern 8e '. Connect with the opponent's correction line pattern to be done. As a result, a short-circuit defect generated in the ceramic circuit board 1 can be repaired in the thin-film wiring layer 2. That is, in FIG. 12, as shown in FIG. 11, the two intermediate pads 7d and 7k are cut by irradiating a focused slit-shaped laser beam to one correction line pattern 8e. Each line segment pattern 8e, 8
e 'indicates that they are connected by the connection conductor lines 15 and 15', respectively. Step <SC in Step G3
15> is a pattern inspection step of inspecting the intermediate pad 7, the repair line pattern 8, and the repair conductor line 15, which are circuit patterns. Relief correction process [SC15
-1] indicates that the focused laser beam is detected when a short-circuit defect or foreign matter is detected in the intermediate pad 7, the repair line pattern 8, and the repair conductor line (metal pattern such as Cr) 15 in the pattern inspection step <SC15>. It can be removed by irradiating light. The pattern inspection process <SC15-2> includes a repair repair process [SC1
5-1] to confirm that it has been corrected.

Next, as shown in FIG. 9, in the step (SC16) in the step G4, the intermediate pad 7 as a circuit pattern is formed.
And the second insulating layer 1 on the repair line pattern 8 and the like.
1 shows a process of applying and baking an insulating material formed by applying and baking. Thereafter, a step (SC17) in step G4
Shows an insulating layer forming step of forming a contact hole 18 concentrically in the second insulating layer 11 so as to correspond to all the intermediate pads 7 by a photolithography process. That is, step G
In 4, contact holes 18 are formed at positions of all the intermediate pads 7 on the second insulating layer 11. Then process G
Step <SC18> in Step 4
And a pattern inspection step for inspecting a pinhole on the second insulating layer 11. Relief correction process [SC18
-1] indicates that an excimer laser beam or the like is applied when foreign matter or the like adheres to the intermediate pad 7 in the contact hole 18 or foreign matter such as a metal or a resist exists on the second insulating layer 11. And removes and corrects only foreign matter without damaging the intermediate pad 7 (without damaging the intermediate pad 7). It is confirmed that the pattern inspection step <SC18-2> has been corrected in the repair correction step [SC18-1].

Next, the step (SC19) in the step G5
Is a method in which the terminal connection pad 12 is basically plated concentrically with the intermediate pad 7 by electroless plating and the base is plated with Ni.
A circuit pattern forming step of forming an Au plating thereon to form a circuit pattern will be described. That is, in the circuit pattern forming step (SC19), the terminal connection pads (usually having a shape close to a circle) 12 to which the terminals of the LSI chip 14 are connected by the bonding member 13 such as a brazing material are formed. The intermediate pad 7 and the terminal connection pad 12 are connected concentrically. Of course, the plating on the second insulating layer 11 between the terminal connection pads 12 is removed. Then, in a step <SC20>, a pattern inspection is performed on the terminal connection pads 12 and the like. In this pattern inspection process <SC20>,
If a foreign matter such as a resist is attached to the terminal connection pad 12 or the like, the terminal connection pad 12 is not damaged by irradiating an excimer laser beam or the like (terminal connection) in the repair and repair step [SC20-1]. Only the foreign matter is removed and corrected (without damaging the pad 12). As described above, in the state of the conductive film such as Cr, the correction line pattern (drawing line pattern) 8b (8 ') and the other party's correction line pattern (drawing line pattern) 8e
In the case where it is not possible to connect (8 ″), as shown in FIG. 1, a focused excimer laser beam is radiated to make a hole in the second insulating layer 11 so as to make two corrections. The ends (pads) of the lead patterns 8b (8 ') and 8e (8 ") are exposed, and a bonding wire is connected between the two ends (pads) using a correction wire 32. Defects can be corrected by supplying a very small amount of an insulating resin such as a polyimide resin with a supply device and sealing with an insulator. Then, the pattern inspection process <SC2
In 0-2>, it is confirmed that the correction has been made.

The above steps G1, G2, G3, G4
Pattern inspection process in G5 <SC10>, <SC1
3>, <SC15>, <SC18>, and <SC20>, all the foreign substances determined as foreign substances (particularly, foreign substances existing on the conductor pattern and foreign substances such as metal and resist existing on the insulating film) are subjected to each of the repair steps. [SC10-1], [SC1
3-1], [SC15-1], [SC18-1], [S
By excimer laser light irradiation at C20-1], removal correction is performed corresponding to an arbitrary area and thickness. Next, in a step (SC21) in the step G6, the insulating layers 102 and 103 formed on the back surface of the ceramic circuit board 1 for protecting the metal pattern 101 are removed, and the input / output pins 33 are set. The steps will be described. Thereby, the multilayer wiring circuit board 31 is completed. Thereafter, in a step <SC22>, an electric circuit inspection (electrically inspecting the conductive net pattern including the ceramic circuit board 1) is performed, and the production process of the multilayer wiring circuit board 31 is completed. In the process (SC23), the multilayer wiring circuit board 31 completed in this manner is manufactured,
The inspected electronic component 14 such as an LSI chip is mounted using the joining member 13 such as a brazing material, and is heated and reflowed in the step (SC24) to obtain a multilayer wiring circuit board module (multi-chip module).

Note that, as shown in FIG.
4 is manufactured through steps SL1 to SLn. Step (S
L1) indicates a circuit patterning step. Process <SL
2> shows an inspection step of circuit patterning. The step (SL3) shows an exposure and exposure step. Process <SL4>
Indicates an inspection step. Step (SL5) shows an etching step. Step <SL6> indicates an inspection step. ...
Step <SLn> indicates an electric circuit function inspection step of the LSI chip. Next, a step <SC25> shown in FIG. 7 shows a function inspection step of the multilayer wiring circuit board module (multi-chip module). The short circuit (short circuit) and open mode (disconnection) determined in the function inspection process <SC25> are improved by improving the quality of the assembly process of the multilayer wiring circuit board module (multi-chip module) (that is, measures against dust and work failure). The pass rate can be made as close as possible to 100 (by preventing the occurrence of defects due to stability). If a short circuit (short circuit) or open mode (disconnection) occurs in the function inspection process <SC25>, it is necessary to correct it as follows. That is, it can be corrected based on the embodiment shown in FIG. However, when a customer request or a fundamental change in design occurs, the function in the function inspection step <SC25> is not satisfied, and the request is made through the steps (SC25-1) to <SC25-6> shown in FIG. Reproduction that satisfies the functions can be performed within a range in which the wiring connection and the wiring cutting can be performed with the actual thing and the electric circuit is satisfied.
That is, if a customer's request or a fundamental change in the design can be achieved by a combination of the contents of the LSI chip and the wiring connection and the wiring disconnection in the thin film wiring layer 2 of the multilayer wiring circuit board 31 currently being assembled, the reproduction satisfying the required function can be performed. Can be realized.

FIG. 13 shows a special reproducing embodiment. FIG.
LSI chip 14 of the multi-chip module indicated by
In the part removing step (SC25-1) shown in FIG. 7, the bonding member 13 such as a brazing material is locally heated and removed by irradiating a laser beam, and the correction line pattern 8a is formed around the exposed terminal connection pad 12a. And the insulator on the intermediate pad 7a (part of the second insulating layer 11) is partially removed by excimer laser processing to expose a part of the intermediate pad 7a and a part of the repair line pattern 8a, The correction line pattern 8a and the intermediate pad 7a are formed by a bonding metal foil 120 such as a gold foil.
Are metallurgically joined by ultrasonic heating. A dam 121 for preventing the spread of the brazing material is formed by a slit having a width of about 10 μm by excimer laser processing, and a bonding metal foil 120 (for example, Au foil) such as a gold foil is formed by a brazing material (solder) when the area of the LSI chip 14a is reattached. To prevent the spread of creatures. Then, a very small amount of insulating resin such as a polyimide resin is supplied by an insulating resin minute supply machine, and the insulating resin 109 ′ is filled and solidified by heating curing. And FIG.
As shown in FIG. 5, the repairing line pattern 8a and the partner's repairing line pattern connected in this manner can be connected using the repair wire 32 in the same manner as described above. After this, through the inspection process <SC25-3>, the component mounting process (SC25-4) and the local heating reflow process (SC25-
5) joining the LSI chip 14a to the joining member 1 such as a brazing material,
3 allows the microchip module to be mounted and mounted on the surface of the multilayer wiring circuit board 31. Thereafter, an inspection process <SC25-6> is performed to complete the correction or the function change.

Next, a case where a fundamental logical change (function fulfillment / change) of a customer request or design occurs will be described with reference to FIG. That is, a typical logical change (function fulfillment / change)
A description will be given of a case where the logic is changed using an empty pad (empty terminal) (shown in FIG. 15B) formed in the LSI chip 4b. As shown in FIG. 15B, before the logical change, for example, the LSI chip 14b
Are connected between the pads (terminals) of the LSI chip 14b and the input / output pins (b).
It is assumed that the connection is made between On the other hand, for example, by using an empty pad existing in the LSI chip 14b, the input / output pins (A)
Is changed to connect the signal to be connected to the empty pad. For this purpose, first, the LSI chip before the logic change is removed using the process <SC25> shown in FIG. 7 and replaced with the new LSI chip 14b whose logic has been changed as described above. On the other hand, several through-through lines 151 are formed on the multilayer wiring circuit board 31 so as to correspond to the respective LSI chips 14. In addition, the intermediate pad 7 in the empty pad and the line pattern for correction (line pattern for drawing)
8t is to be connected and formed in the circuit pattern forming step (SC14) when the thin film layer 2 is formed. If there is no connection between the intermediate pad 7 and the correction line pattern (lead line pattern) 8t in the vacant pad, it is necessary to connect them by the method shown in FIG.

First, in a step (25-1) shown in FIG. 7, the LSI chip before the logic change is removed. Then, in the step (25-2), a circuit correcting operation described below is performed. That is, on the surface of the multilayer wiring circuit board 31, the repair is performed between the exposed terminal of the repairing line pattern (leading line pattern) 8t connected to the empty pad and the exposed terminal of the through-through line 151. The connection is made using a repair wire (for example, a polyurethane-coated Au wire) 152 in the same manner as the connection of the wire 32. Further, on the back surface of the multilayer wiring circuit board 31, between the exposed terminal of the through-hole 151 and the terminal of the input / output pin (a), the repair wire 153 is used in the same manner as the connection of the repair wire 32. Connect. However, LSI chip 14
Since the pad is connected between the pad b and the input / output pin (a), it is usually necessary to disconnect the pad. On the other hand, the connection between the terminal to which the input / output pin 33 is attached and the conductor of the ceramic circuit board 1 is shifted laterally from the position where the input / output pin 33 is attached as shown in FIG. . Therefore, by irradiating excimer laser light at 154 locations (areas), for example,
The connection between the pad of the LSI chip 14b and the input / output pin (a) can be cut off by cutting the terminal portion to which the 3 is attached. Then, after cutting, to the cut location, an ultra small amount of insulating resin such as polyimide resin is supplied by an insulating resin minute supply machine,
The protective film can be formed by filling the insulating resin and solidifying it with a heating cure. Of course, when it is not necessary to disconnect the connection between the pad of the LSI chip 14b and the input / output pin (a), there is no need to perform this disconnection work. The above is the circuit correction work. Next, in the step <25-3>, a confirmation inspection of the circuit repair work is performed, and then the step (25-
The LSI chip 14b whose logic has been changed in 4) is mounted, and in step (25-5), the LSI chip 14b is locally heated using a laser beam or the like, and the LSI chip 14b is joined to a joining member 13 such as a brazing material.
Is mounted and mounted on the surface of the multilayer wiring circuit board 31,
The logical change operation ends.

In the above-described logic change, for example, with the pads of the LSI chip 14b connected to the input / output pins (a), new logic (wiring) is formed between the printed circuit board 35 and the empty pads of the LSI chip 14b. ) Is added, and if the through-through line 151 remains and can be used, the through-through line 15
The connection between the terminal exposed on the back surface of the multilayer wiring circuit board 31 and the desired terminal on the printed circuit board 35 in FIG. Naturally, the chip is replaced with a new LSI chip whose logic has been changed using an empty pad.

If the through line 151 formed on the multilayer printed circuit board 31 cannot be used in the above logical change, the repair line pattern 8 connected to the empty pad on the surface of the multilayer printed circuit board 31 is not used.
What is necessary is just to connect between the exposed terminal of t and the desired terminal on the printed circuit board 35 using a repair wire.
In the above-mentioned logic change, as a last method in which no empty pad remains in the LSI chip 14b and the empty pad cannot be used, the method can be performed by the method shown in FIG. In other words, when a customer's request or a fundamental logical change of the design occurs, the bumps (terminals) 52 of the LSI chip 14 are connected to the multilayer wiring circuit board 3 via the wire 58.
1 and is connected to the pattern 53 of the printed circuit board 35 while being insulated by the insulating coat 54. 50 and 51 are L
2 shows bumps (terminals) of the SI chip 14. 50 ', 5
1 'and 52' are bumps 50 of the LSI chip 14, which are mainly caused by design changes occurring in the component mounting step (SC23) shown in FIG. 1 shows an embodiment of a design change. In this embodiment, the L
The function change is realized by connecting the bump 52 of the SI chip 14 to the pattern 53 of the printed circuit board 35 by the wire 58. Thus, the rescue method shown in FIG. 16 is performed when the urgency is high. If you try to ship the product without wiring from the beginning, the schedule will be delayed by the order of 1 to 3 months, but if you take the rescue method shown in FIG. It is very effective in shortening the schedule.

A case where a logic change is performed between the LSI chips by using an empty pad will be described. In this case, on the surface of the multilayer wiring circuit board 31, between the repair line pattern (lead line pattern) connected to the empty pad of each LSI chip, the repair wire 3 shown in FIG.
2, the logic can be changed between the LSI chips. In this case, if the pads used in the LSI chip before the logic change remain connected to the conductors (wirings) in the ceramic circuit board 1 in the LSI chip after the logic change, the pads are vacant if they cause trouble. It is necessary to take measures such as whether to use a pad (separated pad) or to eliminate the bonding material 13 at this portion. When the empty pad is not connected to the correction line pattern (lead line pattern) as described above, it is necessary to connect the pads by the method shown in FIG.

The function fulfillment / change (logic change) based on a request from a customer or a design change is made by the ceramic circuit board 1.
If it is known before forming the thin film layer 2 thereon, the thin film layer 2 can be removed as shown in FIGS. It can be repaired while forming. For example, it is not necessary to use the method shown in FIG.

On the other hand, the method shown in FIG. 15 can also be used to correct a defect generated when the ceramic circuit board 1 is manufactured. That is, an open defect (open defect) or a short defect (short defect) between wiring patterns (interlayers) generated inside the ceramic circuit board 1 between the thick film connection pad 4 on the surface and the terminal to which the input / output pin 33 is attached. Can be repaired by using the through line 151.

For example, if an open defect exists between the thick film connection pad corresponding to the pad and the terminal corresponding to the input / output pin (a), the intermediate pad 7 and the repair line pattern (lead line pattern) At the time of forming the pad 8, the intermediate pad corresponding to the pad and the repairing line pattern (leading line pattern) 8 were connected using the repair conductor line 15, and then the terminal connection pad 12 was formed. Later, line pattern 8 for correction
The two ends of the repair wire 152 are bonded and connected between the terminal exposed on the front surface of the wire and the terminal exposed on the surface of the through-hole 151 as desired, and further exposed on the back surface of the through-hole 151. Ends of the repair wire 153 between the connected terminal and the terminal to which the input / output pin (a) is attached (this terminal is connected to the thick film connection terminal 155 formed on the back surface of the ceramic circuit board 1). Can be repaired by bonding. The connection between the repair line pattern 8 and the through-through line 151 on the front side is performed by etching a conductive film such as Cr in the same manner as the connection using the repair conductor line 15 as shown in FIG. Can be realized by not removing them. Also on the back side, the connection between the terminal to which the input / output pin (a) is attached and the through-through line 151 is
This can be realized by not removing the conductive film by etching, as in the case of using the repair conductor line 15 as shown in FIG. However, when the pattern of the terminal to which the input / output pin (a) is attached is formed when the ceramic circuit board 1 is manufactured, a bonding connection using the repair wire 153 has to be taken.

As for the short-circuit defect, the insulator 6 is interposed between the intermediate pad 7 and the thick film connection pad 4, and the terminal to which the input / output pin 33 is attached as necessary is cut (cut) using an excimer laser beam. ) Can be repaired using the through-through line 151 in the same manner as described above.

The embodiments of the present invention described above are classified and arranged as follows. That is, the correction of the multichip module according to the present invention includes correction of defects (manufacturing process defects) generated in the manufacturing process and fulfillment / change of functions (logical change) based on customer requirements and design changes. (1) First, correction of a manufacturing process defect will be described with reference to FIGS. First, the ceramic circuit board 1
There is an open portion O and a short portion S of the conductor wiring which cannot be exposed inside the inside. 18c in FIG. 18 corresponds to this restoration. About the open part O,
A repair line pattern (lead line pattern) A- drawn out from the intermediate pad and exposed in the thin film layer 2 corresponding to the wiring patterns a and b related to the open portion O
At A ′ (8 ′) and BB ′ (8 ″), both ends of the covered wire (repair wire) 32 are bonded between A ′ and B ′ as shown in FIG. As for the short spot S, the wiring patterns c / d,
Corresponding to e / f, the repair line pattern (lead line pattern) C- which is drawn out from the intermediate pad and exposed while avoiding a short circuit through the insulator 6 in the thin film layer 2 is interposed.
C '/ DD' (8 '/ 8 "), EE' / FF '
At (8 '/ 8 "), both ends of the covered wire (repair wire) 32 are bonded between C' and D 'and between E' and F 'as shown in FIG.

These are all ceramic circuit boards 1
Is used between the thick film connection pads 4 on the front surface of the ceramic circuit board 1 and the terminals through which the input / output pins 33 on the back surface are attached. This can be similarly restored. Next, a case where an exposed manufacturing process defect is repaired as shown by 18a in FIG. 18 will be described. As shown in FIGS. 8 and 9, each step G1 is formed on the ceramic circuit board 1.
To G5 while sequentially forming patterns, each pattern inspection step <SC10><SC13><SC15><SC1
8> Defects (open defects, short defects) found in <SC20> are removed from each repair repair process [10-1] [1]
3-1] [15-1] [18-1] [20-1] correspond. Since all of them are exposed, open defects caused by the presence of foreign matters such as resists are exposed by irradiating excimer laser light or the like with a very low energy density so that only foreign matters such as resists are peeled off. By removing foreign matter such as resist without damaging conductive patterns such as pads,
Foreign matter such as resist does not exist between conductor pattern layers such as pads, and connection between conductor patterns becomes possible. For an open defect caused by disconnection of the conductor pattern, metallurgical bonding is performed by ultrasonic heating using a bonding metal foil 120 such as an Au foil shown in FIG. 13, or energy beam CVD or metal ion irradiation is performed. In this way, it is also possible to form a conductive film locally so that connection can be made on the surface. In addition, a short-circuit defect caused by the presence of a foreign substance such as a metal can be repaired by irradiating a laser beam or the like having a high energy density to remove the foreign substance such as a metal. When a short defect exists in the conductor pattern itself, the laser beam focused and projected only on the short defect can be irradiated to cut the surface to repair the defect.

Next, a description will be given of a case of repairing a manufacturing process defect in a case where the manufacturing process defect can be exposed by a manufacturing process defect generated inside as shown by 18b in FIG. That is, after forming the thin film layer 2 on the ceramic circuit board 1, for example, a manufacturing process defect in the thin film layer 2 found in the electric circuit detection and inspection process <SC22> or a function inspection process after mounting the LSI chip 14 <SC25> For example, this corresponds to the case of repairing a manufacturing process defect in the thin film layer 2 found in. For open defects, for example, see FIG.
3 using the method shown in FIG. 3 or using the energy beam C
Irradiation with VD or metal ions can repair the conductor film instead of local deposition.
For short defects, if this short defect part can be exposed, a laser beam focused and projected on the short defect area is used to dig a hole, and then the short defect is cut. Can be repaired by filling and solidifying. When performing this repair work, the LSI chip 14 is removed and the LSI chip 14 is removed.
If it is necessary to mount the, this operation shall be performed. In the case where exposure is not possible, 18c in FIG.
The repair work indicated by is performed.

(2) Function fulfillment / change (logical change) based on a customer request or design change will be described with reference to FIG. Normal function fulfillment / change (logical change) is a logical change, and therefore consists of logical connection and logical disconnection. by the way,
Since the logic cannot be changed inside the ceramic circuit board 1, the logic is changed inside the LSI chip (element) 14 shown by 19c in FIG. Therefore, when the logic is to be changed after mounting the LSI chip (element), the mounted LSI chip before the logic change is removed, and the newly changed LSI chip (element) is mounted. In a new LSI chip (element), function fulfillment / change (logic change) including normal logical connection and logical disconnection (cut) is performed between input / output pads inside the functional element. However, in the case of adding or deleting logic, the logic change may consist of only connection of logic or disconnection of logic. This logical change is often made using an empty pad as shown in FIG.

In the case where an empty pad is used, usually, FIG.
A logical change is made at the exposed location indicated by 9a. For example, as shown in FIG. 1, both ends of the repair wire 32 are connected by bonding between terminals of the repair line patterns (lead-out line patterns) 8 'and 8 "connected to the empty pads of each LSI chip. As shown in FIG. 15, both ends of the repair wire 152 are connected by bonding between the terminal of the repair line pattern 8 connected to the empty pad and the terminal exposed on the surface of the through-hole 151 as desired. Both ends of the repair wire 153 are bonded and connected between the terminal exposed on the back surface of the through-hole through line 151 and the terminal to which the input / output pin is attached, and excimer laser light is used at the terminal to which the input / output pin is attached. A logical change is made at a location exposed by cutting.

Further, there is a case where it is necessary to change the logic at the exposed portion shown by 19b in FIG. That is, the logical change at the exposed portion means that, for example, the intermediate pad 7 and the correction line pattern 8 are connected using, for example, the method shown in FIG. A connection is made by locally forming a conductor film by irradiating energy beam CVD or metal ions, and the logic is changed at an exposed portion indicated by 19c (the terminal of each correction line pattern 8 connected to the intermediate pad 7). Bonding connection using the repair wire 32 between
A bonding connection is made between the terminal of the repair line pattern 8 and the terminal exposed on the surface of the through hole 151 as desired using the repair wire 152,
Further, both ends of the repair wire 153 are bonded and connected between a terminal exposed on the back surface of the through hole 151 and a terminal to which an input / output pin is attached,
Cutting (cutting) using excimer laser light at the terminals to which the input / output pins are attached).

As described above, since the logic cannot be changed inside the ceramic circuit board 1, it is basically replaced with an LSI chip (element) 14 whose logic has been changed.
Next, a production system used for producing a multilayer wiring circuit board of a multichip module according to the present invention will be described with reference to FIGS.

As shown in FIG. 20, a thick film process 1310
(Steps (SC1) to (SC7) correspond to FIG. 6), thick film inspection step 1320 (corresponds to step <SC8> in FIG. 6), and thin film step 1330 (steps shown in FIGS. 8 and 9). G1 to G5 (step (SC9) to step <SC20>) correspond), thin film inspection step 1340
(Steps <SC10><SC13> shown in FIGS. 8 and 9)
<SC15><SC18><SC20><SC22>,
<SC25> shown in FIG. 7 corresponds to this. ), Correction process 13
50 (step [SC10-1] [S shown in FIGS. 8 and 9]
C13-1] [SC15-1] [SC18-1] [SC
20-1] and [SC25-2] shown in FIG. In each step of (1), production equipment 131 suitable for each
0a to 1350c (the thick film process 1310 includes a punching machine 1310a for forming a through hole in a green sheet, and a printing machine 1310 for printing a conductor pattern on a green sheet.
b, and a sintering furnace 1310n for sintering the laminated green sheets to form a ceramic circuit board. In the inspection step 1320, a continuity inspection machine 1320a for performing a continuity inspection is installed. In the thin film process 1330,
A polymer applicator 1330a for applying a polymer resin such as a polyimide resin to form an insulating film (insulating layer), an exposing machine 1330b for exposing a circuit pattern and the like, and a developing machine 1330
m etc. are installed. In the inspection step 1340, a pattern inspection machine 1340a for inspecting a circuit pattern including foreign matter and the like is provided.
Inspection machine 13 for inspecting the continuity of wiring and wiring (conductor)
40b and the like are installed. In the correcting step 1350, an excimer laser processing machine 153 that performs a hole digging process on an insulating film, a foreign matter removing process, a cutting process for cutting a wiring pattern, and the like.
0a, an insulating resin micro-injector 1350b for injecting and supplying a very small amount of insulating resin, a spot exposing machine 1350c for performing spot exposure for stopping etching removal, and the like. ) Is used. These production equipment 1310a
As shown in FIG. 21, client computers 1410 to 1450 corresponding to the steps 1310 to 1350 of FIG. 20, server computers 1460 corresponding thereto, and a host computer 1470 that controls and controls the entire production, as shown in FIG. Controlled by a sex computer system. A feature of the present invention resides in that the correction step 1350 in FIG. 20 is integrated with the production system. Typical production equipment for the correction step 1350 is an excimer laser processing machine 1350a and an insulating resin minute supply machine 1350b.

The operation of the excimer laser beam machine 1350a is shown in the flowchart of FIG. Excimer laser processing machine 1
350a has been remarkably developed in recent years. By setting the energy per unit shot and the removal rate according to the material and the substance, the area to be processed is also 1 μm square in area and 0.1 mm in the thickness (depth) direction. A fine processing of about 1 μm is possible, and it can be effectively used for digging a hole in an insulating film of the thin film layer 2 in the multilayer wiring circuit board 31 according to the present invention, removing foreign matter, and cutting a wiring pattern. Can be. FIG. 2 shows the operation of the excimer laser beam machine 1350a.
This will be described according to the flowchart of FIG. That is, when the multilayer wiring circuit board 31 to be corrected is loaded as a work on the work table, the control unit sends the work number to the production control computer system, and the production control computer system sends the position coordinates of the correction location, processing Information such as conditions is received (1601). Next, the position coordinates and processing condition data for one correction point are read out (1603), the work table is driven and controlled to position the processing target area (1604), and the processing is performed according to the processing conditions. Set the conditions (160
5) Apply a laser to perform the required processing (160)
6). The excimer laser beam set to a desired processing condition is irradiated to the correction point of the workpiece by moving to the next correction point and repeating the above operation. The above-described processing operation is sequentially performed for all correction points, and when the correction is completed (1607),
The work is unloaded (1608).

FIG. 23 shows the basic configuration of an insulating resin minute injection machine (insulating resin minute supply machine) 1350b.
As described above, when the thin film layer 2 of the multilayer wiring circuit board 31 according to the present invention is formed, the insulation between the pads of the adjacent layers (between the thick film connection pad 4 and the intermediate pad 7) by the insulator 6 is realized. To do so, it is necessary that the contact hole 5 can be supplied with an insulating resin on the order of pl (picoliter). Therefore, a very small amount of insulating resin such as a polyimide resin is supplied by using a small amount of insulating resin injection machine 1350a composed of a micromanipulator capable of controlling the supply of a small amount of liquid (liquid amount injection) in an ultra small amount of fl (femtoliter). Realized. In FIG. 23, an insulating resin microinjector 135
0b mainly includes a control unit 1710 and a processing unit 1720. In the control unit 1710, reference numeral 1711 denotes a communication controller for exchanging information with the above-described production control computer system, and reference numeral 1712 denotes a processing unit 1720.
Is a device control interface for controlling the device. Processing part 17
In 20, reference numeral 1721 denotes a micro-moving mechanism of the above-described micromanipulator, 1722 denotes an injection unit having a coating amount control unit, 1723 denotes a work table on which a multilayer wiring circuit board of a work is placed, and 1724 denotes a resin injection position of the work by an image. Video monitor to monitor. Reference numeral 1725 denotes a tip manufacturing unit of the glass nozzle attached to the injection unit 1722.

Next, an insulating resin micro-injector 13 shown in FIG.
The operation of 50a will be described with reference to the flowchart shown in FIG. That is, when a multilayer wiring circuit board (a part of a thin film layer is formed on the ceramic circuit board 1) 31 to be corrected is loaded as a work on the work table 1723 (1801), the control unit 1710 causes The work number is sent to the production control computer system, and the position coordinate information of the correction location is received from the production control computer system (1802). Next, the device control interface 1712 reads out the position coordinate data for one correction point (1803), and
23 to control the position of the target area (1).
804), the nozzle is positioned (1805), and after supplying and injecting the insulating resin (1806), the nozzle is retracted (1807). The above operation is sequentially performed for all correction points, and when the correction is completed (1808), the work is unloaded (1809). The present invention
Although the embodiment applied to the multilayer wiring circuit module (multi-chip module) using the ceramic circuit board has been described in detail, the present invention is not limited to this, and the thin film process can be performed on a liquid crystal module or a silicon multilayer wiring circuit board. The present invention can be similarly applied to a silicon multilayer wiring circuit board module or the like in which a wiring is formed using the above method and a bare chip is mounted thereon.

[0064]

As described above, according to the present invention,
When it becomes necessary to relieve a manufacturing process defect or change a function, the original (same type as the original) multilayer wiring circuit board can be used effectively without recreating a new multilayer wiring circuit board to achieve the required quality and required level. This has the effect of enabling development and production of a multi-chip module that achieves functions in a short period of time. Further, according to the present invention, when it becomes necessary to relieve a manufacturing process defect or change a function, the original (same type) multilayer wiring circuit board can be effectively utilized without recreating a new multilayer wiring circuit board. , Increasing the yield of development and production, enabling the production of the required number and types of multi-chip modules with the required minimum number and types of multilayer wiring circuit boards, and the defective and unnecessary multilayer wiring circuit boards and multi-chip modules This produces the effect of minimizing or drastically reducing waste.

[Brief description of the drawings]

FIG. 1 shows a state in which a multi-chip module according to the present invention in which a manufacturing process defect has been corrected is mounted on a printed circuit board in which a manufacturing process defect has been corrected, and a multi-chip module in which function fulfillment / change (logical change) has been performed is referred to as a manufacturing process defect. FIG. 11 is a perspective view showing a state in which the device is mounted on a printed circuit board in which is modified.

FIG. 2 shows an electronic component (LSI) on a thin film layer of a multilayer wiring circuit board according to an embodiment in which a manufacturing process defect according to the present invention is corrected.
FIG. 4 is a cross-sectional view showing a state where a chip is mounted.

FIG. 3 is a cross-sectional view mainly showing an inner thin-film layer of a multilayer wiring circuit board in each repair production process which is a first embodiment for repairing a manufacturing process defect according to the present invention.

FIG. 4 is a plan view of a correction pattern portion in a comparative example,
FIG. 4 is a partial cross-sectional view of a multilayer wiring circuit board on which a correction pattern has been applied.

FIG. 5 is a plan view of a correction pattern portion when an embodiment according to the present invention is implemented, and a partial cross-sectional view showing a thin film layer of a multilayer printed circuit board on which the correction pattern has been applied.

FIG. 6 is a diagram showing a production flow until a multilayer wiring circuit board circuit module (multi-chip module) in which an LSI is mounted on a multilayer wiring circuit board formed by forming a thin film layer on a ceramic circuit board according to the present invention. It is.

FIG. 7 is a diagram showing a production flow until a multilayer wiring circuit board circuit module (multi-chip module) according to the present invention is mounted on a multilayer printed circuit board.

FIG. 8 is a detailed flowchart of the first half of the correction step of FIG. 6;

FIG. 9 is a detailed flowchart of the latter half of the correction step of FIG. 6;

FIG. 10 is a sectional view mainly showing an inner thin film layer of a multilayer wiring circuit board in each repair production process which is a second embodiment for repairing a manufacturing process defect according to the present invention.

FIGS. 11A and 11B are a plan view and a cross-sectional view showing an embodiment in which an insulator is formed in a through hole on a thick film connection pad when correcting a manufacturing process defect according to the present invention.

FIG. 12 is a plan view showing an embodiment in which a repair conductor line between an intermediate pad insulated with an insulator and a repair line pattern (lead line pattern) is used to repair a manufacturing process defect according to the present invention. It is a figure and a sectional view.

FIG. 13 is a diagram illustrating a method for correcting a manufacturing process defect according to the present invention and performing a function fulfillment / change (logic change) between a middle pad and a repair line pattern (lead-out line pattern) using a bonding metal foil; 3A and 3B are a plan view and a cross-sectional view illustrating an example of connection in FIG.

FIG. 14 is a diagram showing a method of correcting a manufacturing process defect and performing a function fulfillment / change (logic change) according to the present invention. FIG. 4 is a perspective view showing an example of connection between the first embodiment and a line pattern.

FIG. 15 is a diagram showing a front surface, a cross section, and a back surface showing an embodiment in which manufacturing process defects are corrected and functions are satisfied / changed (logical changes) between pads and input / output pins of an LSI chip according to the present invention.

FIG. 16 is a perspective view showing an embodiment in which a manufacturing process defect is corrected and a function is satisfied / changed (logical change) between a pad of an LSI chip and a printed circuit board according to the present invention.

FIG. 17 is a perspective view for explaining a method of correcting a manufacturing process defect occurring in the ceramic circuit board according to the present invention.

FIG. 18 is a diagram collectively showing in a table form a method of correcting a manufacturing process defect according to the present invention.

FIG. 19 is a diagram collectively showing, in a table form, a function fulfillment / change (logical change) method performed in accordance with a customer request or a design change according to the present invention.

FIG. 20 is a block diagram of a control device showing an embodiment of the production system according to the present invention.

FIG. 21 is a block diagram of a production control computer system showing an embodiment of the production system according to the present invention.

FIG. 22 is a view showing an operation flow of the excimer laser beam machine according to the present invention.

FIG. 23 is a block diagram showing a configuration of an embodiment of an insulating resin micro-injection machine used in the production system according to the present invention.

FIG. 24 is a diagram showing an operation flow of the small amount injection machine of insulating resin shown in FIG. 23;

[Explanation of symbols]

1. Ceramic circuit board 2. Thin film wiring layer 3.
Internal wiring pattern 4 ... Thick film connection pad 5, 25 ... Contact hole 6 ... Insulator, 7 ... Intermediate pad 8, 8 ', 8 "... Repair line pattern (lead-out line pattern) 9 ... Short-circuit defect (Short defect ), 10: first insulating layer 11: second insulating layer, 12: terminal connection pad, 13
... joining material 14 ... electronic parts (LSI chip, element) 15 ... repair conductor line 31 ... multilayer wiring circuit board 32, 37, 152, 15
3: repair wire 33: input / output pin, 34: connector, 35: printed circuit board 36a, 36b: open circuit defect pattern, 39,
40: circuit pattern 41: short circuit defect, 109: insulating resin, 12
0: bonding metal foil 121: dam, 151: through-through line, 1
54: cutting region 155: thick film connection terminal 1310: thick film process, 1320: thick film inspection process, 1
330: Thin film process 1340: Thin film inspection process, 1350: Correction process, 1350a: Excimer laser processing machine, 1350b: Insulating resin micro injection machine 1410 to 1450: Client computer 1460: Server computer, 1470: Host computer

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kenichi Inoue 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture, Hitachi, Ltd. General Computer Division (72) Inventor Hiroshi Fukuda 1st Horiyamashita, Hadano-shi, Kanagawa, Hitachi Inside the General-purpose Computer Division of the Manufacturing Company (72) Inventor Tsukasa Shibuya 1st General Horiyamashita, Hadano-shi, Kanagawa Prefecture Inside of the General-purpose Computer Business Division, Hitachi Ltd. Within Computer Division (72) Inventor Mamoru Ogiwara 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture Hitachi Computer Co., Ltd. (72) Inventor Shigemasa Sato 1 Horiyamashita, Hadano-shi, Kanagawa General-purpose Computer, Hitachi Ltd. Within the business division (72) Inventor Mitsuru Usui No. 1, Horiyamashita, Hadano-shi, Kawasaki General-purpose computer division of Hitachi, Ltd. (56) References JP-A-63-102399 (JP, A) JP-A-6-209169 (JP, A) (JP, A) JP-A-63-213399 (JP, A) JP-A-61-131497 (JP, A) JP-A-62-84974 (JP, U) (58) Fields investigated (Int. Cl. ⁷⁾ , DB name) H05K 3/46 H01L 23/522 H05K 3/22

Claims (2)

(57) [Claims] 1. A first multilayer for producing a first multilayer three-dimensional circuit.
The three-dimensional circuit manufacturing process and the first multilayer three-dimensional circuit manufacturing process
Inspection of the manufactured first multilayer three-dimensional circuit, the first multilayer
Defects in the inner layer of the three-dimensional circuit due to the manufacturing process
Inspection step for detecting the above, and the first multilayer three-dimensional circuit
Above, correct the defective part detected in the first inspection process
A large number of stacked pads that are inherently conductively connected
Adjacent above and below at least one stacked pad group in the group
Electrically insulate the pads of matching layers with an insulator.
Conduction of the intermediate pad of the upper layer to the repair line pattern
Incorporate a correction circuit configured by connecting and stacking and connecting
Forming a second multilayer three-dimensional circuit to form a second multilayer three-dimensional circuit
And forming the second multilayer three-dimensional circuit forming step.
Inspection of the second multilayer three-dimensional circuit and the first multilayer three-dimensional circuit
And a second inspection step of
Multi-layer three-dimensional circuit for manufacturing multi-layer three-dimensional circuit boards consisting of body circuits
Circuit board manufacturing process and multilayer three-dimensional circuit manufactured in the multilayer three-dimensional circuit board manufacturing process
Mount multiple chip components on the surface of the board and connect
And a chip component mounting connection process to obtain a chip module.
Multi-chip module production method characterized by
Law. 2. The multi-chip module according to claim 1,
Multi-chip manufactured by the method of
Module.