JP3152527B2 - Multilayer circuit wiring board having circuit correction function, circuit correction method and electronic circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit wiring board having a circuit correcting function, a circuit correcting method for the board, and an electronic circuit device having electronic components mounted on the circuit wiring board.

[0002]

2. Description of the Related Art With the increase in speed and integration of LSIs, high-density mounting technology on a circuit wiring board is very important for electronic circuit devices equipped with a large number of LSIs. That is, by increasing the density, the wiring path between LSIs is shortened, the wiring delay time of the electric signal in the substrate is reduced, and the high-speed operation as an electronic circuit device is enabled.

For this reason, as a high-density mounting technique, for example, a flip chip in which a bump made of a metal such as solder is formed on an electrode of an LSI chip surface and the chip is face-down bonded onto a circuit wiring board via the bump is provided. There is a mounting method.

Further, as the number of input / output terminals of the LSI chip increases and the number of signal wirings in the circuit wiring board increases due to the high integration of the LSI, the circuit wiring board on which the LSI is mounted needs to be multilayered. . Therefore, a circuit wiring board is required to have a fine and multi-point electrode terminal forming technology and a multilayer circuit wiring technology.

In such a multi-layer circuit wiring board, it is necessary to repair the circuit such as repairing a defect in the process of manufacturing a fine wiring pattern and changing the logic between LSIs after mounting the LSI on the board. Come. Specifically, the following problems, for example, (1) defective circuit wiring design, (2) defective manufacturing, (3) LSI operation due to signal propagation delay time or wiring pattern defects occurring on wiring paths, etc. Circuit changes are required due to problems such as defects and (4) design changes for improving the performance of the electronic circuit device.

For this reason, a multilayer circuit wiring board requires a repair pattern structure for circuit change without lowering the mounting density and the operation performance of the LSI. Various structures have been proposed so far. I have.

For example, as one of the methods, a repair wiring connection pad and an EC (Engineering Change) pad are provided around an outside of a projection plane of an electronic circuit component mounted on a multilayer circuit board. There is known a method of performing a circuit change by performing wire bonding. But,
In this method, since the repair pads are provided on the circuit board surface, the mounting density of electronic circuit components on the circuit board (total area of mounted electronic circuit components / circuit board area) is significantly reduced. As related to this type of technology, for example, Japanese Patent Application Laid-Open No. Sho 62-25437 and the Microelectronics Packaging Handbook (No. 39)
Page, Figures 1-28, published by Nikkei BP, March 27, 1991
Days).

Therefore, as a method of improving the mounting density, a pad structure for connecting electronic circuit components provided on a circuit board is improved, and a repair pad is provided in a projection plane of the electronic circuit component to provide a repair pad. Methods for reducing the occupied area have been proposed. According to this method, (1) a pad for cutting at the time of remodeling and a pattern connecting pad for remodeling are provided on the terminal connecting pads of the electronic component provided on the surface layer of the substrate,
A wiring pattern in the board connected through the pad for cut during the remodeling, and a remodeling pattern connected to the remodeling pattern connection pad at the time of the remodeling have a structure provided on the inner layer of the substrate. The remodeling cut pad connected to the terminal connection pad provided on the surface layer is cut from the terminal connection pad, and the remodeling pattern connection pad connected to the terminal connection pad on the surface layer is provided on the other side and the inner layer. A dedicated via is provided between the modified pattern and the modified pattern, and (2) the modified pattern is provided as a two-layer structure in the substrate, and the modified pattern is connected to the surface layer. As a pad,
At the position where via connection is possible between these two layers, there is provided a channel-switching conductive via-forming pad indicating a channel-switching conductive-forming position. It should be noted that Japanese Patent Application Laid-Open No. Sho 63-2
No. 13399.

[0009]

The latter repair method of providing a repair pad also in the projection plane of an electronic circuit component can reduce the area occupied by the repair pad provided on the circuit board, as compared with the former. It is excellent in that. But,
The modification cut pad and the modification pattern connection pad separated from the terminal connection pad at the time of modification are still present on the substrate, and therefore have the following problems.

[0010] (1) Since a cut pad for modification and a pattern connection pad for modification are provided as repair pads in addition to the terminal connection pads on the surface of the multilayer circuit board, the electronic circuit components for the circuit board are provided. The mounting density is still low and insufficient for high-density mounting. (2) After flip-chip mounting an LSI chip on a multilayer circuit wiring board, a design change or LSI
If the operation failure occurs, remove the LSI chip,
It is necessary to remount a new LSI chip. This is usually called repair. At this time, since excess solder remains on the terminal connection pads on the substrate after the unnecessary LSI chip is removed, the terminal connection pads are usually formed using a metal having good solder wettability, such as a Cu plate. Work to remove excess solder on top).

However, in the above-mentioned conventional technology, the following problem occurs at the time of repair leveling work because the terminal connection pad is provided with a remodeling cut pad or a remodeling pattern connection pad. Excessive solder wet on the Cu plate spreads to the cut pad at the time of remodeling and reconnects the cut pad at the time of remodeling once cut from the terminal connection pad. It becomes difficult to recognize the position for connecting the pattern, and the efficiency of the drilling work for the via using the laser is reduced. Also, the remodeling route of the wiring pattern is from a remodeling pattern connection pad on the surface layer of the substrate to a remodeling pattern provided as a two-layer structure on the inner layer of the substrate. The holes for the vias are formed by laser using the positions for connecting the remodeling patterns, the positions for forming the continuity for channel switching, and the like, which are provided on the surface layer of the substrate. However, the positioning of the hole to be drilled requires a total of three layers of positioning accuracy, including the surface layer pads of the board and the remodeling pattern of the inner layer. In addition, it becomes easy to be affected by the positioning accuracy of the pattern mask in each layer and the like, and it becomes difficult to form holes for vias with high precision.

Accordingly, an object of the present invention is to solve the above-mentioned problems of the conventional technology, and a first object of the present invention is to provide a multilayer circuit wiring board having a circuit correction function improved for high-density mounting. A second object is to provide a method for repairing a circuit on a circuit wiring board, and a third object is to provide an electronic circuit device in which electronic components are mounted on this board.

[0013]

In order to achieve the above-mentioned object, according to the present invention, a cut pad and a remodeling pattern connection pad for remodeling are removed from the surface of a circuit board, and the wiring pattern provided on the inner layer of the board is replaced with the inner layer. , And cut directly. Further, a wiring pattern, a repair pattern, and a repair free pattern are provided on an inner layer of the substrate, and these are arranged on the same plane to make the structure easy to repair. In addition, the wiring pattern and the repair pattern have a structure that is close to each other, and when connecting both with a conductor such as solder, a hole that exposes both patterns is provided, and the circuit is easily connected simply by embedding the conductor in the trace A structure that can be used. Still further, a circuit correction board having the wiring pattern and the repair pattern is provided between the multilayer circuit wiring board and the electronic circuit components mounted thereon.

The first object of the present invention will be described below. First, the first object is to provide a wiring pattern and a repair pattern in an inner layer via an interlayer insulating film and to provide a circuit pattern on these patterns. A wiring board having a circuit correction area to be cut and connected, a terminal connection pad for connecting electronic circuit components provided on the board, and a conductive board for connecting the wiring pattern to the terminal connection pad. A multilayer circuit wiring board having a circuit correction function comprising a via, wherein at least a circuit correction connection area of a repair pattern provided in the inner layer and at least a circuit correction connection area of the wiring pattern are brought close to each other, and This is achieved by using a multilayer circuit wiring board arranged so as to be located on the same plane as each other.

Preferably, at least the circuit correction connection region of the repair pattern and at least the circuit correction connection region of the wiring pattern are arranged close to each other (more preferably, close to the minimum pattern interval that can be insulated). The repair pattern is disposed on the same plane as the wiring pattern so as to surround the wiring pattern, and the repair pattern is arranged so as to surround the wiring pattern. It is desirable that the wiring pattern is formed so that at least the main part is located on the same plane as the wiring pattern.

Further, it is desirable that the cut and connection circuit correction area is disposed outside the projection area of the terminal connection pad in consideration of a drilling operation at the time of circuit correction. Also,
The intersection of the repair patterns formed by the two-way grid pattern intersecting with each other, the repair pattern in any one direction is connected to a lower layer pattern via a conductive via, and via an interlayer insulating film. The structure may be a three-dimensional intersection where both insulation is maintained, or a structure where both are connected to maintain electrical continuity.

Further, the wiring board has a mounting area in which a plurality of electronic circuit components are mounted adjacently in a matrix, and 1) the mounting in an inner layer area between the adjacent mounting areas. It is desirable to arrange the repair free pattern along the outer periphery of the projection plane of the area in a matrix with a grid pattern in two directions intersecting each other and on the same plane as the wiring pattern and the repair pattern. Circuit correction between adjacent electronic circuit component mounting areas can be performed via the free pattern and the repair pattern.

2) The repair pattern is provided in an inner layer area of the projection surface of the mounting area, and the end of the repair pattern is provided to the outer periphery of the projection surface of the mounting area, and the end is connected via a via. When repairing the circuit between electronic circuit components mounted on the wiring board by connecting to the repair pad provided on the surface layer by
The repair can be performed by connecting the repair pads to be repaired by wire bonding or ribbon bonding.

At the intersection between the repair free patterns composed of the two-way grid pattern intersecting in the above 1), the repair free pattern in any one direction is connected via the conductive via as in the case of the repair pattern. Or a three-dimensional intersection where the two layers are connected to each other and the insulation between the two layers is maintained via an interlayer insulating film, or a structure in which the two layers are connected and the electrical conduction is maintained. Further, at least the main parts of the repair pattern in the two directions intersecting with each other and the repair free pattern are arranged on the same plane. Further, between the repair pattern, the repair free pattern, and the wiring pattern and the interlayer insulating film thereunder, an insulating film such as an oxide film, a nitride film, etc. It is desirable to provide a barrier layer consisting of

The first object can also be achieved by providing a circuit correction board having a circuit correction function between the multilayer circuit wiring board and the electronic circuit components mounted thereon as described above. Similar to the case of the multilayer circuit wiring board, the circuit repair board is provided with a wiring pattern and a repair pattern for forming a repair area on one of the front and back surfaces, and the electronic circuit components are mounted on the circuit repair board. Mounted on and connected to.

A second object of the present invention is a circuit repair method using a multilayer circuit wiring board or a circuit repair board capable of achieving the first object, wherein a wiring pattern and a repair pattern are predetermined. Removing the insulating film on the corrected circuit cut correction region, and cutting the exposed wiring of the correction region, and removing the insulating film on a predetermined circuit connection correction region of the wiring pattern and the repair pattern. And a step of conducting a conductor connection between the exposed wirings of the repair area, or a circuit repair method of the circuit repair board.

A second object of the present invention is to provide a circuit repair method using the multilayer circuit wiring board or the circuit repair board, wherein a predetermined circuit cut repair area of a wiring pattern, a repair pattern and a repair free pattern is provided. Removing the upper insulating film and cutting the exposed wiring in the repair area, and removing the insulating film on a predetermined circuit connection correction area of the wiring pattern, the repair pattern and the repair free pattern, and exposing the exposed wiring. Connecting the conductors between the wirings in the repair area, and performing a circuit repair between the adjacent electronic circuit component mounting areas via the repair pattern and the repair free pattern. This is also achieved by a circuit correction method for a circuit wiring board or a circuit correction board.

Preferably, the step of removing the insulating film on the circuit cut correction area and cutting the exposed wiring of the correction area includes the step of forming a hole in the insulating film by laser beam irradiation and the step of laser beam irradiation subsequent to the step. And the step of removing the insulating film on the circuit connection repair area and connecting the conductors between the exposed wirings of the repair area by a laser beam irradiation process. And a step of connecting the exposed wirings to each other with a conductor.

The step of conductor-connecting the wirings may be, for example, a step of supplying a brazing material such as solder into the opening and melting and connecting the wirings, or a method of laser CVD (Chemical Vapor Deposition) on the exposed wirings. A process of depositing and connecting conductors by vapor phase growth) or a process of connecting using an ultrasonic thermocompression bonding method such as wire bonding or ribbon bonding (solid phase / solid phase connection process). Can also.

In the step of drilling the insulating film by the laser beam irradiation, it is necessary to make the diameter of the hole drilled in the insulating film on the circuit cut correction area significantly smaller than the diameter of the hole drilled in the insulating film on the circuit connection correction area. It is. This prevents excess solder from entering into the cut-corrected hole during the leveling operation, and prevents reconnection of the circuit cut portion. On the other hand, in order to embed a conductor in the hole in the circuit connection correction area and connect adjacent circuits, the diameter is set so that a brazing material such as solder can easily penetrate.

Further, the third object is to mount electronic circuit components on a multilayer circuit wiring board which achieves the first object, and to provide terminal connection pads provided in a mounting area on the board. This is achieved by an electronic circuit device formed by electrically connecting terminals of an electronic circuit component. Usually, a large number of electronic circuit components such as LSIs are connected in a matrix on a substrate, and high-density mounting is achieved. Also, this type of circuit board is configured by integrally connecting and forming a second thin-film multilayer circuit wiring board on a first thick-film board to which input / output terminals are connected. The first thick-film substrate is generally provided with pins as input / output terminals on the back surface, and a connection terminal group for forming a second thin-film multilayer circuit wiring substrate on the front surface. It is composed of a rigid multilayer circuit wiring board such as a substrate.

Further, the third object is to connect a circuit correction board which achieves the first object on the multilayer circuit wiring board, and mount electronic circuit components on the circuit correction board.
This is also achieved by an electronic circuit device in which the terminal connection pads provided in the mounting area on the multilayer circuit wiring board, the terminal connection pads on the circuit correction board, and the terminals of the electronic circuit components are electrically connected. Is done. Such an electronic circuit device is effective, for example, for a large-sized electronic circuit device such as an electronic computer. A circuit-corrected circuit board on which electronic circuit components such as an LSI are mounted and connected in advance and the circuit is corrected is mounted on a multilayer circuit wiring board. Take a connected structure. In this case, usually, an LSI is connected to a circuit correction board in advance to perform a circuit inspection, and when a necessary circuit correction portion is found, the circuit correction is performed according to the circuit correction method of the present invention. A plurality of LSI-connected circuit-corrected boards having no defect and having a corrected circuit are mounted and connected on the multilayer circuit wiring board according to the circuit scale, thereby realizing a desired electronic circuit device. Depending on the circuit scale, 1
One or more LSI chips are connected.

[0028]

According to the multilayer circuit wiring board having the circuit correcting function of the present invention (including the circuit correcting board, the same applies hereinafter), the terminal connection is provided directly below the electronic circuit component mounted on the multilayer circuit wiring board. The repair wiring work can be performed outside the projection area of the repair pads, and the conventional repair pads are removed from the substrate surface, so that the mounting density of electronic circuit components can be greatly improved.

Further, a wiring pattern is provided on an inner layer of the substrate,
At the time of remodeling, by cutting one part on the one hand and connecting it on the other, it is possible to solve the problem that extra solder at the leveling operation causes the cut part to be reconnected. That is, the diameter of the hole that is opened in the insulating layer on the wiring pattern at the time of cutting can be made smaller than that at the time of connection, so that penetration of solder can be prevented. For example, the diameter of the cut portion is 30 to 50 μm, and the diameter of the connection portion is 100 to 150 μm.
By setting m, the solder can be selectively supplied only to the connection portion.

Further, by eliminating the remodeling cut pad and remodeling pattern connection pad described in the section of the prior art from the substrate surface, it is possible to prevent extra solder from spreading during the leveling operation.

At the time of circuit correction, the circuit is cut by simply cutting the circuit correction area of a predetermined pattern with a laser, but the connection of the circuits is made by connecting the connection areas of the patterns arranged close to each other and arranged on the same plane. They are realized by being connected to each other via a conductor such as solder.

Further, by providing the wiring pattern, the repair pattern, and the repair free pattern on the same plane, only one pattern mask is required at the time of forming the circuit, the alignment accuracy between the patterns is improved, and the cut position is improved. Also, the connection position between the patterns can be easily identified.

[0033]

An embodiment of the present invention will be described below with reference to the drawings. Embodiment 1 (1) Configuration of Multilayer Circuit Wiring Board FIG. 1 is a sectional view of a main part of a multilayer circuit wiring board having a circuit correcting function according to an embodiment of the present invention. Usually, this type of circuit board is configured by integrally connecting and forming a second thin-film multilayer circuit wiring board on a first thick-film board to which input / output terminals are connected. Although this first thick film substrate is omitted in this figure, generally, pins as input / output terminals are planted on the back surface, and connection terminal groups for forming a second thin film multilayer circuit wiring board are provided on the front surface. And a rigid multi-layer circuit wiring board such as a ceramic or glass epoxy board. This figure shows a state in which an LSI, which is an electronic component, is mounted and connected on a second thin-film multilayer circuit wiring board which is a feature of the present invention.

In FIG. 1, reference numeral 1 denotes a multilayer circuit wiring board of the present invention which constitutes the second thin-film multilayer circuit wiring board, 2 denotes an LSI chip, 3 denotes solder bumps provided on connection terminals of the LSI chip 2, 4 Is a terminal connecting pad of the electronic component provided on the multilayer circuit wiring board, 5 is a conductive via having one end connected to the terminal connecting pad 4 and the other end connected to the wiring pattern 6, and 7 is a repair pattern X ( (Disposed in the X direction),
8 is a repair pattern Y (arranged in the Y direction), 9 is a repair free pattern, 10 is an insulating film forming a barrier, and 11 is a first terminal connecting pad 4 on the surface layer of the substrate 1.
Reference numeral 12 denotes a second pattern including the wiring pattern 6, the repair pattern X7, the repair pattern Y8, and the repair free pattern 9 in the inner layer of the substrate 1, and 13 denotes the wiring pattern 6, the repair pattern X7, the repair free in the inner layer of the substrate 1. A third pattern consisting of pattern 9, 14 is the substrate 1
, A reference numeral 15 denotes a second interlayer insulating film in the substrate 1, and 16 denotes a third interlayer insulating film in the substrate 1. These three interlayer insulating films 14 to 16 are made of, for example, an organic insulating film such as polyimide or polyamide which is easily patterned.

FIGS. 2 to 4 are plan views of the patterns 11 to 13 in the multilayer circuit wiring board of FIG. That is, FIG. 2 shows the interlayer insulating film 14 in the substrate 1.
A first pattern 11 on the surface layer is shown, and 17 indicates a mounting area of the LSI chip 2. As shown, in this figure 1
A mounting area 17 for four LSIs is provided on a single substrate,
Sixteen terminal connection pads 4 are provided for one LSI chip 2.

FIG. 3 shows the second pattern 12 on the interlayer insulating film 15 in the inner layer of the substrate. The repair pattern X7 and the repair pattern Y8 are arranged in a grid just below the terminal connection pads 4 shown in FIG. The wiring pattern 6 is arranged near the repair pattern X7 and the repair pattern Y8. The repair free patterns 9 are arranged along four sides of each LSI chip mounting area 17. As shown in the cross-sectional view of FIG. 1, the intersection of each wiring pattern crosses three-dimensionally via an insulating film.

FIG. 4 shows the third pattern 13 on the interlayer insulating film 16, where the conductive vias connected to the wiring pattern 6 are formed and the intersection between the repair pattern X7 and the repair pattern Y8 shown in FIG. 5 shows a pattern for repair pattern intersection provided to maintain insulation between the patterns at the intersections between the free patterns 9 and the repair free patterns 9. That is, at the intersection between the repair pattern X7 and the repair pattern Y8, the repair pattern crossing pattern is connected to the repair pattern shown in FIG. 3 via the conductive via 5 (hereinafter, shown in detail in FIG. 5). X7, and the intersection pattern and the conductive via 5 are connected to the repair pattern Y.
8 and passes through the interlayer insulating film 15 to form a three-dimensional intersection of the repair patterns X7 and Y8. A similar three-dimensional intersection is also formed at the intersection between the repair free patterns 9, and an interlayer insulating film 15 is formed under one repair free pattern 9.
Through the other repair free pattern 9.

The repair pattern structure in the multilayer circuit wiring board 1 described above and the principle of the repair method are shown in FIGS.
2 will be described. FIGS. 5 and 6 are enlarged views of the periphery of one terminal connection pad 4 at the intersection of the repair pattern X7 and the repair pattern Y8 with the conductive via 5 interposed therebetween. The third shown in 4
5 shows an example of a repair pattern connection in which the lower pattern 7 is connected to the lower pattern 7 and the insulation between the two is maintained via an interlayer insulating film 15.

That is, FIG. 5 shows a state before wiring correction (initial state).
(A) is a see-through perspective view, (b) is a top view, and (c) of FIG.
3 is a cross-sectional view taken along arrows 1 to 3 shown in FIG. As shown in FIG. 1A, a terminal connection pad 4 on a surface layer of a substrate 1 is connected to a wiring pattern 6 via a conductive via 5. In addition, the wiring pattern 6 is a repair pattern X in a layer around the terminal connection pad 4.
7. It is arranged close to the repair pattern Y8. That is, as shown in FIG. 3, the wiring pattern 6, the repair pattern X7, and the repair pattern Y8 are arranged on the same plane on the substrate inner layer surface (second pattern 12). Further, as shown in FIG. 2B, the wiring pattern 6, the repair pattern X7, and the repair pattern Y8 have a structure in which both are close to each other and have a minimum pattern interval that can be insulated. In addition, as shown in FIG.
The structure at the intersection of the repair pattern Y8 and the repair pattern Y8 is, for example, as shown in the cross-sectional area, under the repair pattern Y8.
The repair pattern X7, the conductor via 5 and the repair pattern crossing pattern 7 on the interlayer insulating layer 16 are connected through the circuit conductors 0 and 15, respectively.

FIGS. 6A and 6B show the structure of the wiring pattern after the wiring pattern of FIG. 5 has been modified. FIG. 6A is a perspective view, FIG. 6B is a top view, and FIG. () Is a cross-sectional view taken along the arrow-shown in FIG.

FIGS. 7 and 8 show examples before and after the pattern modification in which the repair pattern X7 and the repair pattern Y8 differ from those in FIGS. 5 and 6 respectively. That is, the X and Y patterns 7 in FIGS.
8 shows an example in which patterns of a portion corresponding to a three-dimensional intersection are connected using a repair pattern in which the two are integrally connected on the same plane. That is, FIG. 7 shows a configuration of a wiring pattern before wiring correction (initial state), wherein FIG. 7 (a) is a perspective view, FIG. 7 (b) is a top view, and FIG. It is sectional drawing in alignment with the arrow marked in (b).

FIGS. 8A and 8B show the structure of the wiring pattern after the wiring pattern of FIG. 7 is corrected. FIG. 8A is a perspective view, FIG. 8B is a top view, and FIG. Is the same figure (b)
3 is a cross-sectional view along the arrow marked with.

FIGS. 9 and 10 show a wiring correction in which a wiring pattern 6 and a repair pattern X7 formed integrally with the terminal connection pad 4 are arranged on the same plane as the terminal connection pad 4. FIG. It shows before and after examples (repair pattern Y is omitted and a part of wiring pattern 6 is used). That is, FIG. 9 shows a configuration of a wiring pattern before wiring correction (initial state), and FIG.
FIG. 3B is a top view, and FIG. 3C is a cross-sectional view taken along a path indicated by an arrow in FIG. In addition, FIG.
(B) shows a state in which the insulating layer film 14 on the substrate surface has been removed. 10 shows the configuration of the wiring pattern after the wiring pattern of FIG. 9 has been corrected. FIG. 10A is a perspective view, FIG. 10B is a top view, and FIG.
Is a cross-sectional view taken along a path indicated by an arrow in FIG. 9A and 9B also show a state in which the insulating layer film 14 on the substrate surface has been removed as in the case of FIG.
As is clear from these figures, in this example, the wiring pattern 6 and the repair pattern X7 arranged on the same plane are
Since the circuit is cut in one circuit correction region 18 and connected in the other circuit correction region 20 to correct the circuit, there is no need to form a three-dimensional intersection as shown in FIGS. The number of stacked films can be reduced by one layer. That is, the number of laminated interlayer insulating films required for repairing the wiring pattern can be reduced from three to two.

FIGS. 11 and 12 show a terminal in which the wiring pattern 6 and the repair pattern X7 are arranged on the same plane, the cut portion of the circuit correction area is provided on the inner layer, and the connection portion between them is provided on the surface of the substrate. Examples before and after wiring correction provided on the same plane as the connection pads 4 (wiring pattern 6 with repair pattern Y omitted)
Is used). That is, FIG.
FIG. 3A shows a configuration of a wiring pattern before wiring correction (initial state), FIG. 4A is a perspective view, and FIG.
FIG. 3C is a top view, and FIG. 3C is a cross-sectional view along a path indicated by an arrow in FIG. FIG. 12 shows the configuration of the wiring pattern after the wiring pattern of FIG. 11 has been corrected, wherein FIG. 12 (a) is a perspective view, FIG. 12 (b) is a top view,
FIG. 3C is a cross-sectional view along the path indicated by the arrow in FIG. As is apparent from these figures, the circuit pattern is corrected by cutting the wiring pattern 6 and the repair pattern X7, which are arranged on the same plane in the layer, at one of the circuit correction areas 18 (in this figure, the wiring pattern 6 is cut). Cut), and the connection is made in the other circuit correction area 20 provided on the same plane as the terminal connection pad 4, so that a three-dimensional intersection is formed in the insulating layer as a repair pattern as shown in FIGS. Need not be formed, and the repair pattern Y8 is also omitted, so that the structure is simplified.

(2) Procedure for Correcting Wiring Pattern Here, a specific procedure for correcting a wiring pattern will be described below with reference to FIGS. 5 and 6 as an example. . That is, as shown in FIG. 5, the wiring pattern 6 whose one end is connected to the terminal connection pad 4 and the repair pattern Y arranged close to the wiring pattern 6.
As shown in FIG. 6, a predetermined portion of FIG. 8 is cut (18, 19) in one correction region and connected (2, 19) in the other correction region.
0) Then, a repair method for finally connecting the terminal connection pad 4 and the repair pattern Y8 will be described.

[Procedure 1] First, as shown in FIG. 6, a predetermined portion of the wiring pattern 6 connected to the terminal connection pad 4 is cut. Cut position 18 of wiring pattern 6
Is cut on the inner layer side of the substrate from the point where the wiring pattern 6 and the repair pattern Y8 are connected. As a wiring cutting means, a laser is used. First, a hole is formed in the interlayer insulating film 14, and then the wiring pattern 6 is cut. At this time, the energy density at the time of laser drilling differs by about one digit between the material of the wiring pattern 6 (a conductor such as Cu and Al) and the material of the interlayer insulating film 15 (polyimide or the like). There is a possibility that the interlayer insulating film 15 immediately below may be damaged (a hole is formed). Therefore, a thin insulating film 10 (a barrier such as an oxide film or a nitride film) is formed between the second pattern 12 and the interlayer insulating film 15 to prevent damage to the interlayer insulating film due to laser irradiation.

[Procedure 2] In order to expose the connection position between the wiring pattern 6 and the repair pattern Y8, the interlayer insulating film 14 at the connection position 20 is removed using a laser, and a connection hole is formed.

[Procedure 3] A soldering material such as a solder foil or a solder ball is inserted into a connection hole between the wiring pattern 6 and the repair pattern Y8, and the two patterns are connected by melting the solder by laser irradiation. Instead of the connection by brazing, for example, a method of wire bonding, ribbon bonding, wire connection by ultrasonic thermocompression bonding, a method of depositing a predetermined metal in a hole by laser CVD, and a method of connection can be used.

[Procedure 4] In the repair pattern Y8 connected to the wiring pattern 6, unnecessary wiring lines are cut (repair pattern cut position 19). The cutting method is
After removing the interlayer insulating film 14 by laser, the repair pattern Y8
Cut a predetermined part of. It should be noted that this procedure 4 is the same as procedure 1
In the same manner as the cutting of the wiring pattern 6.

At the time of drilling the interlayer insulating film by the laser in the above steps 1, 2 and 4, a difference in the opening diameter is provided between the cut hole and the connection hole, and the cut hole is a necessary minimum. It is desirable to make it smaller than the connection hole. The reason is that when leveling work is performed at the time of mounting and mounting of electronic components, it is to prevent excess solder from entering the inside through the hole at the time of cutting and reconnecting the existing wiring pattern cut portion. .

Further, in determining the drilling position, since the interlayer insulating film is thin, the wiring pattern of the inner layer can be seen through from the outside, so that the positioning can be performed directly. Also,
If necessary, a wiring pattern can be printed on the surface of the substrate in advance using insulating ink.

<Embodiment 2> Next, FIGS.
13 shows an example in which a wiring pattern between two terminal connection pads 4 is corrected via the repair free pattern 9 shown in FIG.
This will be described with reference to FIG. The repair free pattern 9 is arranged along the four sides of each LSI chip mounting area 17 as described in FIGS. 1 to 3 and is arranged in the same layer as other wiring patterns. FIG. 13 is an enlarged plan view of a main part of the second pattern 12 near a corner where four adjacent LSIs 2 are mounted as shown by the LSI mounting area 17 in FIG. ) Shows the state before the wiring is corrected (initial state), FIG. 14B shows the state after the wiring is corrected, and FIG. 14 is the cross-sectional view of the broken substrate wiring after the correction along the arrow in FIG. Each is shown.

The procedure for correcting the wiring pattern will be specifically described below. However, the wiring path between the terminal connection pad A and the terminal connection pad B in FIG. A description will be given of an example in which the connection is made dynamically.
The wiring correction procedure from the terminal connection pads A and B to the nearest repair pattern X7 follows the procedures 1 to 4 described in the first embodiment, and thus the description is omitted here. Will be described. [Procedure 5] At the place where the repair pattern X7 and the repair free pattern 9 are connected (the position of the solder 23 connecting the repair pattern X7 and the repair free pattern 9), the interlayer insulating film 14 is removed by using a laser, and the connection is performed. Make a hole. Drilling is performed in the same manner as in the first embodiment. [Procedure 6] The repair pattern X7 exposed by the drilling and the repair free pattern 9 are connected by inserting a brazing material such as a solder foil or a solder ball into the hole by the same method as in the first embodiment, and irradiating the laser. The solder is melted, and both patterns are solder-connected 23. [Procedure 7] Repair pattern X7 connected by procedures 5 and 6
In the repair pattern 9 and the unnecessary free line 9, unnecessary wiring lines are cut in the same manner as in the first embodiment (the cut position 19 of the repair pattern X7, the repair free pattern 9).
Cut position 22).

In the above embodiment, the wiring pattern 6 shown in FIG. 5B was used. However, the wiring pattern 6 may be arranged such that the repair pattern X7 and the pattern Y8 are close to the solder connection portion only. For example, a T-shaped pattern shape as shown in FIG. 15 may be used, and both ends may be brought close to the direction of the intersection of the repair patterns X7 and Y8.
FIG. 15A shows the pattern before correction, and FIG. 15B shows the pattern after correction.

Further, as a connection method between the wiring lines 6-7 and between the wiring lines 7-9, solder fusion connection by laser was used. However, when the number of solder connection points on the substrate is large, first, all the connection points are connected. Improve workability by soldering each hole after laser drilling into the interlayer insulating film and putting the whole board into a reflow furnace instead of irradiating each hole with a laser and making a batch connection. Can also. Further, as a method replacing the solder connection, for example, there is a wire bonding or a ribbon bonding connection by an ultrasonic thermocompression bonding method.

<Embodiment 3> FIGS. 16 to 23 show that the LSI 2 is mounted on a board provided with a repair area 27 having a circuit repair function on one or both of the multilayer circuit wiring board 1 and the circuit repair board 24. 1 is a cross-sectional view of a main part of an electronic circuit device according to an embodiment. In the repair area 27, a wiring layer having a circuit repair function is provided similarly to the multilayer circuit wiring board 1 described in the first and second embodiments, and the wiring pattern 6, the repair patterns 7, 8, the repair free pattern 9, and the wiring pattern are provided. , A connection between repair patterns, or a cut portion.

That is, FIG. 16 shows a circuit repair function portion in the multilayer circuit wiring board 1 of the first embodiment by the repair area 27, and is a simplified illustration of FIG. FIG. 17 shows a configuration in which the LSI 2 is mounted via a circuit correction board 24 instead of being mounted directly on the multilayer circuit wiring board 1 in FIG. As in the case of the multilayer circuit wiring board 1, a repair area 27 having a circuit repair function is provided on the surface layer portion on the circuit repair board 24. FIG. 18 shows a configuration example in which the repair area 27 on the circuit correction board 24 has the reverse structure of FIG. 17 and is provided on the back surface. 16 to FIG.
In, the connection between adjacent LSIs 2 (FIG. 16) or between the circuit correction boards 24 (FIGS. 17 and 18) is performed using the repair free pattern 9 provided on the multilayer circuit wiring board 1. In FIGS. 19 to 23 to be described, these connections are made by the repair pads 25 provided on the multilayer circuit wiring board 1.
The connection is made by wire bonding or ribbon bonding 26.

That is, FIG. 19 shows a configuration corresponding to FIG. 16, in which the connection between adjacent LSIs 2 is
The repair pad 25 provided on the repair area 27 is bonded to the wire bonding or the ribbon bonding 26. FIG. 20 shows a configuration corresponding to FIG.
The connection between the circuit correction board 24 on which the SI 2 is mounted is connected to the repair pad 25 provided on the thin film layer 29 of the multilayer circuit wiring board 1 by wire bonding or ribbon bonding 26.
And go with. FIG. 21 shows a configuration corresponding to FIG.
The connection between the adjacent circuit correction boards 24 on which the LSIs 2 are mounted is the same as in FIG.

FIGS. 22 and 23 show an example in which a circuit correction board 24 is provided on a thick-film multilayer circuit wiring board 1 made of ceramics or the like. The terminal connection pads 4 and the repair pads 25 on the multilayer circuit wiring board 1 are shown in FIGS. A thick-film conductor wiring (a conductor such as tungsten or molybdenum) 28 is provided for the connection therebetween. That is, FIG. 22 shows a configuration corresponding to FIG.
The connection between the circuit correction boards 24 on which the SI2 is mounted is shown in FIG.
Similarly to the above, the repair pad 25 and the wire bonding or the ribbon bonding 26 are used. FIG.
In the configuration corresponding to FIG. 21, the connection between the circuit correction boards 24 on which the adjacent LSIs 2 are mounted is the same as in FIG.

As described above, according to the present embodiment, the cutting and connection of the wiring lines are performed in the inner layer of the substrate, so that the reconnection of the existing pattern cut portion due to excess solder during the leveling operation can be prevented, and the repaired portion can be prevented. Reliability can be improved. Also, the wiring pattern 6 and the repair pattern 7,
8. By providing the repair free pattern 9 on the same plane, it is possible to improve the positioning accuracy of the pattern correction portion (wiring cut, connection), improve the quality of the product board, improve workability, and improve the circuit pattern correction function. The mounting density of the provided multilayer circuit wiring board can be greatly improved.

[0061]

As described in detail above, the present invention has achieved the initial object. That is, in the multilayer circuit wiring board or the circuit correction board of the present invention having a circuit pattern correction function, a repair pattern is provided on the inner layer, and the wiring pattern and the repair pattern are arranged on the same plane, whereby Correction can be easily performed within the board, improving the reliability and workability of the repaired part during leveling work, improving the alignment accuracy of the wiring lines, and greatly improving the high-density mounting of the multilayer circuit wiring board. . In addition, the circuit repair method of the substrate is also a simple method including a combination of existing three processes of drilling an interlayer insulating film, cutting an unnecessary part pattern and connecting adjacent wirings, and is easily implemented for automation. It is possible. Furthermore, an electronic circuit device in which electronic components are mounted and connected to a multilayer circuit wiring board or a circuit correction board of the present invention having a circuit pattern correction function is highly reliable and densely mounted. Therefore, a compact device configuration can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a multilayer circuit wiring board and an electronic circuit device according to an embodiment of the present invention.

FIG. 2 is a plan view of a first pattern 11 in the multilayer circuit wiring board according to one embodiment of the present invention.

FIG. 3 is a plan view of a second pattern 12 in the multilayer circuit wiring board.

FIG. 4 is a plan view of a third pattern 13 in the multilayer circuit wiring board.

FIG. 5 is an enlarged view of a main part of the multilayer circuit wiring board before a circuit pattern is corrected.

FIG. 6 is an enlarged view of a main part of the multilayer circuit wiring board after a circuit pattern is corrected.

FIG. 7 is an enlarged view of a main part before correcting a circuit pattern in a multilayer circuit wiring board according to another embodiment of the present invention.

FIG. 8 is an enlarged view of a main part of the multilayer circuit wiring board after a circuit pattern is corrected.

FIG. 9 is an enlarged view of a main part of a multilayer circuit wiring board according to another embodiment before a circuit pattern is corrected.

FIG. 10 is an enlarged view of a main part of the multilayer circuit wiring board after the circuit pattern shown in FIG. 9 is modified.

FIG. 11 is an enlarged view of a main part of a multilayer circuit wiring board according to another embodiment before a circuit pattern is corrected.

FIG. 12 is an enlarged view of a main part of the multilayer circuit wiring board after the circuit pattern shown in FIG. 11 is modified.

FIG. 13 is an enlarged view of a main part before and after a circuit pattern is corrected via a repair free pattern 9 in a multilayer circuit wiring board according to still another embodiment of the present invention.

FIG. 14 is an enlarged sectional view of the same.

FIG. 15 is a plan view of a second pattern 12 in a multilayer circuit wiring board according to another embodiment showing a modification of the wiring pattern 6;

FIG. 16 also shows an LSI mounted on the surface adjacent thereto.
Sectional drawing of the principal part of the electronic circuit device which corrected the circuit pattern between chips via the repair free pattern of the repair area | region provided on the multilayer circuit wiring board.

FIG. 17 also shows a repair area formed on the surface of the circuit correction board, and a circuit pattern between LSI chips mounted on the multilayer circuit wiring board via the circuit correction board provided on the multilayer circuit wiring board. The principal part sectional view of the electronic circuit device corrected via the repair free pattern of the repair area.

FIG. 18 also shows a repair area provided on the back surface of the circuit correction board, and a circuit pattern between LSI chips mounted on the multilayer circuit wiring board via the circuit repair board provided on the multilayer circuit wiring board. Sectional drawing of the principal part of the electronic circuit device corrected through the repair free pattern of the repair area.

FIG. 19 is also an LSI mounted on its surface adjacently.
Sectional drawing of the principal part of the electronic circuit device which corrected the circuit pattern between chips by wire bonding to the repair pad of the repair area provided on the multilayer circuit wiring board.

FIG. 20 is a diagram showing a circuit pattern between LSI chips mounted on a multilayer circuit wiring board having a repair area formed on the surface of a circuit repair board and a thin film layer provided on the surface via the circuit repair board. Sectional drawing of the principal part of the electronic circuit device repaired by wire bonding with the repair pad of the repair area | region provided on the circuit wiring board.

FIG. 21 is a diagram showing a circuit pattern between LSI chips mounted on a multilayer circuit wiring board having a repair area provided on the back surface of a circuit repair board and a thin film layer provided on the front surface via the circuit repair board. Sectional drawing of the principal part of the electronic circuit device repaired by wire bonding with the repair pad of the repair area | region provided on the circuit wiring board.

FIG. 22 is a diagram showing an example in which an LSI chip is mounted on a multilayer circuit wiring board having a thick film conductor wiring and a repair pad connected thereto via a circuit repair board provided with a repair area on the surface, and a repair pad is provided. Sectional drawing of the principal part of the electronic circuit device by which the circuit pattern was corrected through the connection by wire bonding between them.

FIG. 23 is a diagram showing an example in which an LSI chip is mounted on a multilayer circuit wiring board having a thick film conductor wiring and a repair pad connected to the same via a circuit repair board provided with a repair area on the back face, Sectional drawing of the principal part of the electronic circuit device by which the circuit pattern was corrected via the connection by wire bonding between pads.

[Explanation of symbols]

1. Multi-layer circuit wiring board 2. LSI
Chip, 3 ... solder bump, 4
... Pad for terminal connection, 5 ... Conductivity barrier,
6 wiring pattern, 7 repair pattern X,
8: repair pattern Y, 9: repair main pattern, 10: insulating film, 11: first
The pattern of 12 ... the second pattern,
13: third pattern, 14: first interlayer insulating film, 15: second interlayer insulating film,
16: third interlayer insulating film, 17: LSI chip mounting area, 18: wiring pattern cut position, 19 ...
Repair pattern cut position, 20: Solder for wiring pattern / repair pattern X, Y connection, 22: Repair free pattern cut position, 23: Repair pattern X, Y / Solder for repair free pattern connection, 24: Circuit correction board
25 repair pad 26 wire bonding or ribbon bonding 27 repair area 28 conductor conductor for thick film 29 thin film layer

Continued on the front page (72) Inventor Masafumi Okubo 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd. Production Technology Research Laboratory (72) Inventor Hiroshi Watanabe 1-Horiyamashita, Hadano-shi, Kanagawa Prefecture General-purpose computer of Hitachi, Ltd. Within Business Unit (72) Inventor Masakazu Yamamoto 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture Within Hitachi, Ltd. General-purpose Computer Business Division (72) Inventor Tsutomu Imai 1-Horiyamashita, Hadano-shi, Kanagawa Prefecture, General Purpose Computer Division at Hitachi, Ltd. 72) Inventor Shinji Abe 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture, Hitachi, Ltd.General-purpose Computer Business Division (72) Inventor Hiroyuki Hidaka 1-Horiyamashita, Hadano-shi, Kanagawa Prefecture, Hitachi, Ltd.General-purpose Computer Business Division (56) Reference Reference JP-A-62-213147 (JP, A) JP-A-4-345086 (JP, A) Japanese Utility Model Laid-open No. Sho 62-84972 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H05K 3/46

Claims (25)

(57) [Claims] 1. A wiring board having a wiring pattern and a repair pattern in an inner layer via an interlayer insulating film, and having a circuit correction region to be cut and connected to a circuit on these patterns, and a wiring board on the wiring board. A multilayer circuit wiring board having a circuit correcting function, comprising: a terminal connection pad for connecting the provided electronic circuit components; and a conductive via for connecting the wiring pattern to the terminal connection pad. A multilayer circuit wiring board, wherein at least a circuit correction connection area of a repair pattern provided in an inner layer and at least a circuit correction connection area of the wiring pattern are arranged close to each other and located on the same plane. 2. The repair pattern according to claim 1, wherein at least a circuit repair connection area of the repair pattern and at least a circuit repair connection area of the wiring pattern are arranged close to each other, and the repair pattern and the wiring pattern surround the wiring pattern. 2. The multilayer circuit wiring board according to claim 1, which is arranged on the same plane. 3. The repair pattern is constituted by a two-way lattice pattern intersecting the wiring pattern so as to surround the wiring pattern, and is arranged so that at least a main part thereof is located on the same plane as the wiring pattern. 3. The multilayer circuit wiring board according to claim 1, wherein: 4. At least a circuit repair area of the repair pattern and at least a circuit repair connection area of the wiring pattern are arranged on the same plane as the terminal connection pads, and are other than the terminal connection pads. multilayer circuit wiring board according to any one of claims 1 to 3 comprising covering the region with the insulating film. 5. The device according to claim 1, wherein said cut and connection circuit correction area is arranged outside a projection area of said terminal connection pad.
5. The multilayer circuit wiring board according to any one of items 4 to 4. 6. The intersection of the repair patterns formed of the two-way grid pattern intersecting each other is connected to the repair pattern in any one direction via a conductive via and via an interlayer insulating film. 4. The multilayer circuit wiring board according to claim 3, wherein the multi-layer circuit wiring board comprises a three-dimensional intersection where the insulation between the two is maintained. 7. The multi-layer structure according to claim 3, wherein the intersection of the repair patterns formed of the two-way grid pattern intersecting each other has a structure in which both are connected to maintain electrical continuity. Circuit wiring board. 8. A mounting area on which a plurality of electronic circuit components are mounted adjacent to each other in a matrix on the wiring board, and the repair pattern is arranged in an inner layer area on a projection surface of the mounting area. The end of this repair pattern is
It is arranged up to the outer periphery of the projection surface of the mounting area, connected to the repair pad provided on the surface layer via the end at the end, so that the circuit correction between the electronic circuit components mounted on the wiring board can be performed. The multilayer circuit wiring board according to any one of claims 1 to 7 , comprising: 9. A circuit correction board having a circuit correction function is provided between a multilayer circuit wiring board and an electronic circuit component mounted thereon, and the multilayer circuit board is provided on one of the front and back surfaces of the circuit correction board. formed by disposing a repair pattern having the same circuit modification functions as those disposed on the wiring board according to claim 1乃
9. The multilayer circuit wiring board according to any one of Nos. 8 to 8 . 10. A mounting area on which a plurality of electronic circuit components are mounted adjacent to each other in a matrix on the wiring board, wherein the mounting area in an inner layer area between the adjacent mounting areas is formed. The repair free pattern is arranged along the outer periphery of the projection surface in a matrix with a two-way grid pattern intersecting, and is arranged on the same plane as the wiring pattern and the repair pattern, and the repair free pattern and the repair pattern are arranged. The circuit according to any one of claims 1 to 7 , wherein a circuit between adjacent electronic circuit component mounting areas can be corrected through the intermediary of the electronic component.
The multilayer circuit wiring board according to any one of the above. 11. An intersecting portion between the repair free patterns composed of the two-way grid pattern intersecting with each other, the repair free pattern in any one direction is connected via a conductive via and an interlayer insulating film. 11. The multilayer circuit wiring board according to claim 10, comprising a three-dimensional intersection where the insulation between the two is maintained through the intersecting portion. 12. The repair free pattern according to claim 10, wherein the intersection between the repair free patterns formed by the two-way grid pattern intersects with each other, and the repair free pattern is electrically connected. Multilayer circuit wiring board. 13. The multilayer circuit wiring board according to any one of the above cross two directions repair pattern and the repair free pattern formed by arranged on the same plane claims 10 to 12. 14. A repair layer according to claim 1, wherein a barrier layer made of an insulating film is provided between the repair pattern, the repair free pattern, and the wiring pattern and an interlayer insulating film thereunder .
The multilayer circuit wiring board according to any one of the above. 15. A multi-layer circuit wiring circuit modification method of a substrate according to any one of claims 1 to 9, remove the wiring pattern and predetermined circuit insulating membrane with a cut-modified region of the repair pattern Cutting the exposed wiring of the repair area, removing the insulating film on a predetermined circuit connection repair area of the wiring pattern and the repair pattern, and conducting a conductor between the exposed wires of the repair area. Connecting the multi-layer circuit wiring board. 16. A circuit modification method for a multilayer circuit wiring board of any one of claims 10 to 14 serial <br/> mounting, wiring patterns, repair pattern and a predetermined circuit repair free pattern Removing the insulating film on the cut repair area and cutting the exposed wiring of the repair area, and removing the insulating film on a predetermined circuit connection repair area of the wiring pattern, the repair pattern, and the repair free pattern. Connecting the conductors between the exposed wirings of the repair area with a conductor, so that a circuit between adjacent electronic circuit component mounting areas can be repaired via the repair pattern and the repair free pattern. Circuit repair method for a multi-layer circuit wiring board. 17. A step of removing an insulating film on the circuit cut correction area and cutting the exposed wiring of the correction area, respectively, includes a step of forming a hole in the insulating film by laser beam irradiation, and a step of subsequently performing wiring by laser beam irradiation. A step of removing the insulating film on the circuit connection repair area and connecting the conductors between the exposed wirings of the repair area by a laser beam irradiating step; Connecting the conductors to each other with a conductor.
Or a circuit repair method for a multilayer circuit wiring board according to 16 above. 18. The method according to claim 17, wherein, in the step of piercing the insulating film by irradiating the laser beam, a hole diameter of the insulating film on the circuit cut correction area is made smaller than a hole diameter of the insulating film on the circuit connection correction area. Circuit repair method for a multilayer circuit wiring board. 19. The circuit repair method for a multilayer circuit wiring board according to claim 17, wherein the step of connecting conductors between the wirings comprises a liquid layer / solid phase connection step in which a brazing material is supplied into the openings and fused. 20. The circuit repair method for a multilayer circuit board according to claim 17, wherein the step of connecting the conductors between the conductors comprises a step of wire bonding or ribbon bonding by an ultrasonic thermocompression bonding method. 21. The circuit repair method for a multilayer circuit wiring board according to claim 17, wherein the step of connecting the wires to the conductors comprises the step of connecting the wires with a brazing material. 22. The method according to claim 17, wherein the step of connecting conductors between the wirings comprises the step of depositing and connecting conductors on the exposed wirings by laser CVD. 23. A circuit repair method for a multilayer circuit wiring board according to claim 8, wherein the step of repairing the circuit between the electronic circuit components includes the step of wire bonding or ribbon bonding connection to a repair pad to be repaired. circuit modification method for a multilayer circuit wiring board according to any one of claims 15 to 18 comprising a. 24. Any of claims 1 to 8 and 10 to 12
An electronic device comprising: an electronic circuit component mounted on a multilayer circuit wiring board according to any one of the above, and a terminal connection pad provided in a mounting area on the substrate and a terminal of the electronic circuit component electrically connected. Circuit device. 25. A circuit correction board and an electronic circuit component according to claim 9 mounted on a multilayer circuit wiring board, and a terminal connection pad provided in a mounting area on said multilayer circuit wiring board and a circuit board. An electronic circuit device comprising a terminal connection pad and a terminal of an electronic circuit component electrically connected to each other.