JPH06209169A - Multilayer circuit wiring board having circuit correction function, its circuit correction method and electronic circuit device - Google Patents

Multilayer circuit wiring board having circuit correction function, its circuit correction method and electronic circuit device

Info

Publication number
JPH06209169A
JPH06209169A JP5002315A JP231593A JPH06209169A JP H06209169 A JPH06209169 A JP H06209169A JP 5002315 A JP5002315 A JP 5002315A JP 231593 A JP231593 A JP 231593A JP H06209169 A JPH06209169 A JP H06209169A
Authority
JP
Japan
Prior art keywords
circuit
repair
pattern
wiring board
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5002315A
Other languages
Japanese (ja)
Inventor
Kiyoshi Matsui
清 松井
Ryohei Sato
了平 佐藤
Masakazu Yamamoto
雅一 山本
Tsutomu Imai
勉 今井
Shinji Abe
慎二 安部
Hiroyuki Hidaka
博之 日高
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5002315A priority Critical patent/JPH06209169A/en
Publication of JPH06209169A publication Critical patent/JPH06209169A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0286Programmable, customizable or modifiable circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To obtain a multilayer circuit board or a circuit correction board having circuit pattirn correction function wherein circuit correction is easily enabled at the time of circuit correction work of an electronic circuit device, and high density mounting of electronic components can be realized, its correction method, and an electronic circuit device wherein electronic components are mounted on the board. CONSTITUTION:Correction pads 6 are arranged on the peripheral part of LSI chips 2 mounted on a board 1. A plurality of wiring patterns 5 are arranged in the vicinity of the pads 6. A correction pattern and connection pads 7 are arranged between the LSI chips 2 Thereby structure wherein correction of wiring (cut and connection is enabled on the board surface layer is obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、回路修正機能を有する
多層回路配線基板と基板の回路修正方法及びその回路配
線基板に電子部品を搭載実装してなる電子回路装置に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit wiring board having a circuit correcting function, a circuit correction method for the board, and an electronic circuit device in which electronic parts are mounted and mounted on the circuit wiring board.

【0002】[0002]

【従来の技術】LSIの高速、高集積化に伴い、多数の
LSIを搭載した電子回路装置では、回路配線基板上の
高密度実装技術が大変重要である。即ち、高密度化を行
なうことにより、LSI間の配線経路を短くし、電気信
号の基板内配線遅延時間の短縮を図り、電子回路装置と
しての高速動作を可能にする。
2. Description of the Related Art With the high speed and high integration of LSIs, a high-density mounting technique on a circuit wiring board is very important in electronic circuit devices having a large number of LSIs mounted thereon. That is, by increasing the density, the wiring path between the LSIs is shortened, the wiring delay time in the board of the electric signal is shortened, and high-speed operation as an electronic circuit device is enabled.

【0003】このため高密度実装技術としては、例え
ば、LSIチップ面の電極にはんだ等の金属からなるバ
ンプを形成し、このバンプを介して上記チップを回路配
線基板上にフェイスダウンボンディングするフリップチ
ップ実装方式がある。
Therefore, as a high-density mounting technique, for example, a flip chip in which bumps made of metal such as solder are formed on electrodes on the surface of an LSI chip and the chips are face-down bonded onto a circuit wiring board via the bumps. There is a mounting method.

【0004】また、LSIの高集積化によりLSIチッ
プの入出力端子数が増えると共に回路配線基板内の信号
配線数も増大するため、LSIを搭載する回路配線基板
は多層化が必要となってくる。よって、回路配線基板に
は、微細、多点の電極用端子形成技術及び多層回路配線
技術が要求される。
Further, since the number of input / output terminals of the LSI chip increases and the number of signal wirings in the circuit wiring board increases due to the high integration of the LSI, the circuit wiring board on which the LSI is mounted needs to be multilayered. . Therefore, the circuit wiring board is required to have a fine and multi-point electrode terminal forming technique and a multilayer circuit wiring technique.

【0005】ところで、このような多層回路配線基板に
おいては、微細配線パターンの製造工程上での不良の補
修、基板へのLSI搭載後にLSI間の論理変更を行な
う等の回路の修正が必要となってくる。具体的には以下
に示すような問題、例えば、(1)回路配線の設計不
良、(2)製造不良、(3)配線経路上に生じる信号伝
播遅延時間や配線パターンの欠陥等によるLSIの動作
不良、(4)電子回路装置の性能アップを図るための設
計変更、等の問題から回路変更が必要となる。
By the way, in such a multilayer circuit wiring board, it is necessary to repair the defect in the manufacturing process of the fine wiring pattern and to correct the circuit such as changing the logic between the LSIs after mounting the LSI on the board. Come on. Specifically, the following problems, for example, (1) circuit wiring design failure, (2) manufacturing failure, (3) signal propagation delay time occurring on the wiring route, wiring pattern defect, etc. Circuit changes are necessary due to problems such as defects and (4) design changes for improving the performance of electronic circuit devices.

【0006】そのため、多層回路配線基板には、実装密
度及びLSIの動作性能を低下させることがない回路変
更用の補修パターン構造が必要とされ、これまでにも各
種各様の構造が提案されている。
Therefore, the multilayer circuit wiring board requires a repair pattern structure for circuit modification which does not reduce the packaging density and the operating performance of the LSI, and various structures have been proposed so far. There is.

【0007】例えば、その一つの手法として、多層回路
基板上に搭載する電子回路部品の投影面外の周辺に、補
修配線接続用パッドやEC(Engineering Change:技
術変更)パッドを設け、このパッドにワイヤボンディン
グを行い回路変更を行う方法が知られている。しかし、
この手法では、回路基板表面に補修用パッドを設けてる
ため、回路基板に対する電子回路部品の搭載密度(搭載
電子回路部品の総面積/回路基板面積)を著しく低下さ
せている。なお、この種の技術に関連するものとして、
例えば特開昭62−25437号公報や、マイクロエレ
クトロニクスパッケージングハンドブック(第39頁、
図1〜28、日経BP社発行、1991年3月27日)
が挙げられる。
For example, as one of the methods, a pad for repair wiring connection or an EC (Engineering Change) pad is provided around the projection surface of an electronic circuit component mounted on a multilayer circuit board, and this pad is provided on this pad. A method of performing wire bonding to change a circuit is known. But,
In this method, since the repair pad is provided on the surface of the circuit board, the mounting density of electronic circuit components on the circuit board (total area of mounted electronic circuit components / circuit board area) is significantly reduced. In addition, as related to this kind of technology,
For example, Japanese Patent Application Laid-Open No. 62-25437 and Microelectronics Packaging Handbook (page 39,
(Figs. 1-28, published by Nikkei BP, March 27, 1991)
Is mentioned.

【0008】そこで、この搭載密度を改善する他の手法
として、回路基板上に設けるパッド構成に改良を加え、
電子部品の投影面内の素子接続用端子パッドの一部にも
補修パッドを形成し、補修パッドの占有面積を少なくす
る方法が提案されている。この方法は、(1)基板の表
面層に設けてある電子部品の端子接続用パッドに、改造
時カット用パッドと改造用パターン接続パッドとを設け
ておき、この改造時カット用パッドを介して接続されて
ある基板内配線パターンと、改造時に改造用パターン接
続パッドと接続される改造用パターンとを基板の内層に
それぞれ設けた構造とし、改造時には、一方では表面層
に設けられ端子接続用パッドと接続された改造時カット
用パッドを端子接続用パッドから切断し、他方では表面
層上の端子接続用パッドと接続された改造用パターン接
続パッドと内層に設けられた改造用パターンとの間に専
用のバイアを設けることにより両者を接続するもの、さ
らには(2)上記改造用パターンを基板内に2層構造と
して設け、表面層には上記改造用パターン接続パッドと
して、これら2層間をバイア接続が可能な位置にチャネ
ル乗り替え用導通形成位置を示すチャネル乗り替え用導
通バイア形成用パッドを設けているものである。なお、
この種の技術に関連するものとしては、例えば特開昭6
3−213399号公報が挙げられる。
Therefore, as another method for improving the mounting density, the pad structure provided on the circuit board is improved,
A method has been proposed in which a repair pad is also formed on a part of the element connection terminal pad on the projection surface of the electronic component to reduce the area occupied by the repair pad. According to this method, (1) a pad for connecting terminals of an electronic component provided on a surface layer of a substrate is provided with a cutting pad for modification and a pattern connection pad for modification, and the pad for cutting on modification is inserted through the pad for cutting. The structure is such that the wiring pattern in the board that is connected and the modification pattern that is connected to the modification pattern connection pad at the time of modification are respectively provided in the inner layer of the board. The cutting pad for remodeling connected to the terminal is cut from the terminal connection pad, and on the other hand, between the remodeling pattern connection pad connected to the terminal connection pad on the surface layer and the remodeling pattern provided on the inner layer. A dedicated via is provided to connect the two, and (2) the modification pattern is provided as a two-layer structure in the substrate, and the modification pattern is connected to the surface layer. As a pad, in which are provided these conductive vias formed pad channel riding replacement showing the two layers in the via connection is positionable conduction forming position for channel riding replacement. In addition,
As a technique related to this kind of technology, for example, Japanese Patent Laid-Open No.
3-213399 gazette is mentioned.

【0009】[0009]

【発明が解決しようとする課題】上記後者の修正方法
は、前者に比べて回路基板上に設ける補修パッドの占有
面積を低減することができるという点で優れている。し
かし、多層回路配線基板にLSIチップをフリップチッ
プ実装した後に、設計変更やLSIの動作不良が生じ回
路修正を行なう場合、既に搭載したLSIチップを取り
外す必要があり、以下に示すような問題点が存在する。
The latter repair method is superior to the former in that the area occupied by the repair pad provided on the circuit board can be reduced. However, after flip-chip mounting an LSI chip on a multilayer circuit wiring board, if a design change or LSI malfunction occurs and circuit correction is performed, it is necessary to remove the already mounted LSI chip, which causes the following problems. Exists.

【0010】すなわち、回路修正を行なうための作業工
程として、 (1)LSIチップの取外し (2)レベリング(LSIチップ取外し後の多層回路配
線基板側の端子接続パッドには、余剰はんだが残るた
め、このはんだを取り除く作業) (3)多層回路配線基板上での回路修正作業 (4)LSIチップを多層回路配線基板上へ再搭載する
ために、LSIチップの端子接続用パッドへはんだを供
給する作業 (5)回路修正後の多層回路配線基板上へ、LSIチッ
プを搭載位置合わせし、はんだで接合させる作業が必要
である。 上記、(1)〜(5)の各作業を行なうためには、各作
業用設備の導入、作業者の確保等が必要になると共に、
回路修正時間に要する時間もかなり掛ってしまうという
問題がある。
That is, as work steps for modifying the circuit, (1) removal of the LSI chip (2) leveling (excessive solder remains on the terminal connection pads on the multilayer circuit wiring board side after the removal of the LSI chip, Work to remove this solder) (3) Work to correct the circuit on the multilayer circuit wiring board (4) Work to supply solder to the terminal connection pads of the LSI chip in order to remount the LSI chip on the multilayer circuit wiring board (5) It is necessary to align the mounting position of the LSI chip on the multilayer circuit wiring board after the circuit modification, and to join it by soldering. In order to perform each of the above-mentioned operations (1) to (5), it is necessary to introduce equipment for each operation, secure workers, etc., and
There is a problem that it takes a considerable amount of time to correct the circuit.

【0011】したがって、本発明の目的は、上記従来の
技術の問題点を解消することにあり、第1の目的はLS
Iチップを取り外さずに回路修正が行なえる多層回路配
線基板を、第2の目的はその回路配線基板の回路修正方
法を、そして第3の目的はこの基板に電子部品を搭載実
装した電子回路装置を、それぞれ提供することにある。
Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art, and the first object is the LS.
A multi-layer circuit wiring board capable of circuit modification without removing the I-chip, a second purpose is a circuit modification method of the circuit wiring board, and a third purpose is an electronic circuit device in which electronic parts are mounted and mounted on the board. To provide each.

【0012】[0012]

【課題を解決するための手段】上記目的を達成するため
に、本発明では多層回路配線基板上に搭載する電子回路
部品の投影面の外周辺に補修パッドを設けると共に、そ
の近傍に修正作業用の複数の配線パターンを設け、LS
Iチップ間には、補修パターンを設けた構造とした。ま
た、多層回路配線基板とその上に搭載する電子回路部品
との間に、上記補修パッド、修正作業用の配線パターン
を配設した回路修正基板を設ける構造とした。
In order to achieve the above object, according to the present invention, a repair pad is provided on the outer periphery of the projection surface of an electronic circuit component mounted on a multilayer circuit wiring board, and a repair pad is provided near the repair pad. Multiple wiring patterns of
A repair pattern was provided between the I chips. Further, the circuit repair board having the repair pad and the wiring pattern for repair work is provided between the multilayer circuit wiring board and the electronic circuit component mounted thereon.

【0013】以下、本発明の具体的な目的達成手段につ
いて説明する。まず、上記第1の目的は、多層回路配線
基板上に搭載した電子回路部品の周辺領域(電子回路部
品の投影面外周領域)に、回路補修中継路となる補修
パッドと、一端が内層配線に接続され他端が補修パッ
ドに近接対向し表面層上に延在する複数本の配線パター
ンとを設けて配線パターンの回路修正領域を形成すると
共に、電子回路部品の投影面内領域に電子回路部品の
端子を接続し、かつ内層配線パターンに接続された端子
接続用パッドを形成して成る多層回路配線基板もしくは
回路修正基板により、達成される。なお、回路修正基板
とは、回路修正機能を有する配線基板であり実質的に多
層回路配線基板と同一機能、構造を有するものである。
これが単独で使用される場合は多層回路配線基板とな
り、他の回路配線基板上に搭載される場合には回路修正
基板となる。したがって、以下の説明では単独使用の多
層回路配線基板の場合を例とする。
The specific means for achieving the object of the present invention will be described below. First, the first object is to provide a repair pad serving as a circuit repair relay path and an inner layer wiring at one end in the peripheral area of the electronic circuit component mounted on the multilayer circuit wiring board (outer peripheral area of the projected surface of the electronic circuit component). A plurality of wiring patterns, which are connected to each other and closely face the repair pad and extend on the surface layer, are provided to form a circuit correction area of the wiring pattern, and an electronic circuit component is provided in the projection plane area of the electronic circuit component. Is achieved by a multilayer circuit wiring board or a circuit modification board which is formed by connecting the terminals of (1) and forming terminal connection pads connected to the inner layer wiring pattern. The circuit correction board is a wiring board having a circuit correction function, and has substantially the same function and structure as the multilayer circuit wiring board.
When it is used alone, it becomes a multilayer circuit wiring board, and when it is mounted on another circuit wiring board, it becomes a circuit correction board. Therefore, in the following description, the case of a single-use multilayer circuit wiring board is taken as an example.

【0014】また、上記多層回路配線基板には、隣接し
て複数個の電子回路部品がマトリクス状に搭載される搭
載領域が形成されており、好ましくは、搭載領域間に設
けられた上記回路修正領域内の補修パッドに隣接して複
数本の補修パターンを配置すると共に、補修パターンの
両端には接続を容易とするために回路配線接続用の接続
パッドを設けた回路修正領域構造とすることが望まし
い。上記補修パッドは、第1の回路補修中継路を形成
し、配線パターンを修正する時に一方では配線パターン
を接続すると共に、他方では第2の回路補修中継路とな
る補修パターンを接続する浮遊電極パッドとなる。
Further, the multi-layer circuit wiring board is formed with a mounting area adjacent to which a plurality of electronic circuit components are mounted in a matrix form, and preferably the circuit modification provided between the mounting areas. A circuit modification area structure may be provided in which a plurality of repair patterns are arranged adjacent to the repair pad in the area and connection pads for circuit wiring connection are provided at both ends of the repair pattern to facilitate connection. desirable. The repair pad forms a first circuit repair relay path, and when the wiring pattern is modified, one of the floating pads is connected to the wiring pattern while the other is connected to the repair pattern to be the second circuit repair relay path. Becomes

【0015】また、上記第2の目的は、上記多層回路配
線基板を用いた回路修正方法であって、配線パターン
及び補修パターンの予め定められた回路カット修正領域
の配線をそれぞれカットする工程と、前記配線パター
ン、補修パッド、補修パターン、接続パッド上の修正領
域の相互間を導体接続する工程とを有して成り、前記補
修パッドと接続パッドまたは、補修パターンを介して隣
接する電子回路部品搭載領域間の回路修正を行えるよう
にして成る多層回路配線基板の回路修正方法により達成
される。また、(1)上記配線をカットする工程として
は、レーザビーム照射や、その他例えばマイクロカッ
タ、超音波カッタなどの機械的にカットする工程、また
(2)配線、パッド間を接続する工程としては、はんだ
の如きろう材を用い溶融接続する工程とするか、ワイヤ
ボンディング、リボンボンディング、あるいは導体箔を
用いて接続する工程とか、ワイヤを用いその両端をろう
材を用い各々の配線、またはパッド間を接続する工程と
で構成することが望ましい。
A second object is a circuit repairing method using the above-mentioned multilayer circuit wiring board, wherein a step of cutting wires in predetermined circuit cut repair areas of a wiring pattern and a repair pattern, respectively. A step of conducting a conductor connection between the wiring pattern, the repair pad, the repair pattern, and the correction area on the connection pad, and mounting the electronic circuit component adjacent to the repair pad and the connection pad or the repair pattern. This is achieved by a method of modifying a circuit of a multilayer circuit wiring board which enables modification of a circuit between regions. Further, (1) as the step of cutting the wiring, laser beam irradiation and other steps such as mechanically cutting with a micro cutter, an ultrasonic cutter, etc., and (2) as the step of connecting the wiring and the pad , A process of fusion connection using a brazing material such as solder, or a process of connecting using wire bonding, ribbon bonding, or a conductor foil, or using a brazing material at both ends using a brazing material for each wiring or between pads It is desirable to configure with the process of connecting.

【0016】また、上記第3の目的は、上記第1の目的
が達成される多層回路配線基板上に、電子回路部品を搭
載し、前記基板上の搭載領域に設けられた端子接続用パ
ッドと電子回路部品の端子とを電気的に接続して成る電
子回路装置により、達成される。通常、LSI等の電子
回路部品は基板上にマトリクス状に多数個接続され、高
密度実装が達成される。また、この種の回路基板は、入
出力端子が接続された第1の厚膜基板上に、第2の薄膜
多層回路配線基板が一体的に接続、形成されて構成され
る。この第1の厚膜基板は、一般に裏面に入出力端子と
してのピンが植設され、表面には第2の薄膜多層回路配
線基板を形成する接続端子群が設けられており、セラミ
ックスやガラスエポキシ基板等の剛性のある多層回路配
線板で構成される。
A third object of the present invention is to mount electronic circuit components on a multilayer circuit wiring board which achieves the first object, and to provide terminal connecting pads provided in a mounting area on the board. This is achieved by an electronic circuit device that is electrically connected to terminals of electronic circuit components. Usually, a large number of electronic circuit components such as LSI are connected in a matrix on a substrate to achieve high-density mounting. Further, this type of circuit board is configured by integrally connecting and forming a second thin film multilayer circuit wiring board on a first thick film board to which input / output terminals are connected. This first thick-film substrate is generally provided with pins as input / output terminals on its back surface, and a connection terminal group forming a second thin-film multilayer circuit wiring board is provided on its front surface. It is composed of a rigid multilayer circuit wiring board such as a substrate.

【0017】また、上記第3の目的は、上記第1の目的
が達成される回路修正基板を前記多層回路配線基板上に
接続し、上記回路修正基板上に電子回路部品を搭載し、
前記多層回路配線基板上の搭載領域に設けられた端子接
続用パッドと、回路修正基板上の端子接続用パッドと電
子回路部品の端子とを各々電気的に接続して成る電子回
路装置により達成される。
A third object is to connect a circuit modification board, which achieves the first object, onto the multilayer circuit wiring board, and mount electronic circuit parts on the circuit modification board.
This is achieved by an electronic circuit device in which a terminal connection pad provided in a mounting area on the multilayer circuit wiring board, a terminal connection pad on a circuit correction board, and a terminal of an electronic circuit component are electrically connected to each other. It

【0018】[0018]

【作用】本発明の回路修正機能を有する多層回路配線基
板または回路修正基板によれば、多層回路配線基板上に
搭載した電子回路部品の周辺で補修作業が行え、従来行
っていたような一度搭載した電子回路部品を取り外す必
要が無くなり、補修作業にかかる作業時間や、設備投資
を大幅に低減できる。また、一つの補修パッドに対し、
複数の配線パターンを共用させることにより、補修時に
必要な補修パッド数を低減させることができ、多層回路
配線基板面積の大形化が防止でき、電子回路部品の搭載
密度の向上を図ることができる。
According to the multilayer circuit wiring board or the circuit modification board having the circuit modifying function of the present invention, the repair work can be performed around the electronic circuit component mounted on the multilayer circuit wiring board, and it can be mounted once as in the past. There is no need to remove the electronic circuit parts that have been removed, and the work time required for repair work and equipment investment can be greatly reduced. Also, for one repair pad,
By sharing a plurality of wiring patterns, it is possible to reduce the number of repair pads required at the time of repair, prevent the multilayer circuit wiring board area from increasing, and improve the mounting density of electronic circuit components. .

【0019】[0019]

【実施例】以下、図面により本発明の一実施例を説明す
る。 〈実施例1〉図1は、本発明の一実施例に係る回路修正
機能を有する多層回路配線基板の要部断面図である。図
1において、1は本発明の多層回路配線基板、2はLS
Iチップ、3ははんだバンプ、4は端子接続用パッド、
5は表面層上に設けた配線パターン、5’は多層回路配
線基板の内層に配設した配線パターン、6は補修パッ
ド、7は接続パッドである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. <Embodiment 1> FIG. 1 is a cross-sectional view of essential parts of a multilayer circuit wiring board having a circuit correcting function according to an embodiment of the present invention. In FIG. 1, reference numeral 1 is a multilayer circuit wiring board of the present invention, and 2 is an LS.
I chip, 3 solder bumps, 4 terminal connection pads,
Reference numeral 5 is a wiring pattern provided on the surface layer, 5'is a wiring pattern provided on the inner layer of the multilayer circuit wiring board, 6 is a repair pad, and 7 is a connection pad.

【0020】また、図2は図1の多層回路配線基板上に
4個のLSIチップを搭載する場合の表面層の各パター
ンを示し、9は破線で示したLSI搭載領域、10は両
端に接続パッド7を有する補修パターンである。図1、
図2に示すように、LSIチップ搭載領域9周辺に補修
パッド6が配置され、それに近接させて配線パターン5
が配設されている。なお、この実施例では1個の補修パ
ッド6に2つの配線パターン5が近接された構造である
が、配線ピッチが可能な限りの配線パターン数を設ける
ことができる。また、隣接するLSI搭載領域9間及び
外周には、補修パッド6に近接して複数本の補修パター
ン10を配置し、その両端に接続パッド7が配設してあ
る。
Further, FIG. 2 shows each pattern of the surface layer when four LSI chips are mounted on the multilayer circuit wiring board of FIG. 1, 9 is an LSI mounting area shown by a broken line, and 10 is both ends connected. It is a repair pattern having a pad 7. Figure 1,
As shown in FIG. 2, the repair pad 6 is arranged around the LSI chip mounting area 9, and the wiring pattern 5 is placed close to the repair pad 6.
Is provided. In this embodiment, the two wiring patterns 5 are arranged close to one repair pad 6, but as many wiring patterns as possible can be provided. Further, a plurality of repair patterns 10 are arranged between the adjacent LSI mounting areas 9 and on the outer periphery thereof in the vicinity of the repair pad 6, and the connection pads 7 are arranged at both ends thereof.

【0021】次に、上記図1、図2の多層回路配線基板
を用いた場合の回路修正後の構造を図3、図4を用いて
説明する。図3、図4において、8はボンディングワイ
ヤ、11は配線パターン5のカット領域、12は配線パ
ターン5/補修パッド6の接続領域、14は補修パター
ン10のカット領域である。以下、図4の平面図におい
て、一方のLSI搭載領域内の端子接続用パッド4のA
から、隣接する他方のLSI搭載領域内のBまでの回路
修正方法について述べる。
Next, the structure after the circuit modification when the multilayer circuit wiring board shown in FIGS. 1 and 2 is used will be described with reference to FIGS. 3 and 4, 8 is a bonding wire, 11 is a cut area of the wiring pattern 5, 12 is a connection area of the wiring pattern 5 / repair pad 6, and 14 is a cut area of the repair pattern 10. Hereinafter, in the plan view of FIG. 4, A of the terminal connecting pad 4 in one LSI mounting area is shown.
To B in the other adjacent LSI mounting area will be described.

【0022】〔手順1〕端子接続用パッドA、Bに導体
接続されている配線パターン5において、配線パターン
5のカット領域11で両者の配線をカットする。カット
手段は、レーザビーム、マイクロカッタ、超音波カッタ
など何れの手法でも良い。 〔手順2〕カットされた配線パターン5と、これに近接
して設けた補修パッド6間を導体8で接続する。 〔手順3〕上記補修パッド6と接続パッド7間を導体8
で接続する。 〔手順4〕隣接する他の補修パターン10に形成された
接続パッド7間を導体8で接続する。なお、上記手順
2、3、4における導体での接続方法として、接続領域
12のように接続部分が相互に近接している個所は、は
んだ接続、導体8のように少し離れた個所は、ワイヤボ
ンディング、リボンボンディング、導体箔、ワイヤ両端
をはんだで接続する等の固相/固相、もしくは液層/固
相の接続方法が望ましい。ワイヤ、リボン、導体箔等の
接続は、はんだ接続のみならず、超音波ボンディングに
よることもできる。
[Procedure 1] In the wiring pattern 5 that is conductor-connected to the terminal connecting pads A and B, both wirings are cut in the cut area 11 of the wiring pattern 5. The cutting means may be any method such as a laser beam, a micro cutter, or an ultrasonic cutter. [Procedure 2] The cut wiring pattern 5 and the repair pad 6 provided in the vicinity thereof are connected by the conductor 8. [Procedure 3] Conductor 8 is provided between the repair pad 6 and the connection pad 7.
Connect with. [Procedure 4] The connection pads 7 formed on the other adjacent repair patterns 10 are connected by the conductors 8. As a method of connecting with a conductor in the above steps 2, 3, and 4, a portion where the connecting portions are close to each other, such as the connecting region 12, is a solder connection, and a portion such as the conductor 8 is slightly apart is a wire. A solid phase / solid phase or liquid layer / solid phase connection method such as bonding, ribbon bonding, conductor foil, or connecting both ends of a wire with solder is desirable. Connection of wires, ribbons, conductor foils, etc. can be made not only by solder connection but also by ultrasonic bonding.

【0023】また、他の回路修正方法としては、(1)
図4に示した端子接続パッド4のCからDまでの回路修
正方法のように、端子接続用パッド4のC、Dに接続し
た補修パッド6と補修パターン10間を接続領域12で
示すように直接導体接続し、補修パターン10の接続領
域12に近い部分をカットすることにより回路修正が行
える。補修パターン10のカットは、必ずしも必要では
ないがカットすることにより、冗長回路となるのを避け
てパターンの浮遊容量を低減したり、他端の接続パッド
7を他の回路修正に有効に利用することができるので、
このような場合にはカットするのが望ましい。また、
(2)上記手順1、2によって端子接続用パッド4の
A、Bに接続された各々の補修パッド6間を、直接ワイ
ヤボンディング、リボンボンディング、またはワイヤ両
端を各補修パッド6に対しはんだ付けする等の接続方法
により実現することもできる。
As another circuit modification method, (1)
As in the circuit modification method from C to D of the terminal connection pad 4 shown in FIG. 4, as shown by the connection area 12 between the repair pad 6 and the repair pattern 10 connected to C and D of the terminal connection pad 4. The circuit can be corrected by directly connecting the conductors and cutting the portion of the repair pattern 10 near the connection region 12. Cutting of the repair pattern 10 is not always necessary, but by cutting it, the stray capacitance of the pattern is reduced by avoiding a redundant circuit, and the connection pad 7 at the other end is effectively used for other circuit modification. Because you can
In such a case, it is desirable to cut. Also,
(2) Direct wire bonding, ribbon bonding, or both ends of the wires are soldered to the respective repair pads 6 between the respective repair pads 6 connected to A and B of the terminal connecting pads 4 by the above steps 1 and 2. It can also be realized by a connection method such as.

【0024】〈実施例2〉次に、図5、図6を用いて実
施例1で得られた多層回路配線基板1上に、同様の方法
で作成した回路修正機能を有する回路修正基板13を介
してLSIチップ2を搭載した場合の回路修正方法につ
いて述べる。図5は多層回路配線基板1上に、端子接続
パッド4のEからFまでの回路修正を行った回路修正基
板13を搭載した電子回路装置の平面図、図6はその要
部断面図で、13は回路修正基板を示す。なお、回路修
正基板13に設けられた補修パット6には、裏面の多層
回路配線基板1の端子接続用パッド4に接続するため配
線及び接続端子が形成されている。回路修正方法は、上
記実施例1で示した手順1〜4を組み合わせることによ
り実現できる。
<Embodiment 2> Next, a circuit-correcting board 13 having a circuit-correcting function prepared by the same method is formed on the multilayer circuit wiring board 1 obtained in Embodiment 1 with reference to FIGS. 5 and 6. A circuit correction method when the LSI chip 2 is mounted via the above will be described. FIG. 5 is a plan view of an electronic circuit device in which a circuit correction board 13 in which the circuit of the terminal connection pads 4 from E to F is modified is mounted on the multilayer circuit wiring board 1, and FIG. Reference numeral 13 denotes a circuit correction board. The repair pad 6 provided on the circuit correction substrate 13 is provided with wiring and connection terminals for connecting to the terminal connection pads 4 of the multilayer circuit wiring substrate 1 on the back surface. The circuit modification method can be realized by combining the steps 1 to 4 shown in the first embodiment.

【0025】以上述べたように、本実施例によれば多層
回路配線基板上に搭載した電子回路部品の周辺に回路修
正用の補修パッドを設け、複数の配線パターンを近接し
て配置し、配線カット及び接続を基板表面層上で行うこ
とにより、既に基板に搭載された電子回路部品を取り外
すことなく回路修正が行え、作業時間の短縮や、設備投
資の低減を図ることができる。
As described above, according to this embodiment, repair pads for circuit correction are provided around electronic circuit components mounted on a multilayer circuit wiring board, and a plurality of wiring patterns are arranged in close proximity to each other. By performing the cutting and connection on the surface layer of the substrate, the circuit can be corrected without removing the electronic circuit components already mounted on the substrate, and the working time and the facility investment can be reduced.

【0026】[0026]

【発明の効果】以上詳述したとおり、本発明により初期
の目的を達成することができた。即ち、回路パターンの
修正機能を備えた本発明の多層回路配線基板または回路
修正基板においては、基板上に搭載した電子回路部品の
周辺に補修パッドを設け複数の配線パターンを近接して
配置させることにより、配線の修正を基板表面層上で容
易に行え、既に搭載した電子回路部品の取外し工程が削
除でき、回路修正の作業時間短縮や、設備投資低減が行
えるとともに、1個の補修パッドに対し、複数個の配線
パターンを共用させることにより、基板上に搭載する電
子回路部品の搭載密度を向上させることができる。ま
た、多層回路配線基板に比べ回路修正基板は、基板サイ
ズが大幅に小さくできるため、基板作成時の歩留を向上
させることができ、基板作成コストの低減が可能とな
る。
As described above in detail, the initial object can be achieved by the present invention. That is, in the multilayer circuit wiring board or the circuit correction board of the present invention having the function of correcting the circuit pattern, a repair pad is provided around the electronic circuit component mounted on the board to arrange a plurality of wiring patterns close to each other. The wiring can be easily modified on the surface layer of the board, the removal process of the electronic circuit parts already mounted can be deleted, the work time for circuit modification and the equipment investment can be reduced, and one repair pad can be used. By sharing a plurality of wiring patterns, the mounting density of electronic circuit components mounted on the substrate can be improved. In addition, the circuit size of the circuit-corrected board can be made significantly smaller than that of the multilayer circuit wiring board, so that the yield at the time of board production can be improved and the board production cost can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す回路修正前の多層回路
配線基板及び電子回路装置の要部断面図。
FIG. 1 is a cross-sectional view of an essential part of a multilayer circuit wiring board and an electronic circuit device before circuit modification showing an embodiment of the present invention.

【図2】同じく多層回路配線基板の平面図。FIG. 2 is a plan view of the same multilayer circuit wiring board.

【図3】同じく回路パターン修正後の要部断面図。FIG. 3 is a sectional view of an essential part after the circuit pattern is similarly corrected.

【図4】同じく回路パターン修正後の平面図。FIG. 4 is a plan view of the same circuit pattern after correction.

【図5】同じく多層回路配線基板上に回路修正基板を搭
載した他の実施例となる電子回路装置における回路パタ
ーン修正後の平面図。
FIG. 5 is a plan view after circuit pattern correction in an electronic circuit device according to another embodiment in which a circuit correction board is mounted on a multilayer circuit wiring board.

【図6】同じく回路パターン修正後の要部断面図。FIG. 6 is a sectional view of an essential part after the circuit pattern is similarly corrected.

【符号の説明】[Explanation of symbols]

1…多層回路配線基板、 2…LSI
チップ、3…はんだバンプ、 4
…端子接続用パッド、5…配線パターン、
6…補修パッド、7…接続パッド、
8…ボンディングワイヤ、9…LSI
搭載領域、 10…補修パターン、1
1…配線パターンのカット領域、12…配線パターン/
補修パッド接続領域、13…回路修正基板、
14…補修パターンのカット領域。
1 ... Multilayer circuit wiring board, 2 ... LSI
Chip, 3 ... Solder bump, 4
… Terminal connection pads, 5… wiring patterns,
6 ... Repair pad, 7 ... Connection pad,
8 ... Bonding wire, 9 ... LSI
Mounting area, 10 ... Repair pattern, 1
1 ... Wiring pattern cut area, 12 ... Wiring pattern /
Repair pad connection area, 13 ... Circuit correction board,
14 ... Cut area of repair pattern.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 今井 勉 神奈川県秦野市堀山下1番地 株式会社日 立製作所汎用コンピュータ事業部内 (72)発明者 安部 慎二 神奈川県秦野市堀山下1番地 株式会社日 立製作所汎用コンピュータ事業部内 (72)発明者 日高 博之 神奈川県秦野市堀山下1番地 株式会社日 立製作所汎用コンピュータ事業部内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tsutomu Imai 1 Horiyamashita, Hadano, Kanagawa Pref. General Computer Division, Nitrate Manufacturing Co., Ltd. (72) Shinji Abe 1 Horiyamashita, Hadano, Kanagawa Pref. (72) Inventor Hiroyuki Hidaka No. 1 Horiyamashita, Hadano City, Kanagawa Prefecture

Claims (13)

【特許請求の範囲】[Claims] 【請求項1】多層回路配線基板上に搭載した電子回路部
品の周辺領域に、回路補修中継路となる補修パッド
と、一端が内層配線に接続され他端が補修パッドに近
接対向し表面層上に延在する複数本の配線パターンとを
設けて配線パターンの回路修正領域を形成すると共に、
電子回路部品の搭載領域内に電子回路部品の端子を接
続し、かつ内層配線パターンに接続された端子接続用パ
ッドを形成して成る多層回路配線基板。
1. A repair pad, which serves as a circuit repair relay path, is provided in the peripheral area of an electronic circuit component mounted on a multilayer circuit wiring board, and one end is connected to an inner layer wiring and the other end is closely opposed to the repair pad and is on the surface layer. And a plurality of wiring patterns extending to form a circuit correction area of the wiring pattern,
A multilayer circuit wiring board formed by connecting terminals of an electronic circuit component in a mounting area of the electronic circuit component and forming a terminal connection pad connected to an inner layer wiring pattern.
【請求項2】上記多層回路配線基板には、隣接して複数
個の電子回路部品がマトリクス状に搭載される搭載領域
が形成され、この搭載領域間に設けられた上記回路修正
領域内の補修パッドに隣接して複数本の補修パターンを
配設して成る請求項1記載の多層回路配線基板。
2. The multi-layer circuit wiring board is provided with mounting areas adjacent to each other for mounting a plurality of electronic circuit components in a matrix, and repairs are made in the circuit correction areas provided between the mounting areas. The multilayer circuit wiring board according to claim 1, wherein a plurality of repair patterns are arranged adjacent to the pads.
【請求項3】上記補修パターンの両端に回路配線接続用
の接続パッドを設けて成る請求項2記載の多層回路配線
基板。
3. The multilayer circuit wiring board according to claim 2, wherein connection pads for connecting circuit wiring are provided at both ends of the repair pattern.
【請求項4】多層回路配線基板と、この上に搭載する電
子回路部品との間に、回路修正機能を有する回路修正基
板を設けると共に、回路修正基板の表面に請求項1乃至
3何れか記載の補修パッド、配線パターンを配設し、回
路修正基板上の補修パッドを基板内導体配線を介して裏
面側の前記多層回路配線基板の端子接続用パッドに導体
配線を介して接続して成る多層回路配線基板。
4. The circuit correction board having a circuit correction function is provided between the multilayer circuit wiring board and the electronic circuit component mounted thereon, and the surface of the circuit correction board is provided on any one of claims 1 to 3. A multilayer structure in which repair pads and wiring patterns are provided, and the repair pads on the circuit correction board are connected to the terminal connection pads of the multilayer circuit wiring board on the back side via conductor wiring via conductor wiring. Circuit wiring board.
【請求項5】電子回路部品を搭載し、回路修正した回路
修正基板を多層回路配線基板上に複数個搭載すると共
に、前記隣接する回路修正基板相互間の回路修正を前記
多層回路配線基板上の回路修正領域で修正して成る多層
回路配線基板。
5. An electronic circuit component is mounted and a plurality of circuit-corrected circuit-corrected boards are mounted on a multilayer circuit wiring board, and circuit correction between adjacent circuit-corrected boards is performed on the multilayer circuit-wired board. A multi-layer circuit wiring board that is modified in the circuit modification area.
【請求項6】請求項1乃至3何れか記載の多層回路配線
基板を用いた回路修正方法であって、配線パターン及
び補修パターンの予め定められた回路カット修正領域の
配線をそれぞれカットする工程と、前記配線パターン
と補修パターン間の相互を導体接続する工程と、補修
パッドと補修パターン上の接続パッド間の相互を導体接
続する工程と、補修パッドと補修パターンの相互を導
体接続する工程と、補修パターン上の接続パッド間の
相互を導体接続する工程とを有して成る多層回路配線基
板及び回路修正基板の修正方法。
6. A circuit repairing method using the multilayer circuit wiring board according to claim 1, further comprising a step of cutting wires in predetermined circuit cut repair areas of the wiring pattern and the repair pattern, respectively. A step of conducting a conductor connection between the wiring pattern and the repair pattern, a step of conducting a conductor connection between the repair pad and a connection pad on the repair pattern, and a step of conducting a conductor connection between the repair pad and the repair pattern, A method of repairing a multilayer circuit wiring board and a circuit repairing board, the method comprising: connecting conductors between connection pads on a repair pattern.
【請求項7】請求項4もしくは5記載の回路修正基板を
用いた回路修正方法であって、配線パターン及び補修
パターンの予め定められた回路カット修正領域の配線を
それぞれカットする工程と、前記配線パターンと補修
パターン間の相互を導体接続する工程と、補修パッド
と補修パターン上の接続パッド間の相互を導体接続する
工程と、補修パッドと補修パターンの相互を導体接続
する工程と、補修パターン上の接続パッド間の相互を
導体接続する工程とを有して成る回路修正基板の修正方
法。
7. A circuit repairing method using the circuit repairing substrate according to claim 4 or 5, wherein a step of cutting wires in predetermined circuit cut repair areas of the wiring pattern and the repair pattern, respectively, Conductive connection between the pattern and the repair pattern, conductive connection between the repair pad and the connection pad on the repair pattern, conductive connection between the repair pad and the repair pattern, and And a method of electrically connecting the connection pads between the conductors with each other.
【請求項8】請求項6の乃至記載の接続する工程と
して、ろう材を供給し溶融接続する工程として成る多層
回路配線基板の回路修正方法。
8. A circuit repairing method for a multilayer circuit wiring board, which comprises a step of supplying a brazing material and performing a melt connection as the connecting step according to claim 6.
【請求項9】請求項7の乃至記載の接続する工程と
して、ろう材を供給し溶融接続する工程として成る回路
修正基板の回路修正方法。
9. A circuit repairing method for a circuit repairing substrate, which comprises the step of supplying a brazing material and performing melt-bonding as the connecting step according to claim 7.
【請求項10】上記回路修正領域の配線パターン及び補
修パターンのカット方法として、レーザビーム照射、も
しくは機械的に切断する工程として成る請求項6記載の
多層回路配線基板の修正方法。
10. The method for repairing a multilayer circuit wiring board according to claim 6, wherein the method for cutting the wiring pattern and the repair pattern in the circuit repair area is a step of laser beam irradiation or mechanical cutting.
【請求項11】上記回路修正領域の配線パターン及び補
修パターンのカット方法として、レーザビーム照射、も
しくは機械的に切断する工程として成る請求項7記載の
回路修正基板の回路修正方法。
11. The circuit repairing method for a circuit repairing substrate according to claim 7, wherein the method for cutting the wiring pattern and the repair pattern in the circuit repairing area comprises a step of laser beam irradiation or mechanical cutting.
【請求項12】請求項1乃至3何れか記載の多層回路配
線基板上に電子回路部品を搭載し、前記基板上の搭載領
域に設けられた端子接続用パッドと電子回路部品の端子
とを電気的に接続して成る電子回路装置。
12. An electronic circuit component is mounted on the multilayer circuit wiring board according to claim 1, and the terminal connection pad and the terminal of the electronic circuit component provided in the mounting area on the substrate are electrically connected. Circuit devices that are connected together electrically.
【請求項13】多層回路配線基板上に請求項4もしくは
5記載の回路修正基板及び電子回路部品を搭載し、前記
多層回路配線基板上の搭載領域に設けられた端子接続用
パッドと回路修正基板上の端子接続用パッドと電子回路
部品の端子とを各々電気的に接続して成る電子回路装
置。
13. A circuit correction board and an electronic circuit component according to claim 4 or 5 are mounted on a multilayer circuit wiring board, and a terminal connecting pad and a circuit correction board provided in a mounting area on the multilayer circuit wiring board. An electronic circuit device in which the upper terminal connection pad and the terminals of the electronic circuit component are electrically connected to each other.
JP5002315A 1993-01-11 1993-01-11 Multilayer circuit wiring board having circuit correction function, its circuit correction method and electronic circuit device Pending JPH06209169A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5002315A JPH06209169A (en) 1993-01-11 1993-01-11 Multilayer circuit wiring board having circuit correction function, its circuit correction method and electronic circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5002315A JPH06209169A (en) 1993-01-11 1993-01-11 Multilayer circuit wiring board having circuit correction function, its circuit correction method and electronic circuit device

Publications (1)

Publication Number Publication Date
JPH06209169A true JPH06209169A (en) 1994-07-26

Family

ID=11525907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5002315A Pending JPH06209169A (en) 1993-01-11 1993-01-11 Multilayer circuit wiring board having circuit correction function, its circuit correction method and electronic circuit device

Country Status (1)

Country Link
JP (1) JPH06209169A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007335434A (en) * 2006-06-12 2007-12-27 Nec Corp Flexible wiring board, method for repairing disconnection thereof and circuit board
JP2011035094A (en) * 2009-07-31 2011-02-17 Dainippon Printing Co Ltd Method of repairing printed board pattern

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007335434A (en) * 2006-06-12 2007-12-27 Nec Corp Flexible wiring board, method for repairing disconnection thereof and circuit board
JP2011035094A (en) * 2009-07-31 2011-02-17 Dainippon Printing Co Ltd Method of repairing printed board pattern

Similar Documents

Publication Publication Date Title
US4817850A (en) Repairable flip-chip bumping
US20020089050A1 (en) Semiconductor device
US5923539A (en) Multilayer circuit substrate with circuit repairing function, and electronic circuit device
JP2004207566A (en) Semiconductor device, display apparatus, and manufacturing method thereof
JPH1032221A (en) Printed wiring board
JPH10135267A (en) Structure of mounting board and its manufacture
KR100764668B1 (en) Substrate for mounting flip chip and the manufacturing method thereof
JPH04137692A (en) Remodeling of printed board
JPH06209169A (en) Multilayer circuit wiring board having circuit correction function, its circuit correction method and electronic circuit device
JP3268615B2 (en) Manufacturing method of package parts
JP2002280491A (en) Electronic component and its manufacturing method
JP2837521B2 (en) Semiconductor integrated circuit device and wiring change method thereof
JP3152527B2 (en) Multilayer circuit wiring board having circuit correction function, circuit correction method and electronic circuit device
US6229219B1 (en) Flip chip package compatible with multiple die footprints and method of assembling the same
JP2539287B2 (en) Manufacturing method of circuit board with circuit component mounting terminals
JP2848346B2 (en) Electronic component mounting method
JP3270233B2 (en) Semiconductor device
KR100628519B1 (en) System on board and manufacturing method thereof
KR100370839B1 (en) Circuit Tape for Semiconductor Package
JPH0779080A (en) Multilayer circuit wiring board and circuit correcting method based thereon
JPS63187653A (en) Loading structure of semiconductor element
JPH0645763A (en) Printed wiring board
JPH07122834A (en) Connecting structure of printed wiring board
JPH11214852A (en) Multilayer circuit wiring board, production thereof and correction method therefor
JPH1022605A (en) Method for mounting hybrid electronic parts onto board