JP3172267B2 - Large-scale wiring board and manufacturing method thereof - Google Patents

Large-scale wiring board and manufacturing method thereof

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Publication number
JP3172267B2
JP3172267B2 JP18066192A JP18066192A JP3172267B2 JP 3172267 B2 JP3172267 B2 JP 3172267B2 JP 18066192 A JP18066192 A JP 18066192A JP 18066192 A JP18066192 A JP 18066192A JP 3172267 B2 JP3172267 B2 JP 3172267B2
Authority
JP
Japan
Prior art keywords
wiring
substrate
layer
board
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP18066192A
Other languages
Japanese (ja)
Other versions
JPH0629355A (en
Inventor
康則 成塚
英穂 山村
健二 武田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Priority to JP18066192A priority Critical patent/JP3172267B2/en
Publication of JPH0629355A publication Critical patent/JPH0629355A/en
Application granted granted Critical
Publication of JP3172267B2 publication Critical patent/JP3172267B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、例えば電子計算機や電
子交換器等のように高速で電気的信号を処理する必要の
ある電子機器のように大規模な回路を高密度に組み込む
必要のある電子機器に好適な大規模配線基板とその製造
方法及びこれを用いた電子機器に関するものである。BACKGROUND OF THE INVENTION The present invention requires a high-density integration of a large-scale circuit such as an electronic device which needs to process electric signals at a high speed, such as an electronic computer or an electronic exchange. The present invention relates to a large-scale wiring board suitable for an electronic device, a method for manufacturing the same, and an electronic device using the same.

【０００２】[0002]

【従来技術】近年、電子機器の性能は大規模集積回路
（ＬＳＩ）を限られた空間に多く組み込むための実装技
術に大きく左右されるようになって来た。既に、ＬＳＩ
の外部の回路及びＬＳＩとの接続部分は、従来最も用い
られてきたプリント基板における配線ピッチでは形成で
きないほど細かい配線パタ−ンが必要となってきてお
り、セラミック厚膜印刷技術によって形成された多層配
線基板上に更に細かい回路パタ−ン形成が可能な薄膜技
術によって接続部分を形成した基板や、同様の薄膜技術
によって接続部分を形成した高耐熱樹脂テ−プをＬＳＩ
と基板との間に入れるテ−プオ−トメ−テッドボンディ
ング（ＴＡＢ）と呼ばれる技術が適用され始めている。
一般に、薄膜技術によって作られた配線とＬＳＩとの接
続には、Ａｕ等の細いワイヤを用いるワイヤボンディン
グと呼ばれる接続法または半田を用いる接続法が用いら
れる。特に、半田を用いる接続法の中でもコントロ−ル
ド・コラプス・ボンディング（ＣＣＢ）法は、ＬＳＩチ
ップの表面全面から端子を引き出すことができるために
端子数が多いＶＬＳＩに好適なため、一部の実装基板に
用いられるようになってきた。2. Description of the Related Art In recent years, the performance of electronic devices has been greatly influenced by mounting techniques for incorporating large-scale integrated circuits (LSIs) into a limited space. Already LSI
The external circuit and the connection portion with the LSI require a fine wiring pattern that cannot be formed with the wiring pitch of a printed circuit board most conventionally used, and a multilayer formed by a ceramic thick film printing technique. A substrate formed with a connection portion by a thin film technology capable of forming a finer circuit pattern on a wiring substrate or a high heat resistant resin tape formed by a similar thin film technology to form a connection portion is formed on an LSI.
A technique called tape automated bonding (TAB) between the substrate and the substrate has begun to be applied.
In general, a connection method called wire bonding using a thin wire such as Au or a connection method using solder is used to connect a wiring formed by a thin film technique to an LSI. In particular, among the connection methods using solder, the control collapse bonding (CCB) method is suitable for a VLSI having a large number of terminals because terminals can be drawn out from the entire surface of the LSI chip, and therefore, some mounting methods are used. It has come to be used for substrates.

【０００３】しかしながら、上記のような接続法は接続
部分の必要面積が数十μｍ径は必要であるため、配線を
より高密度に接続することが次第に困難になりつつある
上に、接続のための特別な配線層構成を必要とするため
工程が増える欠点もある。これに対して、接着剤により
上下の電極を機械的に押しつけて電気的接続を行う技術
が実用化されつつある。この場合、基本的には２０μｍ
以下の配線ピッチにおける接続も可能であることが示さ
れている。この接続法の問題点は上下の電極間に接着剤
が残るため、接続部の電気抵抗が比較的高いことが挙げ
られる。また、接着剤による接続のため、実使用条件下
での接続信頼性が基本的には高くないことから、通信機
及び計算機のように高信頼性を求められる製品には適用
が困難であることも大きな問題として挙げられる。However, the above-mentioned connection method requires a connection area of several tens of μm in diameter, which makes it increasingly difficult to connect wiring at a higher density. There is also a drawback that the number of steps increases because the special wiring layer configuration is required. On the other hand, a technique of mechanically pressing the upper and lower electrodes with an adhesive to perform electrical connection has been put into practical use. In this case, basically 20 μm
It is shown that connection at the following wiring pitch is also possible. The problem with this connection method is that since the adhesive remains between the upper and lower electrodes, the electrical resistance of the connection portion is relatively high. In addition, the connection reliability under actual use conditions is basically not high due to the connection using an adhesive, so it is difficult to apply it to products that require high reliability such as communication equipment and computers. Is also a major problem.

【０００４】これらに対して、ＬＳＩチップと配線基板
との電気的接続をいわゆるボンディング技術を用いずに
接続するボンディングレスインタ−コネクション法も提
案され検討が進められている。典型的な例としてＩＣカ
ードに見られるように、熱可塑性樹脂へＬＳＩチップを
埋め込むことでＬＳＩ表面及び樹脂部表面を平坦化し、
これによりＬＳＩの接続パッドが基板表面に位置する基
板を形成し、接続パッド間の配線を容易に形成する技術
が報告されている。On the other hand, a bondingless interconnection method for connecting an electrical connection between an LSI chip and a wiring board without using a so-called bonding technique has been proposed and studied. As seen in IC cards as a typical example, embedding an LSI chip in a thermoplastic resin flattens the LSI surface and resin surface,
Thus, a technique has been reported in which a substrate is formed in which connection pads of an LSI are located on the surface of the substrate, and wiring between the connection pads is easily formed.

【０００５】また、図７に示したように支持板２上にＬ
ＳＩチップ１を所定間隔で配列し、隣接するチップ間に
樹脂２３を埋込みチップを支持板２に固定すると共に樹
脂表面を平坦化する。この時、チップ１の電極パッド３
上に樹脂が残らないように除去してからその上全面に絶
縁層４を形成し、所定のスルーホールを設ける。次いで
配線金属を全面に形成してから選択エッチングによりパ
ターニングして配線５を形成するものである。この絶縁
層４と配線５との形成工程を繰返し、この例では２層の
配線５を形成している。[0005] Further, as shown in FIG.
The SI chips 1 are arranged at predetermined intervals, a resin 23 is embedded between adjacent chips, the chips are fixed to the support plate 2, and the resin surface is flattened. At this time, the electrode pad 3 of the chip 1
After removing the resin so as not to remain thereon, the insulating layer 4 is formed over the entire surface thereof, and predetermined through holes are provided. Next, a wiring metal is formed on the entire surface and then patterned by selective etching to form the wiring 5. The process of forming the insulating layer 4 and the wiring 5 is repeated, and in this example, two layers of the wiring 5 are formed.

【０００６】なお、この種の技術に関連するものとして
は、例えばアイ・イ−・イ−・イ−・トランザクション
・シイエイチエムティー第１０巻第３号（１９８７年）
３１０〜３１３ページ〔ＩＥＥＥ Ｔransactions on Ｃ
onponents，Ｈybrids，andＭanufacturing Ｔecnolog
y，Ｖol．ＣＨＭＴ−１０，Ｎｏ．３ Ｓept．１９８
７，ｐｐ．３１０〜３１３〕及び特開昭６２−８１７４
５号公報が挙げられる。[0006] It should be noted that related to this kind of technology are, for example, I-I-I-I-T Transaction Shim-TMT, Vol. 10, No. 3 (1987).
Pages 310 to 313 [IEEE Transactions on C
onponents, Hybrids, and Manufacturing Tecnolog
y, Vol. CHMT-10, No. 3 Sep. 198
7, pp. 310-313] and JP-A-62-8174.
No. 5 publication.

【０００７】[0007]

【発明が解決しようとする課題】高密度配線基板に関し
て本来の目的を考えてみると、電気的素子を高密度に配
設し、これを最短の配線で接続することであり、これの
１つの方向がＬＳＩそのものである。従って、複数のＬ
ＳＩを配線基板上に接続する場合はＬＳＩチップそのも
のを高密度に配設する必要がある。しかしながら、上記
技術は何れも１つのＬＳＩ上の接続パッドの大きさ及び
パッド間の間隔が小さい場合の配線基板の接続法であ
り、複数のＬＳＩチップを高密度に配線基板と接続する
ことまでは考慮されていなかった。従って、何れの例に
おいてもＬＳＩチップ間の間隔を小さくする上で何らか
の困難を伴っていた。Considering the original purpose of a high-density wiring board, it is necessary to arrange electrical elements at high density and connect them with the shortest wiring. The direction is the LSI itself. Therefore, a plurality of L
When connecting an SI on a wiring board, it is necessary to arrange the LSI chips themselves at high density. However, each of the above techniques is a method of connecting a wiring board when the size of a connection pad on one LSI and the interval between the pads are small, and until a plurality of LSI chips are connected to the wiring board with high density. Was not taken into account. Therefore, in each of the examples, there was some difficulty in reducing the interval between the LSI chips.

【０００８】したがって本発明の目的は、上記従来の問
題点を解消することにあり、その第１の目的は複数のＬ
ＳＩチップを支持基板に隙間なく高密度に搭載固定する
と共にその表面に多層配線構造体を配設して成る大規模
配線基板を提供することにあり、第２の目的はその製造
方法を提供することにある。Accordingly, an object of the present invention is to solve the above-mentioned conventional problems, and a first object of the present invention is to solve a plurality of L
It is an object of the present invention to provide a large-scale wiring board in which an SI chip is mounted and fixed at high density on a support substrate without gaps, and a multilayer wiring structure is provided on the surface thereof. A second object is to provide a manufacturing method thereof. It is in.

【０００９】[0009]

【課題を解決するための手段】上記課題に対して、最も
ＬＳＩチップを高密度に配設するために支持基板上に厚
さの揃ったＬＳＩチップを隙間なく隣接させ、ＬＳＩチ
ップの集団そのものがあたかも１枚の基板のごとくなる
よう固定することである。そしてこの基板上へのＬＳＩ
チップの固定に際しては、チップの形成された電極パッ
ドを上向きとして、その背面を支持基板に固定し、さら
に基板の電極パッド側には絶縁層に設けたスルーホール
を介して隣接するチップ間もしくは同一チップ内の電極
パッドに接続する配線を形成しておく。本発明の大規模
配線基板は、このＬＳＩチップを固定した基板上に、さ
らに別途準備した配線基板を多層に積層した構成とした
ものである。In order to solve the above-mentioned problems, in order to arrange the LSI chips at the highest density, LSI chips having the same thickness are arranged adjacent to each other on the support substrate without any gap, and the group of LSI chips themselves is formed. This is to fix it as if it were like a single substrate. And LSI on this substrate
When fixing the chip, the electrode pad on which the chip is formed faces upward, the back surface is fixed to the support substrate, and the electrode pad side of the substrate is between adjacent chips or the same via a through hole provided in an insulating layer. Wirings connected to the electrode pads in the chip are formed in advance. The large-scale wiring board of the present invention has a configuration in which a separately prepared wiring board is stacked in multiple layers on a board to which this LSI chip is fixed.

【００１０】すなわち、ＬＳＩチップの集団を固定した
基板上に配線基板を多層に積層するにあたっては、ＬＳ
Ｉチップ内配線または隣接するＬＳＩチップ間の配線等
の多層配線の一部の配線を形成したスルーホールを有す
る配線基板（例えば絶縁フィルム上に形成したもの）を
予め個別に製作しておき、この配線基板を上記ＬＳＩチ
ップの集団を固定した基板上に接着剤を用いて積層固定
し、１層積層する毎にめっきによりスルーホールを介し
てＬＳＩチップ側の下層配線との間を電気的に接続す
る。この配線基板の積層回数を所望の回数繰返すことに
より、目的とする大規模配線基板を実現することができ
る。That is, in laminating a wiring board in multiple layers on a board to which a group of LSI chips is fixed, the LS
A wiring board (for example, formed on an insulating film) having a through hole in which a part of a multi-layer wiring such as a wiring in an I chip or a wiring between adjacent LSI chips is formed is individually manufactured in advance. The wiring substrate is laminated and fixed on the substrate on which the above-mentioned LSI chip group is fixed by using an adhesive, and every time one layer is laminated, the wiring is electrically connected to the lower layer wiring on the LSI chip side through a through hole by plating. I do. By repeating the number of times of laminating the wiring boards a desired number of times, a target large-scale wiring board can be realized.

【００１１】以下に本発明の具体的な目的達成手段につ
いて説明する。先ず、上記第１の目的は、電極パッド
の形成された面を上向きにして複数のＬＳＩチップを支
持基板上に隙間無く配列すると共に、その背面を支持基
板に固着したＬＳＩチップ集団の表面に、絶縁層に配設
されたスルーホールを介して前記電極パッドに接続され
た配線層を形成して成る第１の基板と、予めスルーホ
ールの形成された絶縁シートに配線パターンが形成され
た配線基板と、前記第１の基板に前記配線基板を接着
剤で固着、積層し、前記配線基板のスルーホールを介し
て前記第１の基板の配線層と前記配線基板上の配線パタ
ーンとを電気的に接続するめっき金属層とを有して成る
大規模配線基板により、達成される。Hereinafter, specific means for achieving the object of the present invention will be described. First, the first object is to arrange a plurality of LSI chips on a support substrate without gaps with the surface on which the electrode pads are formed facing upward, and to attach the back surface to the surface of an LSI chip group fixed to the support substrate, A first substrate formed with a wiring layer connected to the electrode pad via a through hole provided in an insulating layer, and a wiring substrate formed with a wiring pattern on an insulating sheet in which a through hole is formed in advance; And bonding and laminating the wiring substrate to the first substrate with an adhesive, and electrically connecting a wiring layer of the first substrate and a wiring pattern on the wiring substrate via a through hole of the wiring substrate. This is achieved by a large-scale wiring board having a plating metal layer to be connected.

【００１２】上記第１の基板上に積層する配線基板とし
ては、単層（１枚）に限らず回路規模に応じて複数枚固
着、積層して多層配線構造体とする。また、この大規模
配線基板を外部回路に接続するために、最表面の配線パ
ターン上に、ピン付きコネクタを導体で接続してコネク
タ付き配線基板とすることが実用的で好ましい。コネク
タはセラミックス等の厚膜配線基板で構成し、一方の面
に接続ピンを植設し、他方の面に配線パターンに接続す
る電極を形成しておく。これをはんだ接続で配線基板に
接続、固定してコネクタ付きの大規模配線基板とする。The wiring substrate to be laminated on the first substrate is not limited to a single layer (one), but a plurality of substrates are fixed and laminated according to the circuit scale to form a multilayer wiring structure. In order to connect this large-scale wiring board to an external circuit, it is practical and preferable to connect a connector with pins with a conductor on the outermost wiring pattern to obtain a wiring board with connectors. The connector is composed of a thick film wiring board made of ceramics or the like, connection pins are planted on one surface, and electrodes connected to the wiring pattern are formed on the other surface. This is connected to a wiring board by soldering and fixed to form a large-scale wiring board with a connector.

【００１３】また、支持基板の背面に、例えば水冷によ
る冷却機構筐体を配設することが望ましく、ＬＳＩチッ
プの放熱を良好にするため支持基板は、熱伝導良好でＬ
ＳＩチップの熱膨張係数に近似した無機絶縁基板で構成
することが望ましい。支持基板の背面に凹凸を設けてこ
れを冷却機構筐体の一部として兼用し、支持基板を直接
冷却する構成とすることができる。It is desirable to dispose a cooling mechanism housing by, for example, water cooling on the back surface of the support substrate.
It is desirable that the chip be formed of an inorganic insulating substrate having a coefficient of thermal expansion approximate to that of the SI chip. Irregularities may be provided on the back surface of the support substrate, which may also be used as a part of the cooling mechanism housing to directly cool the support substrate.

【００１４】上記第１の基板の絶縁層は、表面の平坦化
が容易なように例えばポリイミドの如き有機絶縁層を塗
布膜で構成することが望ましい。また、配線基板の絶縁
シートとしては、例えばポリイミドの如き有機絶縁フィ
ルムで構成すると共に、スルーホールの形状は、めっき
による電気的接続を容易とするため、ロート状にテーパ
ーを設けることが望ましい。The insulating layer of the first substrate is desirably formed of a coating film of an organic insulating layer such as polyimide so that the surface can be easily flattened. In addition, it is desirable that the insulating sheet of the wiring board be formed of an organic insulating film such as polyimide, and that the shape of the through hole be provided with a funnel-shaped taper in order to facilitate electrical connection by plating.

【００１５】また、上記第２の目的は、電極パッドの
形成された面を上向きにして複数のＬＳＩチップを支持
基板上に隙間無く配列すると共に、その背面を支持基板
に固着するに際し、各チップ上面を同一平面となるよう
配設して、ＬＳＩチップ集団を固着する工程と、前記
ＬＳＩチップ集団の表面に、絶縁層を形成した後、前記
電極パッド上の位置に対応する絶縁層にスルーホールを
形成し、このスルーホールを介して同一チップ内もしく
は隣接するチップ間の電極パッド間を電気的に接続する
配線層を形成して第１の基板を準備する工程と、絶縁
シートを準備し、前記第１の基板上の配線層に対応させ
た位置にスルーホールを形成すると共に、このスルーホ
ールを配線回路の一つとして含む配線パターンを絶縁シ
ート上に形成して配線基板を形成する工程と、前記第
１の基板に前記配線基板を接着剤で固着、積層する工程
と、前記積層された配線基板にめっき処理を施し、ス
ルーホールを介して前記第１の基板の配線層と前記配線
基板上の配線パターンとを電気的に接続する工程とを有
して成る大規模配線基板の製造方法により、達成され
る。A second object of the present invention is to arrange a plurality of LSI chips on a support substrate without gaps with the surface on which the electrode pads are formed facing upward, and to fix the back surface of each chip to the support substrate. Arranging the upper surface so as to be flush with each other and fixing an LSI chip group; forming an insulating layer on the surface of the LSI chip group; and forming a through hole in the insulating layer corresponding to a position on the electrode pad. Forming a wiring layer for electrically connecting electrode pads in the same chip or between adjacent chips through the through holes to prepare a first substrate; and preparing an insulating sheet; A through hole is formed at a position corresponding to a wiring layer on the first substrate, and a wiring pattern including the through hole as one of the wiring circuits is formed on an insulating sheet to form a wiring board. Forming, bonding the wiring substrate to the first substrate with an adhesive, and laminating the wiring substrate, performing plating on the laminated wiring substrate, and wiring the first substrate through a through hole. This is achieved by a method for manufacturing a large-scale wiring board, comprising a step of electrically connecting a layer and a wiring pattern on the wiring board.

【００１６】大規模配線基板の回路規模に応じて上記
の工程からの工程迄を複数回繰返し、第１の基板上に
複数の配線基板を積層して多層回路基板を形成する工程
とすることが望ましい。さらに好ましい工程として、上
記の積層工程の後に、スルーホール底部の配線層上に
残留した不要な接着剤を除去する工程を付加することで
あり、これにより電気的接続の信頼性を確実なものとす
ることができる。According to a circuit scale of a large-scale wiring board, the above-described steps from the above steps are repeated a plurality of times to form a multilayer circuit board by laminating a plurality of wiring boards on the first board. desirable. As a more preferable step, after the above-mentioned laminating step, a step of removing unnecessary adhesive remaining on the wiring layer at the bottom of the through hole is added, thereby ensuring the reliability of the electrical connection. can do.

【００１７】また、上記の第１の基板を準備する工程
における配線層の好ましい形成例としては、成膜工程に
より順次Ｃｒ／Ｃｕ／Ｃｒを成膜して３層膜とするか、
もしくはＴｉ／Ｃｕ／Ｃｒの３層膜とし、上記の積層
工程の後に、スルーホール底部に表れた配線層の最表層
のＣｒをエッチング処理により除去して下地のＣｕ層を
露出させる工程を付加し、のめっき処理をＣｕもしく
はＮｉめっき処理工程とすることが好ましい。第１層目
のＣｒはＣｕの下地層として形成するものであり、第３
層目のＣｒはＣｕの酸化防止膜として形成する。Further, as a preferable example of forming the wiring layer in the step of preparing the first substrate, Cr / Cu / Cr is sequentially formed into a three-layer film by a film forming step.
Alternatively, after the above-mentioned laminating step, a step of exposing the outermost layer of Cr of the wiring layer appearing at the bottom of the through-hole by etching to expose the underlying Cu layer is added after forming the three-layered film of Ti / Cu / Cr. Is preferably a Cu or Ni plating step. The first layer of Cr is formed as an underlayer of Cu.
The Cr layer is formed as an antioxidant film for Cu.

【００１８】また、好ましい例として、上記のように
の絶縁層の形成を、ポリイミド前駆体を塗布・キュアし
て表面の平坦化された絶縁層として形成すると共に、
の絶縁シートをポリイミドフィルムで形成することが望
ましい。As a preferred example, the formation of the insulating layer as described above is performed by applying and curing a polyimide precursor to form an insulating layer having a flat surface.
Is desirably formed of a polyimide film.

【００１９】[0019]

【作用】厚さの揃ったＬＳＩチップを隙間無く隣接させ
て支持基板に固定することでＬＳＩチップの集団の表面
において、チップ間に生じる段差を２０μｍ以下とする
ことが可能となる。この段差は塗布・キュア工程により
形成する有機絶縁層、または無機絶縁膜をＬＳＩチップ
の集団上に形成することによって低減でき、完全に平坦
化できなくともチップ間に跨る配線を形成した場合にも
断線等の不良を発生することがない程度の大きさの段差
にすることができる。An LSI chip having a uniform thickness is fixed to a supporting substrate so as to be adjacent to the LSI chip without any gap, so that a step generated between the chips on the surface of the group of LSI chips can be reduced to 20 μm or less. This step can be reduced by forming an organic insulating layer or an inorganic insulating film formed by a coating / curing step on a group of LSI chips, and even if wiring over the chips is formed even if it cannot be completely planarized. The step can be made large enough not to cause a defect such as disconnection.

【００２０】また、チップ集団を固定するために用いる
支持基板として熱伝導率の高い材質を用いると、多層配
線基板完成後にはそのままＬＳＩチップから発生する熱
を放散するための冷却板または冷却機構の一部として用
いることができる。支持基板は、単体金属、合金、セラ
ミックス等で構成されるがＬＳＩチップの熱膨張率に近
いものが望ましく、例えばＺｒ、Ｗ等の単体金属もしく
はインバー合金として知られる熱膨張係数の小さな合金
等が用いられる。Further, when a material having high thermal conductivity is used as a support substrate for fixing a chip group, a cooling plate or a cooling mechanism for dissipating heat generated from an LSI chip as it is after completion of a multilayer wiring board. Can be used as part. The support substrate is composed of a single metal, an alloy, ceramics, or the like, and desirably has a coefficient of thermal expansion close to that of an LSI chip. Used.

【００２１】更に、ＬＳＩチップ集団上の電極パッドに
予め絶縁層を介して接続された配線を有する基板上に、
スルーホールの設けられた配線基板を多層に積層するに
あたっては、別途予めＬＳＩチップ内配線または隣接す
るＬＳＩチップ間の配線等多層配線の一部の配線を形成
済みのスルーホールを有するフィルム基板を製作してお
き、上記基板上の配線と配線基板のスルーホールとの位
置合わせを行ない、両基板を接着剤で張り合わせて固定
し、配線基板を１層積層する毎にめっきによりスルーホ
ール内を埋めて下層配線との間を電気的に接続する。こ
の工程を積層数に見合って複数回繰返す。これにより、
積層する個々の配線基板の配線不良を予め検査してお
き、良好な配線層のみを選択し積層することが可能とな
り、配線基板の製造歩留まりの低下を防ぐことができ
る。また、めっきにより電気的接続を形成することで、
比較的低温で基板上に積層することができるため、配線
層を多層に積層する場合の熱応力による種々の問題発生
を防ぐことができる。Further, on a substrate having wires previously connected to electrode pads on a group of LSI chips via an insulating layer,
When laminating a wiring board provided with through holes in multiple layers, a film substrate having through holes in which a part of multilayer wiring such as wiring in an LSI chip or wiring between adjacent LSI chips is formed in advance is separately manufactured. In advance, align the wiring on the substrate with the through hole of the wiring substrate, fix both substrates together with an adhesive, and fill the through hole by plating every time one layer of the wiring substrate is laminated. It is electrically connected to the lower wiring. This process is repeated a plurality of times according to the number of layers. This allows
Wiring defects of individual wiring boards to be stacked can be inspected in advance, and only good wiring layers can be selected and stacked, thereby preventing a reduction in the manufacturing yield of the wiring boards. Also, by forming an electrical connection by plating,
Since the layers can be stacked on the substrate at a relatively low temperature, it is possible to prevent various problems caused by thermal stress when the wiring layers are stacked in multiple layers.

【００２２】[0022]

【実施例】以下、本発明の一実施例を図面にしたがって
説明する。 〈実施例１〉図１、図２は、本発明の大規模配線基板を
製造する基本的な製造方法の一例を示す工程図である。
先ず、図１（ａ）に示すように、熱膨張率がＬＳＩチッ
プ１の値に近いＺｒ、Ｗ等の単体金属またはインバ−合
金として知られる熱膨張係数の小さな合金等を支持板２
としてこの片側の面上に、ＬＳＩチップ１の電極パッド
３のある面側を上方に向けて多数個隙間無く並べ、接着
剤またははんだのような金属の接合材を用いてその背面
側を支持板２に固着する。固着に際しては個々のＬＳＩ
チップ１の表面が極力平坦になるように平滑な板をＬＳ
Ｉチップ１の表面に押しつける等の手段を講ずると良
い。また、ＬＳＩチップ相互間の隙間を極力無くすこと
を目的に、ＬＳＩチップの表面側をこの平滑な板に予め
仮留めした後、ＬＳＩチップ裏面を支持板に押しつけ固
着してもよい。An embodiment of the present invention will be described below with reference to the drawings. <Embodiment 1> FIGS. 1 and 2 are process diagrams showing an example of a basic manufacturing method for manufacturing a large-scale wiring board according to the present invention.
First, as shown in FIG. 1A, a support plate 2 is made of a single metal such as Zr or W having a coefficient of thermal expansion close to that of the LSI chip 1 or an alloy having a small coefficient of thermal expansion known as an invar alloy.
On the one surface, the surface with the electrode pads 3 of the LSI chip 1 is arranged upward without gaps, and the back surface thereof is supported by a metal bonding material such as adhesive or solder. 2 When fixing, individual LSI
LS a smooth plate so that the surface of chip 1 is as flat as possible
It is preferable to take measures such as pressing against the surface of the I chip 1. Further, in order to minimize the gap between the LSI chips, the front side of the LSI chip may be temporarily fixed to this smooth plate in advance, and then the back surface of the LSI chip may be pressed and fixed to the support plate.

【００２３】次に図１（ｂ）に示すように、ＬＳＩチッ
プ１の表面全面に絶縁層４としてポリイミド前駆体を塗
布・キュアし表面の平坦化を行う。ＬＳＩチップ相互間
の段差が２０μｍ以下であれば、塗布・キュア工程を複
数回繰り返すことで配線形成に支障が無い程度にまで段
差を軽減できる。形成したポリイミド絶縁層４の所定の
部分にフォトエッチング技術により電極パッド３を取り
出すためのスル−ホ−ル４ａを形成する。Next, as shown in FIG. 1B, a polyimide precursor is applied and cured as an insulating layer 4 on the entire surface of the LSI chip 1 to planarize the surface. If the step between the LSI chips is 20 μm or less, the step can be reduced to such an extent that wiring formation is not hindered by repeating the coating / curing process a plurality of times. A through hole 4a for taking out the electrode pad 3 is formed on a predetermined portion of the formed polyimide insulating layer 4 by a photo etching technique.

【００２４】図１（ｃ）に示すように、この絶縁層４上
にスパッタリングまたは蒸着のような成膜手法を用いて
Ｃｒ／Ｃｕ／ＣｒまたはＴｉ／Ｃｕ／Ｃｒの順序で３層
膜から成る配線層５を連続的に形成する。この後、配線
層５を予め予定された所定のマスクパターンを用い、フ
ォトエッチング技術により各層を順次加工し、配線パタ
−ン５を形成する。この工程により、ＬＳＩチップ１の
表面の接続パッド３と絶縁層４表面の配線５との電気的
接続がスルーホール４ａを介して形成される。ここで形
成される絶縁層４としてのポリイミド層は、熱膨張率が
ＬＳＩチップの値と同等であることが配線基板の信頼性
および製造上の点から望ましい。このようにして形成し
た基板を第１の基板と称し、符号３０で示す。As shown in FIG. 1C, a three-layer film is formed on the insulating layer 4 in the order of Cr / Cu / Cr or Ti / Cu / Cr using a film forming technique such as sputtering or vapor deposition. The wiring layer 5 is formed continuously. Thereafter, the wiring layer 5 is sequentially processed by a photo-etching technique using a predetermined mask pattern that is predetermined in advance to form a wiring pattern 5. By this step, an electrical connection between the connection pad 3 on the surface of the LSI chip 1 and the wiring 5 on the surface of the insulating layer 4 is formed through the through hole 4a. It is desirable that the polyimide layer as the insulating layer 4 formed here has the same coefficient of thermal expansion as the value of the LSI chip from the viewpoint of the reliability of the wiring board and the manufacturing. The substrate thus formed is referred to as a first substrate, and is denoted by reference numeral 30.

【００２５】なお、ＬＳＩチップ１が極めて高密度とな
り、それに伴い電極パッド３が微小となると、絶縁層４
のスルーホール４ａも微小となり、スパッタリングや蒸
着による成膜工程だけでは電極パッド３との導通が不完
全となる場合が生じる。したがって、このような場合に
は接続の信頼性を高めるために配線層５の成膜後にめっ
き工程を付加して導通を確実にすることが望ましい。When the density of the LSI chip 1 becomes extremely high and the electrode pads 3 become minute, the insulating layer 4
Of the through hole 4a becomes very small, and the conduction with the electrode pad 3 may be incomplete only by the film forming process by sputtering or vapor deposition. Therefore, in such a case, it is desirable to add a plating step after the film formation of the wiring layer 5 to secure conduction, in order to enhance the reliability of the connection.

【００２６】次に、図２（ａ）〜（ｃ）に示すように、
第１の基板３０とは別に、第２の基板と成る配線基板４
０を形成する。先ず、同図（ａ）に示すように、絶縁フ
ィルム７としてポリイミドフィルムを準備し、この所定
の位置にレ−ザ−アブレ−ション技術またはフォトエッ
チング技術によりスル−ホ−ル７ａを形成する。ここで
用いるポリイミドフィルムの膨張率もＬＳＩチップ１と
同等であることが望ましい。Next, as shown in FIGS. 2 (a) to 2 (c),
In addition to the first substrate 30, the wiring substrate 4 serving as a second substrate
0 is formed. First, as shown in FIG. 1A, a polyimide film is prepared as an insulating film 7, and a through hole 7a is formed at a predetermined position by a laser ablation technique or a photo etching technique. It is desirable that the expansion coefficient of the polyimide film used here is also equal to that of the LSI chip 1.

【００２７】次に同図（ｂ）に示すように、このフィル
ム７上に配線金属層８をスパッタリングもしくは蒸着に
より形成する。配線金属層８としてはＣｒ／Ｃｕ／Ｃｒ
またはＴｉ／Ｃｕ／Ｃｒからなる３層の配線層を順次連
続的に形成する。次いで同図（ｃ）に示すように、配線
金属層８をフォトエッチング技術を用いてパターニング
加工し、スル−ホ−ル７ａを有する単層の配線基板４０
を形成する。Next, as shown in FIG. 2B, a wiring metal layer 8 is formed on the film 7 by sputtering or vapor deposition. Cr / Cu / Cr as the wiring metal layer 8
Alternatively, three wiring layers made of Ti / Cu / Cr are sequentially and sequentially formed. Next, as shown in FIG. 3C, the wiring metal layer 8 is patterned by using a photo-etching technique to form a single-layer wiring substrate 40 having a through hole 7a.
To form

【００２８】次に同図（ｄ）に示すように、前工程
（ｃ）で形成した配線基板４０を、図１（ｃ）で形成し
た第１の基板３０の上に搭載し、接着剤６を用いて両者
を接合、固定する。この接合に際しては、配線基板４０
の裏面に接着剤６を塗布した後、上記第１の基板３０上
の所定配線層５の位置にスル−ホ−ル７ａが重なるよう
に位置決めし、配線基板４０のポリイミドフィルムと基
板３０とを接着する。接着剤６としては室温〜２００℃
以下の温度で固まり、反応時に水分及びガスを発生しな
いものが望ましい。また、接着にあたっては基板３０と
ポリイミドフィルム４０間の余剰の接着剤が少なくなる
ように、接着剤が固化する前にロ−ル等を用いて余分な
接着剤６を追い出すようにした方が電気的接続を形成す
る工程で良好な結果が得られる。Next, as shown in FIG. 3D, the wiring board 40 formed in the previous step (c) is mounted on the first substrate 30 formed in FIG. The two are joined and fixed using. At the time of this joining, the wiring board 40
After the adhesive 6 is applied to the back surface of the first substrate 30, the through-hole 7a is positioned so as to overlap the predetermined wiring layer 5 on the first substrate 30, and the polyimide film of the wiring substrate 40 and the substrate 30 are bonded together. Glue. Room temperature to 200 ° C. as the adhesive 6
Desirable is one that solidifies at the following temperature and does not generate moisture and gas during the reaction. When bonding, the excess adhesive 6 is expelled using a roll or the like before the adhesive is solidified, so that the excess adhesive between the substrate 30 and the polyimide film 40 is reduced. Good results can be obtained in the step of forming the electrical connection.

【００２９】接着が終了したし点でスル−ホ−ル７ａの
底部に残る不要な接着剤６を溶剤またはＯ2アッシング
処理等により除去し、次いで次工程（ｅ）のめっき処理
に備えてスル−ホ−ル７ａの底部に露出した配線層５の
最表面のＣｒ層をエッチングにより除去し、下地のＣｕ
層表面を露出させる。なお、このＣｒ層の除去は、図１
（ｃ）工程の最後に行なうこともできる。すなわち、予
め配線基板４０のスルーホール７ａが当接する基板３０
上の配線層５の最上部のＣｒ層を所定のマスクパターン
を用いてフォトエッチングにて除去し、下地のＣｕ層を
露出させる。Unnecessary adhesive 6 remaining at the bottom of the through-hole 7a at the point where the bonding is completed is removed by a solvent or O 2 ashing treatment, and then the through-hole is prepared for the plating treatment of the next step (e). The uppermost Cr layer of the wiring layer 5 exposed at the bottom of the hole 7a is removed by etching, and the underlying Cu
The layer surface is exposed. The removal of the Cr layer is performed as shown in FIG.
(C) It can be performed at the end of the step. That is, the substrate 30 with which the through-hole 7a of the wiring substrate 40 contacts in advance.
The uppermost Cr layer of the upper wiring layer 5 is removed by photoetching using a predetermined mask pattern to expose the underlying Cu layer.

【００３０】最後に同図（ｅ）に示すように、めっき処
理を行ないＮｉ，Ｃｕ等の金属膜９をスル−ホ−ル７ａ
の底部及び側面に成長させる。このめっき層９によって
第１の基板３０の配線５と配線基板４０上に形成した配
線８間の電気的導通が形成される。このようにして、本
発明の目的とする大規模配線基板５０を製造することが
できる。Finally, as shown in FIG. 3E, plating is performed to form a metal film 9 of Ni, Cu or the like on the through-hole 7a.
Grow on the bottom and sides. By this plating layer 9, electrical continuity between the wiring 5 of the first substrate 30 and the wiring 8 formed on the wiring substrate 40 is formed. In this manner, the large-scale wiring board 50 aimed at by the present invention can be manufactured.

【００３１】なお、この実施例では基本的な製造例を示
しているため、図２（ｄ）では、基板３０上に配線基板
４０を１層積層しているが、実際には複数層繰返して積
層して多層構造とし、大規模な配線構造体を形成する。Although this embodiment shows a basic example of manufacturing, in FIG. 2D, one layer of the wiring board 40 is laminated on the substrate 30, but actually, a plurality of layers are repeated. A large-scale wiring structure is formed by stacking layers.

【００３２】〈実施例２〉図３は、上記実施例１の工程
により製造した大規模多層配線基板５０（ただし、配線
基板４０を繰返し多層構造としたもの）の最上部の配線
層９ａと外部回路の配線とをコネクタ接続するための構
成例を示した要部断面図である。６０はコネクタ、１５
はコネクタ接続用のソケットで、コネクタ６０のピン１
４がソケット１５の挿入口１６に挿入されて大規模多層
配線基板５０の回路は、図示されていない外部回路に接
続される。<Embodiment 2> FIG. 3 shows the uppermost wiring layer 9a of the large-scale multi-layered wiring board 50 (in which the wiring board 40 has a repetitive multilayer structure) manufactured by the process of the above-described first embodiment and the external wiring layer 9a. FIG. 2 is a cross-sectional view of a main part showing a configuration example for connecting a circuit wiring with a connector. 60 is a connector, 15
Is a socket for connecting a connector.
4 is inserted into the insertion opening 16 of the socket 15, and the circuit of the large-scale multilayer wiring board 50 is connected to an external circuit (not shown).

【００３３】コネクタ６０は、厚膜配線基板（例えばセ
ラミックス多層基板）から成り、図示のごとく絶縁基板
６１の所定位置に設けられた貫通スル−ホ−ル６２に導
体１１を埋め込んで焼成し、裏面にコネクタ接続のため
のピン１４がろう材１３によりパッド１２に固定されて
いる。コネクタ６０の表面は、ＣＣＢ接続技術を用いて
大規模多層配線基板５０の最上部の配線層９ａとはんだ
１０により接続する。これにより、配線密度を大きく低
下させること無く外部回路と電気的接続が可能となる。
このコネクタ６０を構成する厚膜配線基板の熱膨張率も
ＬＳＩチップと同等であることが望ましい。The connector 60 is made of a thick-film wiring board (for example, a ceramic multilayer board). As shown in the figure, the conductor 11 is embedded in a through-hole 62 provided at a predetermined position of an insulating board 61 and fired. A pin 14 for connecting a connector is fixed to the pad 12 by a brazing material 13. The surface of the connector 60 is connected to the uppermost wiring layer 9a of the large-scale multilayer wiring board 50 by the solder 10 using the CCB connection technique. As a result, electrical connection with an external circuit is possible without greatly reducing the wiring density.
It is desirable that the coefficient of thermal expansion of the thick film wiring board constituting the connector 60 is also equal to that of the LSI chip.

【００３４】〈実施例３〉図４は、実施例１及び２で形
成した大規模多層配線基板５０の支持板２の背面に、冷
却構造筐体１８を熱伝導性良好な接着剤２１、もしくは
ろう材で接続、配設してＬＳＩチップ集団から発生した
熱を効率良く外部に逃がすことができる構成とした大規
模配線基板の要部概略断面図を示したものである。<Embodiment 3> FIG. 4 shows a case where the cooling structure housing 18 is bonded to the adhesive 21 having good thermal conductivity on the back surface of the support plate 2 of the large-scale multilayer wiring board 50 formed in Embodiments 1 and 2. FIG. 2 is a schematic cross-sectional view of a main part of a large-scale wiring board configured to connect and dispose with a brazing material so that heat generated from a group of LSI chips can be efficiently released to the outside.

【００３５】また、図５も同じく大規模多層配線基板５
０の支持板２の背面に、冷却構造筐体１８を配設した変
形例を示した要部概略断面図である。この例では支持板
２の背面形状を凹凸の形状に加工し、これを冷却構造筐
体１８の一部として兼用するもので、支持板２の突出し
た外周部２ａをシール材２２を介して残りの冷却構造筐
体１８に接続し、支持板２を直接冷却できる構造とした
ものであり、図４の構成よりも冷却効果をより向上させ
ることができる。FIG. 5 also shows a large-scale multilayer wiring board 5.
FIG. 11 is a schematic cross-sectional view of a main part showing a modification in which a cooling structure housing 18 is provided on the back surface of a support plate 2 of No. 0. In this example, the back surface of the support plate 2 is processed into an uneven shape, which is also used as a part of the cooling structure housing 18, and the protruding outer peripheral portion 2 a of the support plate 2 remains through the sealing material 22. The cooling plate 18 is connected to the cooling structure housing 18 so that the support plate 2 can be cooled directly, and the cooling effect can be further improved as compared with the configuration of FIG.

【００３６】いずれの冷却構造筐体１８においても、冷
媒１９は吹き出しノズル２０から矢印方向に流れて、図
示されていない放熱部で熱交換され循環する構成となっ
ている。なお、冷媒としては例えば冷却水が実用的であ
るが、これに限らずその他一般に使用されるガス状もし
くは液状の冷媒が用いられる。In any of the cooling structure casings 18, the refrigerant 19 flows from the blow-out nozzle 20 in the direction of the arrow, and is circulated by exchanging heat in a radiating portion (not shown). Note that, as the refrigerant, for example, cooling water is practical, but not limited thereto, and other commonly used gaseous or liquid refrigerants are used.

【００３７】〈実施例４〉図６は、同一ＬＳＩチップ１
内の電極パッド３を、その上に絶縁層４を介して配設し
た配線層５で相互に配線接続できるようにした大規模多
層配線基板５０を示したもので、実施例１の図１及び図
２の変形例を示している。製造方法としては、基本的に
は実施例１と同様であり、図１（ｂ）〜（ｃ）の製造工
程において、ＬＳＩチップ集団上に絶縁層４としてポリ
イミド層を塗布・キュアによって形成した後、この絶縁
層４上に形成する配線５として１つのＬＳＩチップ１内
の電極パッド３間を相互に結ぶ配線５を形成する。その
後、図２（ａ）〜（ｅ）を形成する工程を経て基板３０
上に配線基板４０を形成した。<Embodiment 4> FIG. 6 shows the same LSI chip 1
1 shows a large-scale multilayer wiring board 50 in which electrode pads 3 inside can be interconnected by a wiring layer 5 disposed thereon via an insulating layer 4. 3 shows a modification of FIG. 2. The manufacturing method is basically the same as that of the first embodiment. In the manufacturing steps of FIGS. 1B to 1C, after a polyimide layer is formed as an insulating layer 4 on a group of LSI chips by coating and curing. Then, as the wiring 5 formed on the insulating layer 4, a wiring 5 connecting the electrode pads 3 in one LSI chip 1 to each other is formed. After that, the substrate 30 is subjected to the steps of forming FIGS.
The wiring substrate 40 was formed thereon.

【００３８】このような配線パタ−ンにすることで、隣
接するＬＳＩチップ１間に残る段差を跨る配線をこの層
では避けることができるため、上記ポリイミド層４で覆
いきれない段差が有る場合でも配線の形状不良発生を防
ぐことができる。また、ＬＳＩチップ１内の配線の一部
を配線層５で受持つことになり、ＬＳＩチップ内の長い
配線を配線抵抗の小さな多層配線部分で行うため、電気
信号の伝播遅延が小さくなり、結果としてＬＳＩの高速
動作を可能とする利点もあるため、今後のＬＳＩの高集
積化による配線微細化に伴う電気信号の伝播遅延増大を
補うことができる。By adopting such a wiring pattern, a wiring crossing a step remaining between the adjacent LSI chips 1 can be avoided in this layer, so that even if there is a step that cannot be covered by the polyimide layer 4, Occurrence of a wiring shape defect can be prevented. In addition, since a part of the wiring in the LSI chip 1 is taken over by the wiring layer 5, a long wiring in the LSI chip is performed by a multilayer wiring part having a small wiring resistance, so that a propagation delay of an electric signal is reduced. In addition, since there is an advantage that the LSI can operate at high speed, it is possible to compensate for an increase in propagation delay of an electric signal due to miniaturization of wiring due to future high integration of the LSI.

【００３９】〈実施例５〉この例は、ＬＳＩチップ及び
その上部に設けた多層配線層の検査回路に関する例を説
明するものである。実施例１に示した大規模多層配線基
板５０は、ＬＳＩチップ１上に配線基板４０を単層もし
くは複数層積層して、直接回路を形成するため、ＬＳＩ
チップ１の回路検査はＬＳＩチップ単体が完成した時点
で行うことが最も望ましいが、これが困難である場合を
考慮して図１（ａ）に示したＬＳＩチップ集団の中に予
備のＬＳＩチップを含ませるか、ＬＳＩチップそのもの
の中に予備回路を設け、さらに塗布・キュアによって形
成した絶縁層４の表面、またはフィルム状配線基板４０
上に、ＬＳＩチップ上の回路および配線基板４０上の回
路を検査するための回路を設ける。また、回路の不良部
分を回路から切離し、予備回路を配線基板４０上の回路
と接続するためのいわゆる冗長回路を設けることにより
ＬＳＩチップ１の不良を救済し、大規模配線基板５０が
機能不全となることを防ぐ。<Embodiment 5> This embodiment describes an example relating to an inspection circuit for an LSI chip and a multilayer wiring layer provided thereon. The large-scale multilayer wiring board 50 shown in the first embodiment is formed by laminating the wiring board 40 on the LSI chip 1 in a single layer or a plurality of layers to directly form a circuit.
It is most preferable that the circuit inspection of the chip 1 be performed when the LSI chip itself is completed. However, in consideration of a case where this is difficult, a spare LSI chip is included in the LSI chip group shown in FIG. Alternatively, a spare circuit is provided in the LSI chip itself, and the surface of the insulating layer 4 formed by coating and curing, or the film-like wiring substrate 40
A circuit for inspecting a circuit on the LSI chip and a circuit on the wiring board 40 is provided thereon. Further, a defective portion of the circuit is separated from the circuit, and a so-called redundant circuit for connecting the spare circuit to the circuit on the wiring board 40 is provided, so that the defect of the LSI chip 1 can be relieved, and the large-scale wiring board 50 becomes malfunctioning. Prevent becoming.

【００４０】[0040]

【発明の効果】本発明によれば、ＬＳＩチップを隙間無
く配設し、チップ間の配線を形成することが可能となる
ので、多層配線基板における配線長を最短とすることが
できるため、多層配線内での電気信号遅延を最小にでき
る。これにより電子計算機や電子交換器のように高速で
電気信号を伝播させる必要の有る装置の機能を大幅に向
上させることができる上、装置を小さくすることができ
る。According to the present invention, it is possible to arrange LSI chips without gaps and to form wiring between the chips, so that the wiring length in the multilayer wiring board can be minimized. Electrical signal delay in wiring can be minimized. As a result, the function of a device such as an electronic computer or an electronic exchanger that needs to propagate an electric signal at high speed can be greatly improved, and the size of the device can be reduced.

【００４１】また、多層配線板の製造法として、予め配
線を形成した配線基板を別途製造しておき、この配線板
をＬＳＩを隙間無く搭載した第１の基板に接合して、配
線板の配線と下層の配線（第１の基板上の配線）との層
間の電気的接続を、めっき処理にて形成することによ
り、多層配線部の製造工程中において２５０℃を越える
ような高温の工程が不要になる。これにより熱応力によ
る配線不良の発生を防ぐことができる上、多層配線を形
成する有機材料の選択枝が非常に広くなり、接着剤を使
用することも可能となる。また、この工程を採用するこ
とにより、各層における配線を予め検査して良品のみ多
層配線板に用いることにより多層配線板の製造歩留まり
低下を防ぐことができる。さらに、配線基板内に冗長回
路を内蔵することでも多層配線基板の製造歩留まり低下
を防ぐことができる。As a method of manufacturing a multilayer wiring board, a wiring board on which wiring is formed in advance is separately manufactured, and this wiring board is bonded to a first substrate on which an LSI is mounted without any gap, and wiring of the wiring board is performed. By forming the electrical connection between the layer and the underlying wiring (wiring on the first substrate) by plating, a high-temperature process exceeding 250 ° C. is not required in the manufacturing process of the multilayer wiring portion. become. As a result, it is possible to prevent the occurrence of wiring failure due to thermal stress. In addition, the selection of organic materials for forming the multilayer wiring becomes very wide, and an adhesive can be used. Further, by adopting this step, it is possible to prevent a decrease in the production yield of the multilayer wiring board by inspecting the wiring in each layer in advance and using only good products for the multilayer wiring board. Furthermore, by incorporating a redundant circuit in the wiring board, it is possible to prevent a reduction in the manufacturing yield of the multilayer wiring board.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例と成る大規模配線基板の製造
工程を示す断面図。FIG. 1 is a sectional view showing a manufacturing process of a large-scale wiring board according to an embodiment of the present invention.

【図２】同じく大規模配線基板の製造工程を示す断面
図。FIG. 2 is a sectional view showing a manufacturing process of the large-scale wiring board.

【図３】同じく大規模配線基板の外部回路との接続部分
の構造を示す断面図。FIG. 3 is a cross-sectional view showing a structure of a connection portion between the large-scale wiring board and an external circuit.

【図４】同じく大規模配線基板のＬＳＩチップ集団の冷
却機構を示す断面図。FIG. 4 is a cross-sectional view showing a cooling mechanism of an LSI chip group of the large-scale wiring board.

【図５】同じく大規模配線基板のＬＳＩチップ集団の異
なる冷却機構を示す断面図。FIG. 5 is a cross-sectional view showing a different cooling mechanism of the LSI chip group of the large-scale wiring board.

【図６】同じく多層配線板内のＬＳＩチップ内・チップ
間の相互配線を示す断面図。FIG. 6 is a cross-sectional view showing interconnections in and between LSI chips in the same multilayer wiring board.

【図７】従来例の樹脂埋込み型による配線基板の構造を
示す断面図。FIG. 7 is a cross-sectional view showing the structure of a conventional wiring board of a resin embedded type.

【符号の説明】[Explanation of symbols]

１…ＬＳＩチップ、 ２…支持基板、３…
ＬＳＩの電極パッド、 ４…絶縁層、４ａ…スル
ーホール、 ５…配線層、６…接着剤、
７…絶縁フィルム（有機絶縁物フィル
ム）、７ａ…スルーホール、 ８…配線金属
層、９…めっき層、 ９ａ…配線金属層
＋めっき層、１０…接続用はんだ、 １１…厚
膜導体、１２…接続パッド、 １３…接続用
ろう材、１４…コネクタ接続用ピン、 １５…コネク
タ接続用ソケット、１６…ピン挿入孔、 １
７…多層配線部、１８…冷却機構筐体、 １９
…冷却媒体、２０…冷媒の吹き出しノズル、 ２１…冷
却機構の接着剤、２２…シ−ル材、 ２３
…チップ埋込用樹脂、３０…第１の基板、
４０…配線基板、５０…大規模配線基板、 ６０
…コネクタ、６１…絶縁基板、 ６２…ス
ルーホール。1 ... LSI chip, 2 ... Support substrate, 3 ...
LSI electrode pad, 4 ... insulating layer, 4a ... through hole, 5 ... wiring layer, 6 ... adhesive,
7 ... insulating film (organic insulating film), 7a ... through hole, 8 ... wiring metal layer, 9 ... plating layer, 9a ... wiring metal layer + plating layer, 10 ... solder for connection, 11 ... thick film conductor, 12 ... Connection pad, 13: connection brazing material, 14: connector connection pin, 15: connector connection socket, 16: pin insertion hole, 1
7: multilayer wiring section, 18: cooling mechanism housing, 19
... Cooling medium, 20 ... Blow-off nozzle of refrigerant, 21 ... Adhesive of cooling mechanism, 22 ... Seal material, 23
... resin for embedding chips, 30 ... first substrate,
40 ... wiring board, 50 ... large-scale wiring board, 60
... Connector, 61 ... Insulating board, 62 ... Through hole.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−258055（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/52 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-258055 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 23/52

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】電極パッドの形成された面を上向きにし
て複数のＬＳＩチップを支持基板上に隙間無く配列する
と共に、その背面を支持基板に固着したＬＳＩチップ集
団の表面に、絶縁層に配設されたスルーホールを介して
前記電極パッドに接続された配線層を形成して成る第１
の基板と、予めスルーホールの形成された絶縁シート
に配線パターンが形成された配線基板と、前記第１の
基板に前記配線基板を接着剤で固着、積層し、前記配線
基板のスルーホールを介して前記第１の基板の配線層と
前記配線基板上の配線パターンとを電気的に接続するめ
っき金属層とを有して成る大規模配線基板であって、前
記配線基板の最上層の配線層に、ピン付きコネクタを導
体で接続してコネクタ付き配線基板として成る大規模配
線基板。The surface on which an electrode pad is formed faces upward.
Multiple LSI chips on a support substrate without gaps
Also, a collection of LSI chips whose back surface is fixed to a support substrate
Through the through-holes provided in the insulating layer
A first layer formed by forming a wiring layer connected to the electrode pad;
Board and insulating sheet with through holes formed in advance
A wiring board on which a wiring pattern is formed;
The wiring substrate is fixed to the substrate with an adhesive, laminated, and the wiring
A wiring layer of the first substrate through a through hole of the substrate;
To electrically connect with the wiring pattern on the wiring board
A large-scale wiring board having a metal layer;
A large-scale wiring board which is a wiring board with a connector, in which a connector with pins is connected to the uppermost wiring layer of the wiring board with a conductor. 【請求項２】電極パッドの形成された面を上向きにし
て複数のＬＳＩチップを支持基板上に隙間無く配列する
と共に、その背面を支持基板に固着したＬＳＩチップ集
団の表面に、絶縁層に配設されたスルーホールを介して
前記電極パッドに接続された配線層を形成して成る第１
の基板と、予めスルーホールの形成された絶縁シート
に配線パターンが形成された配線基板と、前記第１の
基板に前記配線基板を接着剤で固着、積層し、前記配線
基板のスルーホールを介して前記第１の基板の配線層と
前記配線基板上の配線パターンとを電気的に接続するめ
っき金属層とを有して成る大規模配線基板であって、前
記支持基板の背面に、冷却機構筐体を配設して成る大規
模配線基板。2. The surface on which electrode pads are formed is directed upward.
Multiple LSI chips on a support substrate without gaps
Also, a collection of LSI chips whose back surface is fixed to a support substrate
Through the through-holes provided in the insulating layer
A first layer formed by forming a wiring layer connected to the electrode pad;
Board and insulating sheet with through holes formed in advance
A wiring board on which a wiring pattern is formed;
The wiring substrate is fixed to the substrate with an adhesive, laminated, and the wiring
A wiring layer of the first substrate through a through hole of the substrate;
To electrically connect with the wiring pattern on the wiring board
A large-scale wiring board having a metal layer;
A large-scale wiring board in which a cooling mechanism housing is disposed on the back of the support board. 【請求項３】電極パッドの形成された面を上向きにし
て複数のＬＳＩチップを支持基板上に隙間無く配列する
と共に、その背面を支持基板に固着するに際し、各チッ
プ上面を同一平面となるよう配設して、ＬＳＩチップ集
団を固着する工程と、前記ＬＳＩチップ集団の表面
に、絶縁層を形成した後、前記電極パッド上の位置に対
応する絶縁層にスルーホールを形成し、このスルーホー
ルを介して同一チップ内もしくは隣接するチップ間の電
極パッド間を電気的に接続する配線層を形成して第１の
基板を準備する工程と、絶縁シートを準備し、前記第
１の基板上の配線 層に対応させた位置にスルーホールを
形成すると共に、このスルーホールを配線回路の一つと
して含む配線パターンを絶縁シート上に形成して配線基
板を形成する工程と、前記第１の基板に前記配線基板
を接着剤で固着、積層する工程と、 前記積層された配線基板にめっき処理を施し、スルー
ホールを介して前記第１の基板の配線層と前記配線基板
上の配線パターンとを電気的に接続する工程とを有して
成る大規模配線基板の製造方法であって、前記 の積層
工程の後に、スルーホール底部の配線層上に残留した不
要な接着剤を除去する工程を付加して成る大規模配線基
板の製造方法。3. The surface on which the electrode pads are formed faces upward.
Multiple LSI chips on a support substrate without gaps
At the same time, when fixing the back to the support substrate,
The top surface of the LSI chip is
Fixing a group, and a surface of the LSI chip group
After forming an insulating layer, the position on the electrode pad is
Form a through hole in the corresponding insulating layer and
Of the same chip or between adjacent chips
Forming a wiring layer for electrically connecting between the electrode pads;
Preparing a substrate, preparing an insulating sheet,
A through hole at a position corresponding to the wiring layer on the
While forming this through hole as one of the wiring circuits
The wiring pattern included on the insulating sheet is
Forming a board; and attaching the wiring board to the first board.
Bonding with an adhesive, laminating, and plating the laminated wiring board, through
A wiring layer of the first substrate and the wiring substrate through a hole
Electrically connecting the upper wiring pattern
A method for manufacturing a large-scale wiring board, comprising a step of removing unnecessary adhesive remaining on a wiring layer at the bottom of a through hole after the laminating step. 【請求項４】電極パッドの形成された面を上向きにし
て複数のＬＳＩチップを支持基板上に隙間無く配列する
と共に、その背面を支持基板に固着するに際し、各チッ
プ上面を同一平面となるよう配設して、ＬＳＩチップ集
団を固着する工程と、前記ＬＳＩチップ集団の表面
に、絶縁層を形成した後、前記電極パッド上の位置に対
応する絶縁層にスルーホールを形成し、このスルーホー
ルを介して同一チップ内もしくは隣接するチップ間の電
極パッド間を電気的に接続する配線層を形成して第１の
基板を準備する工程と、絶縁シートを準備し、前記第
１の基板上の配線層に対応させた位置にスルーホールを
形成すると共に、このスルーホールを配線回路の一つと
して含む配線パターンを絶縁シート上に形成して配線基
板を形成する工程と、前記第１の基板に前記配線基板
を接着剤で固着、積層する工程と、 前記積層された配線基板にめっき処理を施し、スルー
ホールを介して前記第１の基板の配線層と前記配線基板
上の配線パターンとを電気的に接続する工程とを有して
成る大規模配線基板の製造方法であって、前記 の第１
の基板を準備する工程における配線層の形成に際して
は、成膜工程により順次Ｃｒ／Ｃｕ／Ｃｒを成膜して３
層膜とするか、もしくはＴｉ／Ｃｕ／Ｃｒの３層膜と
し、上記の積層工程の後に、スルーホール底部に表れ
た配線層の最表層のＣｒをエッチング処理により除去し
て下地のＣｕ層を露出させる工程を付加し、のめっき
処理をＣｕもしくはＮｉめっき処理工程として成る大規
模配線基板の製造方法。4. The surface on which the electrode pads are formed faces upward.
Multiple LSI chips on a support substrate without gaps
At the same time, when fixing the back to the support substrate,
The top surface of the LSI chip is
Fixing a group, and a surface of the LSI chip group
After forming an insulating layer, the position on the electrode pad is
Form a through hole in the corresponding insulating layer and
Of the same chip or between adjacent chips
Forming a wiring layer for electrically connecting between the electrode pads;
Preparing a substrate, preparing an insulating sheet,
A through hole at a position corresponding to the wiring layer on the
While forming this through hole as one of the wiring circuits
The wiring pattern included on the insulating sheet is
Forming a board; and attaching the wiring board to the first board.
Bonding with an adhesive, laminating, and plating the laminated wiring board, through
A wiring layer of the first substrate and the wiring substrate through a hole
Electrically connecting the upper wiring pattern
The method for manufacturing a large-scale wiring board, comprising :
In forming the wiring layer in the step of preparing the substrate, Cr / Cu / Cr is sequentially formed in a film forming step to form a wiring layer.
After the above-mentioned laminating step, the outermost layer of the wiring layer appearing at the bottom of the through-hole is removed by etching to remove the underlying Cu layer. A method for manufacturing a large-scale wiring board, wherein an exposing step is added, and the plating process is a Cu or Ni plating process.
JP18066192A 1992-07-08 1992-07-08 Large-scale wiring board and manufacturing method thereof Expired - Fee Related JP3172267B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18066192A JP3172267B2 (en) 1992-07-08 1992-07-08 Large-scale wiring board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18066192A JP3172267B2 (en) 1992-07-08 1992-07-08 Large-scale wiring board and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH0629355A JPH0629355A (en) 1994-02-04
JP3172267B2 true JP3172267B2 (en) 2001-06-04

Family

ID=16087109

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001267747A (en) * 2000-03-22 2001-09-28 Nitto Denko Corp Manufacturing method for multi-layered circuit board
JP4441974B2 (en) * 2000-03-24 2010-03-31 ソニー株式会社 Manufacturing method of semiconductor device

Also Published As

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