JP2712936B2 - Polyimide multilayer wiring board and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and a manufacturing method of a polyimide multilayer wiring board having a multilayer wiring layer using a polyimide resin for interlayer insulation on a ceramic substrate or a hard organic resin substrate, and more particularly to a structure of a polyimide resin layer. And a lamination method.

[0002]

2. Description of the Related Art A multilayer printed wiring board has conventionally been used as a wiring board on which an LSI chip is mounted.
The multilayer printed wiring board is configured by using a copper-clad laminate as a core material and a prepreg as an adhesive for the core material, alternately laminating the core material and the prepreg, and integrating them using a hot press.
The electrical connection between the laminated plates is performed by integrating the core material and the prepreg, forming a through hole with a drill, and plating the inner wall of the through hole with copper.

In recent years, a multilayer wiring board using a polyimide resin for interlayer insulation on a ceramic substrate has been used as a wiring board for a large computer which requires a higher wiring density than a multilayer printed wiring board. This polyimide-ceramic multilayer wiring board uses a polyimide resin insulating layer forming step of applying and drying a polyimide precursor varnish on a ceramic substrate and forming a via hole in this coating film, and uses photolithography, vacuum evaporation and plating methods. And a series of steps are repeated to form a polyimide multilayer wiring layer.

In addition to the above-described method for forming a polyimide / ceramic multilayer wiring substrate, a wiring pattern is formed on a polyimide sheet, and the sheet is positioned on the ceramic substrate and sequentially laminated under pressure to form a multilayer wiring. There is also a method of forming a substrate. According to this method, since the signal layer is formed in sheet units, sheets having no defect can be selected and stacked, and the production yield can be increased as compared with the above-described sequential stacking method.

[0005]

In the above-mentioned multilayer printed wiring board, electrical connection between the laminated boards is performed by through-holes formed by drilling, so that fine through-holes cannot be formed. Therefore, the number of wirings that can be formed between through holes is limited. Further, one through-hole is required for connection between one laminated board, and as the number of laminated layers increases, the signal wiring accommodating property decreases, and it becomes difficult to form a multilayer printed wiring board with a high wiring density. There was a disadvantage.

In order to compensate for the above-mentioned disadvantages of the conventional multilayer printed wiring board, a recently developed polyimide-ceramic multilayer wiring board has a polyimide precursor on the ceramic substrate as many times as the number of laminated polyimide insulating layers. It is necessary to repeat each step of varnish application, drying, formation of via holes, and curing. Therefore, it takes a very long time for the lamination process of the multilayer wiring board. In addition, since the process of forming the polyimide insulating layer is repeatedly performed, the thermal stress of the curing process performed many times is applied to the polyimide resin in the lower layer portion of the multilayer wiring layer, so that the polyimide resin is deteriorated. . Further, since the polyimide multilayer wiring layer is of a sequential lamination type, it is difficult to improve the production yield. There is a disadvantage that.

Also, in the sheet-based lamination method developed as a method for improving the manufacturing yield, since the pressure lamination is performed sequentially one layer at a time, the higher the number of layers, the more the thermal stress is applied to the lower layer of the polyimide resin and the lower the polyimide resin. The disadvantages of degradation and long substrate manufacturing days are not improved.

[0008]

According to the present invention, there is provided a polyimide multi-layer wiring board comprising a plurality of polyimide multi-layer wiring layers formed on a ceramic substrate or a hard organic resin plate having a conductor layer therein. a plurality of the blocks have a layered structure obtained by laminating those forming the wiring layer as a single block, the anisotropic conductive film adhesion and electrical connection sandwiched between the blocks between each block It is a polyimide multilayer wiring board having a structure characterized by being performed by pressing and heating, and the step of forming this polyimide multilayer wiring board includes a ceramic plate or a hard organic resin plate having a conductor layer inside. A plurality of polyimide wiring layers formed on the front and back are combined into one block, and via holes are formed on the surface of the polyimide wiring layer. To form a metal via electrically connected to the internal wiring layer or a polyimide via hole with a metal part electrically connected to the bottom surface, and to form a polyimide multilayer wiring layer on a ceramic substrate or a hard organic resin substrate A polyimide via having a metal bump electrically connected to an internal wiring layer via a via hole on the surface of the polyimide multi-layer wiring layer or a metal via electrically similarly connected metal portion on the bottom surface of the polyimide multilayer wiring layer. A hole is formed, and the surface of the polyimide wiring layer on the ceramic substrate formed by the ceramic plate having the conductor layer inside or the polyimide surface of the polyimide multilayer wiring layer on the back surface of the hard organic resin plate formed by After positioning and overlaying each other via a conductive film, under pressure and heating conditions, the polyimide multilayer formed by The polyimide surface of the polyimide multilayer wiring layer formed with the polyimide surface of the wire layer is bonded by the adhesive force of the adhesive layer of the anisotropic conductive film, and at the same time, the metal bumps or the metal on the bottom surface of the via hole and the metal bump are bonded. By connecting with the conductive particles in the anisotropic conductive film to electrically connect the laminated structures, and repeating the above steps a plurality of times, a polyimide multilayer wiring layer laminated body is formed on the ceramic substrate or the hard organic resin substrate A method for manufacturing a polyimide multilayer wiring board.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a polyimide multilayer wiring board according to the present invention. The ceramic base substrate 12 used in this embodiment is a co-fired alumina ceramic substrate having input / output pins 11 on the back surface of the substrate and having an internal wiring layer of molybdenum metal. The specifications of the polyimide multilayer wiring layer are as follows. The signal wiring 15 has a line width of 25 μm and a wiring thickness of 7 μm.
m gold-plated wiring. The signal wiring is a set of the X direction and the Y direction, and the upper and lower portions thereof are sandwiched between ground wiring layers 13 to adjust impedance and reduce crosstalk noise. Polyimide resin 14 used is, for example, if non-photosensitive, PIQ of Hitachi Chemical, PYRALIN of DuPont,
Hitachi Chemical's PL-
1200, DuPont PI-2702D, Toray Photo Nice, Asahi Kasei PIMEL etc.
0 μm. The number of signal wiring layers is eight. The basic configuration is that one ground electrode layer and one signal wiring layer are respectively located on the front and back of a ceramic plate having a conductor layer inside. Therefore, this embodiment is composed of four blocks. When each block is completed, an electrical inspection is performed to select non-defective blocks, and the process proceeds to the next step of connecting blocks. The electrical connection between the blocks is made by conductive particles present in the nickel-gold bumps 16 plated with gold on the nickel plating, with an anisotropic conductive film 17 interposed therebetween. The size of the nickel / gold bump is, for example, 25-3.
It is formed with a thickness of 00 μm square and 10 to 50 μm.
The thickness of the anisotropic conductive film is 20 to 30 μm, the particle size of the conductive particles present in the film is 5 to 25 μm, and the concentration of the conductive particles in the anisotropic conductive film is 5 μm.
-20% by volume. As the anisotropic conductive film, for example, SUMIZAC1003 manufactured by Sumitomo Bakelite Co., Ltd. is used. On the uppermost layer of the formed polyimide multilayer wiring board, connection pads 110 for soldering the LSI chip are formed by copper plating.

FIGS. 2 to 4 show a first embodiment of a method for manufacturing a polyimide multilayer wiring board according to the present invention in the order of steps. The specification of the polyimide multilayer wiring layer portion of the polyimide multilayer wiring board of this embodiment is the same as that of the embodiment of FIG. Photosensitive polyimide is used for the polyimide resin, and gold is used for the wiring metal.

The steps of manufacturing the polyimide multilayer wiring board of this embodiment are as follows.

First, FIG. 2 shows a manufacturing process of one block in which one grounding and connection layer 22 and one signal wiring layer 25 are provided on the front and back of a ceramic plate 21 having a conductor layer therein.

The steps (1) to (4) described below are first performed on the front side of the ceramic plate 21 having a conductor layer inside, and then performed on the rear side. By alternately stacking the front side and the back side of the board, the stress applied to the ceramic board by the polyimide multilayer wiring layer is offset, and the warpage of the ceramic board is reduced.

(1) A grounding and connection wiring layer is patterned on the surface of a ceramic plate 21 having a conductor layer therein by photolithography using a photoresist, and electrolytic gold plating is performed to form a grounding and connection wiring layer 22.

(2) A photosensitive polyimide varnish 23 is coated on a ceramic plate having a conductor layer inside the ground and connection layer formed in (1), and exposed and developed to form a via hole 24 at a predetermined position. And cure.

(3) One signal wiring layer 25 is formed in the same manner by the method of forming the ground and connection layers in (1).

(4) A connection bump 26 is formed on the uppermost layer of the multilayer wiring layer formed in the above (3) at a position where electrical connection is made with the multilayer wiring layer formed in the following (5) and thereafter. The bumps are patterned by photolithography using a photoresist, and are formed in multiple layers of electrolytic nickel plating and electrolytic gold plating. Nickel plating is a layer for preventing gold / tin, which is conductive particles of the anisotropic conductive film, from diffusing into the gold wiring layer. Each plating thickness is 10 μm for nickel and 3 μm for gold.

The above description relates to the manufacture of a block having the basic configuration.

Further, as shown in FIG. 3, one ground and connection layer 22 and one signal wiring layer 25 are formed on a ceramic substrate 27 on which input / output pins 210 are finally assembled on the rear surface.

(5) Eventually, the ground and connection wiring layers 22 are patterned by photolithography using a photoresist on the ceramic substrate 27 on which the input / output signal pins and the power supply pins 210 are on the back surface, and are ground by electrolytic gold plating. And forming a connection wiring layer.

(6) A photosensitive polyimide varnish 23 is applied on the ceramic substrate on which the grounding and connection layers are formed in (5), and exposure and development are performed to form via holes 24 at predetermined positions, and curing is performed.

(7) One signal wiring layer 25 is formed by (5)
And the connection layer is formed in the same manner.

(8) On the polyimide layer formed in (7), connection bumps 26 are formed at positions where they are to be electrically connected to the multilayer wiring layers formed in (1) to (4). The bumps are patterned by photolithography using a photoresist, and are formed by multilayer plating of electrolytic nickel plating and electrolytic gold plating. The plating thickness of nickel and gold is the same as in the above (4).

Next, a plurality of blocks formed by the above (1) to (4) are laminated on the ceramic multilayer substrate formed by the above (5) to (8) shown in FIG. The step of completing the polyimide multilayer wiring board will be described.

(9) A polyimide layer having the connection metal bump 26 formed in (4) of the polyimide multi-layer wiring layer on the ceramic plate having a conductor layer therein formed in (1) to (4) above; The polyimide multi-layer wiring layer having the metal bumps 26 on the ceramic substrate formed in the above (5) to (8) is positioned through the anisotropic conductive film 28, and then superposed, pressed and heated. Then, the polyimide films are bonded and fixed by the adhesive force of the anisotropic conductive film 28. At this time, the conductive particles of gold / tin existing in the anisotropic conductive film 28 are crushed between the metal bumps 26 formed in (4) and the metal bumps 26 formed in (8), and the two laminated structures are formed. Make an electrical connection. Where there is no metal bump, the conductive particles are not crushed, so there is no continuity in the lateral direction, and no short circuit occurs between adjacent metal bumps. The insulation resistance at this time is 10
⁹ Ω or more. The details of the pressurizing and heating methods are as follows. Here, an anisotropic conductive film having a carrier film is used. As the carrier film, a polyester film having a thickness of 50 to 100 μm is used. First, an anisotropic conductive film cut to the size of the substrate is laminated on a polyimide multilayer wiring layer having metal bumps on the ceramic substrate formed in the above (5) to (8), and then 135 ° C., 3 to 5 kg / ^{2 under} the condition of cm 2
Temporarily crimp for 3 seconds. Next, the carrier film is peeled off from the anisotropic conductive film, and the connection metal formed in (4) of the polyimide multilayer wiring layer on the ceramic plate having the conductor layer formed therein in the above (1) to (4) The polyimide layer having bumps is aligned. After being superimposed on the substrate, final press bonding is performed at 150 to 160 ° C. and 30 to 40 kg / cm ² for 20 to 30 seconds. Here, a vacuum hydraulic press device is used for temporary press bonding and final press bonding,
It is performed in a reduced pressure state of 0 Torr or less.

(10) On the polyimide wiring layer laminate formed in the above steps (1) to (9), a ceramic plate having a conductor layer in another inside formed in the above steps (1) to (4) The above polyimide wiring layer is laminated and integrated by the method (9).

(11) The above step (10) is repeated until the number of signal wiring layers becomes eight.

(12) Next, a connection electrode layer 29 for connecting the multilayer wiring board and the wiring of the LSI chip is formed. For this reason, it is not necessary to form a connection metal bump on the uppermost layer of the block to be stacked last. Instead, a connection electrode pad is formed on the polyimide layer on the surface to perform solder connection with the bump of the chip carrier in which the LSI chip is sealed. At this time, tin-lead eutectic solder is used as solder for connecting the bumps of the LSI chip carrier and the connection electrode pads, and the connection electrode pads are formed by copper plating without tin-lead solder erosion.

(13) Finally, input / output signal pins and power supply pins 210 are assembled at predetermined positions on the back surface of the ceramic substrate 27.

FIGS. 5 to 7 show a second embodiment of the method for manufacturing a polyimide multilayer wiring board according to the present invention in the order of steps. The specification of the polyimide multilayer wiring layer portion of the polyimide multilayer wiring board of this embodiment is the same as that of the embodiment of FIG. Photosensitive polyimide is used for the polyimide resin, and multi-layer plating of copper and nickel is used for the wiring metal, and the thickness of each is 6.5 μm for copper plating and 0.5 μm for nickel plating. Here, the nickel plating on the copper plating, the photosensitive polyimide used in the present example easily reacts with metallic copper,
It is a barrier metal that prevents metallic copper from directly contacting the photosensitive polyimide because it adversely affects the polyimide.

The steps of manufacturing the polyimide multilayer wiring board according to the second embodiment are as follows.

First, FIG. 5 shows a process of manufacturing one block in which one grounding and connection layer 32 and one signal wiring layer 35 are provided on the front and back surfaces of the hard organic resin plate 31 having a conductor layer inside.

Each of the steps (1) to (5) described below is first performed on the front side of the hard organic resin plate having a conductor layer inside, and then performed on the rear side. By alternately stacking the front side and the back side of the board, the stress caused by the polyimide multilayer wiring layer applied to the hard organic resin board is offset, and the amount of warpage of the hard organic resin board is reduced.

(1) The grounding and connection wiring layer is patterned on the hard organic resin plate 31 by photolithography using a photoresist, electrolytic copper plating is performed, and then electroless nickel plating is performed to form the grounding and connection wiring layer 32. Form.

(2) A photosensitive polyimide varnish 33 is applied on the hard organic resin plate on which the grounding and connection layers are formed in (1), and is exposed and developed to form a via hole 34 at a predetermined position and cure. Do.

(3) One signal wiring layer 35 is formed by (1)
And the connection layer is formed in the same manner.

(4) A polyimide varnish is applied only on the surface of the hard organic resin plate on the signal wiring layer formed in the above (3), and is exposed and developed to form a via hole at a predetermined position. Do. At this time, the via hole on the front side of the hard organic resin plate is for connection and its size is
At the time of connection, it is formed larger than the other metal bump.
For example, when the size of the metal bump is 25 to 300 μm, the size of the connection via hole 36 is formed to be 30 to 350 μm.

(5) Only the rear side of the hard organic resin plate is provided on the uppermost layer of the multilayer wiring layer formed in the above (3) with the following (6)
The connection bumps 37 are formed at positions where electrical connection with the multilayer wiring layer to be formed thereafter is made. The bumps are patterned by photolithography using a photoresist and formed by electrolytic copper plating. The thickness of the bump is 60 μm.

The above description relates to the manufacture of a block having a basic configuration.

As shown in FIG. 6, separately from the above, one ground and connection layer and one signal wiring layer 35 are formed on a ceramic substrate 38 on which the input / output pins 311 are finally assembled on the back surface.

(6) The grounding and connection wiring layer 32 is patterned by photolithography using a photoresist on the ceramic substrate 38 on which the input / output signal pins and the power supply pins 311 finally come to the back side, and electrolytic copper plating is performed. After that, electroless nickel plating is performed to ground and connect wiring layer 3
Form 2

(7) A photosensitive polyimide varnish 33 is applied on the ceramic substrate on which the grounding and connection layers are formed in (6), and exposure and development are performed to form via holes 34 at predetermined positions, and curing is performed.

(8) One signal wiring layer 35 is
In the same manner, the grounding and the connection layer are formed in the same manner.

(9) A polyimide varnish is applied on the signal wiring layer formed in (8), and exposure and development are performed to form via holes 36 at predetermined positions, and curing is performed. The via hole formed at this time is for connection, and its size is formed larger than the metal bump to be connected at the time of connection. For example, when the size of the metal bump is 25 to 300 μm, the size of the connection via hole is 30 to 350 μm.

Next, a plurality of blocks formed by the above (1) to (5) are laminated on the ceramic multilayer substrate formed by the above (6) to (9) shown in FIG. The step of completing the multilayer wiring board will be described.

(10) The polyimide layer having the connection bumps 37 formed in (5) of the polyimide multi-layer wiring layer on the back surface of the hard organic resin plate 31 formed in (1) to (5) and (6) ) To (9), the polyimide multilayer wiring layer having the connection via holes 36 on the ceramic substrate is positioned between the polyimide wiring layers via the anisotropic conductive film 39, and then laminated, pressurized and heated. Then, the polyimide films are bonded and fixed by the adhesive force of the anisotropic conductive film 39. At this time, the indium / lead conductive particles present in the anisotropic conductive film are crushed by the connection bumps 37 formed in (5) and the wiring metal on the bottom surface of the connection via holes 36 formed in (9), and two. Are electrically connected. Where there is no metal bump, the conductive particles are not crushed, so there is no continuity in the lateral direction, and no short circuit occurs between adjacent metal bumps.
The insulation resistance at this time is 10 ⁹ Ω or more.

The details of the pressurizing and heating methods are as follows. Here, an anisotropic conductive film having a carrier film is used. Carrier film thickness 5
A polyester film of 0 to 100 μm is used. First, an anisotropic conductive film cut to the size of a substrate is laminated on a polyimide multi-layer wiring layer having connection via holes on the ceramic substrate formed in the above (6) to (9), ^{2 under} the condition of 5 kg / cm 2
Temporarily press-bond for ~ 3 seconds. Next, the carrier film is peeled off from the anisotropic conductive film, and the polyimide layer having the connection bump formed in (5) of the polyimide multilayer wiring layer on the back surface of the hard organic resin plate formed in (1) to (5) above Perform position adjustment. 150-16 after superimposed on the substrate
The final press bonding is performed at 0 ° C. and 30 to 40 kg / cm ² for 20 to 30 seconds. Here, a vacuum hydraulic press device is used for the temporary pressure bonding and the final pressure bonding, and the pressing is performed in a reduced pressure state of 10 Torr or less.

(11) On the polyimide wiring layer laminate formed in the above steps (1) to (10), a hard organic material having a conductor layer in another inside formed in the above steps (1) to (5) is formed. The polyimide wiring layer of the resin plate is laminated and integrated by the method (10).

(12) The above step (11) is repeated until the number of signal wiring layers becomes eight.

(13) Next, a connection electrode layer 310 for connecting the multilayer wiring board and the wiring of the LSI chip is formed. For this reason, it is not necessary to form a connection via hole in the uppermost layer of the block to be stacked last. Instead, a connection electrode pad is formed on the polyimide layer on the surface to perform solder connection with the bump of the chip carrier in which the LSI chip is sealed. At this time, tin-lead eutectic solder is used as solder for connecting the bumps of the LSI chip carrier and the connection electrode pads, and the connection electrode pads are formed by copper plating without tin-lead solder erosion.

(14) Finally, input / output signal pins and power supply pins 311 are assembled at predetermined positions on the back surface of the ceramic substrate 38.

FIGS. 8 to 10 show a third embodiment of the method for manufacturing a polyimide multilayer wiring board according to the present invention in the order of steps. The specification of the polyimide multilayer wiring layer portion of the polyimide multilayer wiring board of this embodiment is the same as that of the embodiment of FIG. Photosensitive polyimide is used for the polyimide resin, and multi-layer plating of copper and nickel is used for the wiring metal, and the thickness of each is 6.5 μm for copper plating and 0.5 μm for nickel plating. Here, the nickel plating on the copper plating, the photosensitive polyimide used in the present example easily reacts with metallic copper,
It is a barrier metal that prevents metallic copper from directly contacting the photosensitive polyimide because it adversely affects the polyimide.

[0054] manufacturing process of the polyimide multilayer wiring substrate of the third embodiment are the following topics: Ride.

First, FIG. 8 shows a manufacturing process of one block in which one grounding and connection layer 42 and one signal wiring layer 45 are provided on the surface of a hard organic resin plate 41 having a conductor layer inside.

Each of the steps (1) to (5) described below is performed first on the front side of the hard organic resin plate having the conductor layer inside, and then on the rear side. By alternately stacking the front side and the back side of the board, the stress due to the polyimide multilayer wiring layer applied to the hard organic resin board 41 is offset, and the amount of warpage of the hard organic resin board is reduced.

(1) The grounding and connection wiring layer is patterned on the hard organic resin plate 41 by photolithography using a photoresist, electrolytic copper plating is performed, and then electroless nickel plating is performed to form the grounding and connection wiring layer. Form.

(2) Photosensitive polyimide varnish 43 is hard organic resin plate 4 on which grounding and connection layers are formed in (1).
1 is applied, exposed and developed to form a via hole 44 at a predetermined position, and curing is performed.

(3) One signal wiring layer 45 is formed by (1)
And the connection layer is formed in the same manner.

(4) A polyimide varnish is applied only on the rear surface side of the hard organic resin plate 41 to the signal wiring layer formed in the above (3), exposure and development are performed to form via holes at predetermined positions, and curing is performed. Do. At this time, the via hole 44 on the back surface side of the hard organic resin plate is for connection, and the size thereof is formed larger than the metal bump which is the partner at the time of connection. For example, when the size of the metal bump is 25 to 300 μm, the size of the connection via hole is 30 to 350 μm.

(5) A position on the uppermost layer of the multilayer wiring layer formed in the above (3) only on the surface side of the hard organic resin plate 41, where electrical connection with the multilayer wiring layer formed in the following (6) and thereafter is made. A connection bump 47 is formed on the substrate. The bumps are patterned by photolithography using photoresist,
It is formed by electrolytic copper plating. The thickness of the bump is 60 μm.

The above description relates to the manufacture of a block having the basic configuration.

Next, as shown in FIG. 9, one ground and connection layer 42 and one signal wiring layer 45 are formed on a ceramic substrate 48 on which the input / output pins 411 are finally assembled on the rear surface.

(6) The ground and connection wiring layer 42 is patterned by photolithography using a photoresist on the ceramic substrate 48 on which the input / output signal pins and the power supply pins 411 are finally provided, and electrolytic copper plating is performed. After that, electroless nickel plating is applied to ground and connection wiring layer 4
Form 2

(7) A photosensitive polyimide varnish 34 is applied on the ceramic substrate on which the grounding and connection layer 42 has been formed in (6), exposed and developed to form a via hole 44 at a predetermined position, and curing is performed. .

(8) One signal wiring layer 45 is
And the connection layer 42 is formed in the same manner.

(9) On the signal wiring layer 45 formed in (8), the connection bumps 47 are formed at positions where electrical connection is made with the multilayer wiring layers formed in (1) to (5). The bumps are patterned by photolithography using a photoresist and formed by electrolytic copper plating. The thickness of the bump is 60 μm.

Further, on the ceramic multilayer substrate formed in the above (6) to (9) shown in FIG.
The step of stacking a plurality of blocks formed in (5) to (5) to complete the polyimide multilayer wiring board of the present invention will be described.

(10) Polyimide multilayer wiring layer having connection via hole 46 formed in (5) of polyimide multilayer wiring layer on back surface of hard organic resin plate 41 formed in (1) to (5) above And a polyimide multi-layer wiring layer having connection bumps 47 on the ceramic substrate formed in the above (6) to (9) is positioned with an anisotropic conductive film 49 interposed therebetween, and then overlapped. By applying pressure and heating, the polyimide films are bonded and fixed to each other by the adhesive force of the anisotropic conductive film 49. At this time, the conductive metal of indium / lead existing in the anisotropic conductive film 49 is crushed by the wiring metal on the bottom surface of the connection via hole 46 formed in (5) and the connection bump 47 formed in (9). , The two laminated structures are electrically connected. Where there is no metal bump, the conductive particles are not crushed, so there is no continuity in the lateral direction, and no short circuit occurs between adjacent metal bumps. The insulation resistance at this time is 10 ⁹ Ω or more. The details of the pressurizing and heating methods are as follows. The anisotropic conductive film 49 used here has a carrier film. Carrier film thickness 50-1
A 00 μm polyester film is used. First, an anisotropic conductive film cut to the size of a substrate is laminated on a polyimide multi-layer wiring layer having connection bumps on the ceramic substrate formed in the above (6) to (9), and 135 ° C., 3 to 5 kg / Cm ² for 2 to 3 seconds. Next, the carrier film is peeled off from the anisotropic conductive film, and the polyimide having the connection via hole formed in (5) of the polyimide multilayer wiring layer on the back surface of the hard organic resin plate formed in (1) to (5) above Perform layer alignment. 150-160 ° C after superimposing on the substrate,
The main bonding is performed for 20 to 30 seconds under the condition of 30 to 40 kg / cm ² . Here, a vacuum hydraulic press device is used for the temporary pressure bonding and the final pressure bonding, and the pressing is performed in a reduced pressure state of 10 Torr or less.

(11) On the polyimide wiring layer laminate formed in the above steps (1) to (10), a hard organic material having a conductor layer in another inside formed in the above steps (1) to (5) is formed. The polyimide wiring layer of the resin plate 41 is laminated and integrated by the method (10).

(12) The above step (11) is repeated until the number of signal wiring layers becomes eight.

(13) Next, a connection electrode layer 410 for connecting the multilayer wiring board and the wiring of the LSI chip is formed. For this reason, it is not necessary to form a connection bump on the top layer of the last stacked block. Instead, a connection electrode pad is formed on the polyimide layer on the surface to perform solder connection with the bump of the chip carrier in which the LSI chip is sealed.
At this time, tin-lead eutectic solder is used as solder for connecting the bumps of the LSI chip carrier and the connection electrode pads, and the connection electrode pads are formed by copper plating without tin-lead solder erosion.

(14) Finally, input / output signal pins and power supply pins 411 are assembled at predetermined positions on the back surface of the ceramic substrate.

In the above-described embodiment, the polyimide multilayer wiring layer is formed on the ceramic substrate. However, in addition to the ceramic substrate, a hard organic resin substrate 52, for example, a polyimide resin molded substrate can be used. In this case, as shown in FIG. 11, the input / output pins 51 are formed by forming through-holes in the polyimide resin molded substrate 52 and driving the input / output pins. FIG. 11 is a cross-sectional view of a polyimide multilayer wiring board using this polyimide resin molded board. The multilayer wiring board of the present embodiment can accurately match the thermal expansion coefficient of the polyimide resin molded substrate 52 serving as a base and the polyimide multilayer wiring layer having a wiring layer, and is particularly suitable for manufacturing a large-area high-layer wiring board. ing.

By using the method described above, it is possible to form a high wiring density polyimide multilayer wiring board having a high number of laminations in a very short manufacturing time as compared with a conventional sequential lamination type polyimide ceramic multilayer wiring board. Can and
Since electrical inspection can be performed for each block and non-defective blocks can be selected and laminated, a high manufacturing yield can be realized.

[0076]

As described above, the polyimide multilayer wiring board of the present invention has a structure of a polyimide multilayer wiring layer in which a plurality of wiring layers are formed on the front and back of a ceramic plate or a hard organic resin plate having a conductor layer inside. The conventional multi-layer printing method is characterized in that a single block is formed as a laminated structure of a plurality of blocks, and electrical connection between the blocks is performed by an anisotropic conductive film sandwiched between the blocks. Through-holes required for wiring boards are no longer necessary, and fine patterns can be formed in the signal wiring layer.
High-density wiring can be realized, and a curing process that is performed many times is unnecessary as in the conventional polyimide-ceramic multilayer wiring substrate. This shortens the wiring board manufacturing time and reduces the heat of the polyimide resin by performing the curing process many times. Since deterioration can be prevented and the electrical inspection of the wiring layer can be performed in block units, non-defective blocks can be selected and stacked. Also, since the thin-film multilayer wiring portion includes a ceramic plate or a hard organic resin plate having a conductor layer inside, even if the number of layers required for the thin-film multilayer wiring portion increases, cracks in the polyimide resin or ceramic plates may be caused. Harmful effects such as peeling of the ceramic plate or cracking of the ceramic plate can be reduced. Therefore, the present invention has an effect that a high-quality, high-multilayer, high-wiring-density polyimide multi-layer wiring substrate can be formed in a short number of production days and at a high production yield.

[Brief description of the drawings]

FIG. 1 shows a first structure of a polyimide multilayer wiring board according to the present invention.
Illustrating the embodiment of

FIG. 2 shows a first embodiment of the manufacturing method of the present invention in the order of the manufacturing steps.

FIG. 3 illustrates a first embodiment of the manufacturing method of the present invention in the order of the manufacturing steps.

FIG. 4 illustrates a first embodiment of the manufacturing method of the present invention in the order of the manufacturing steps.

FIG. 5 illustrates a second embodiment of the manufacturing method of the present invention in the order of the manufacturing steps.

FIG. 6 illustrates a second embodiment of the manufacturing method of the present invention in the order of the manufacturing steps.

FIG. 7 illustrates a second embodiment of the manufacturing method of the present invention in the order of the manufacturing steps.

FIG. 8 illustrates a third embodiment of the manufacturing method of the present invention in the order of the manufacturing steps.

FIG. 9 illustrates a third embodiment of the manufacturing method of the present invention in the order of the manufacturing steps.

FIG. 10 illustrates a third embodiment of the manufacturing method of the present invention in the order of the manufacturing steps.

FIG. 11 illustrates a second embodiment of the structure of the polyimide multilayer wiring board of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 I / O pin 12 Ceramic substrate 13 Grounding and connection wiring layer 14 Polyimide insulating layer 15 Signal wiring layer 16 Metal bump 17 Anisotropic conductive film 18 Ceramic plate or hard organic resin plate with through holes 19 Pitch adjusting layer 110 LSI connection pad 111 Block 21 Ceramic Plate with Through Hole 22 Grounding and Connection Wiring Layer 23 Polyimide Insulation Layer 24 Via Hole 25 Signal Wiring Layer 26 Connection Metal Bump 27 Ceramic Substrate 28 Anisotropic Conductive Film 29 LSI Connection Pad 210 Input / Output Pin 31 Through Hard organic resin plate with hole 32 Grounding and connection wiring layer 33 Polyimide insulating layer 34 Via hole 35 Signal wiring layer 36 Connection via hole 37 Exclusive metal bump 38 Ceramic substrate 39 Anisotropic conductive film 310 LSI connection pad 311 I / O pin 41 Hard organic resin plate with through hole 42 Grounding and connection wiring layer 43 Polyimide insulating layer 44 Via hole 45 Signal wiring layer 46 Connection via hole 47 Exclusive metal bump 48 Ceramic substrate 49 Anisotropically conductive Functional film 410 LSI connection pad 411 I / O pin 51 I / O pin 52 Hard organic resin substrate 53 Grounding and connection wiring layer 54 Polyimide insulating layer 55 Signal wiring layer 56 Metal bump 57 Anisotropic conductive film 58 Ceramic plate with through hole or Hard organic resin plate 59 Pitch adjustment layer 510 LSI connection pad 511 block

Claims (6)

(57) [Claims] 1. A plurality of the block layer polyimide multilayer wiring formed on an insulating substrate, a material obtained by forming a plurality of polyimide wiring layers on the front and rear of the insulator plate having a conductive layer inside as a single block A multilayer structure in which electrical connection and bonding between the respective blocks are performed by an anisotropic conductive film sandwiched between the respective blocks. 2. The polyimide multilayer wiring board according to claim 1, wherein the insulator plate having a conductor layer inside is a ceramic plate or a hard organic resin plate. 3. The polyimide multilayer wiring board according to claim 2, wherein the insulator substrate is a ceramic substrate or a hard organic resin substrate. 4. A polyimide multilayer wiring layer is formed on the front and back of a ceramic plate or a hard organic resin plate having a conductor layer inside, and via-holes are formed on the surface of each of the polyimide multilayer wiring layers formed on the front and back thereof. To form metal bumps electrically connected to the internal wiring layer, and to form a polyimide multilayer wiring layer on a ceramic substrate or a hard organic resin substrate, and to form a via hole on the surface of the polyimide multilayer wiring layer in the same manner as above. A ceramic substrate formed by forming a metal bump electrically connected to an internal wiring layer through a ceramic substrate having a conductive layer inside or a polyimide multi-layer wiring layer on the back surface of a hard organic resin plate formed by Or, after aligning with the surface of the polyimide wiring layer on the hard organic resin substrate with an anisotropic conductive film between them, Under thermal conditions, the polyimide surface of the polyimide multilayer wiring layer formed with the polyimide surface of the polyimide multilayer wiring layer formed by bonding with the adhesive force of the adhesive layer of the anisotropic conductive film, and simultaneously facing metal bumps By crushing the conductive particles in the anisotropic conductive film, the layers are electrically connected to each other, and then the polyimide layer on the surface of the ceramic plate or the hard organic resin plate having a conductive layer inside is laminated. The metal bumps formed on the polyimide surface of the layer wiring layer, and the metal bumps on the polyimide surface of the polyimide multilayer wiring layer on the back surface of the ceramic plate or the hard organic resin plate having another conductor layer formed inside by another method formed in the same manner. Further lamination is performed in the same manner as above, and the above process is repeated a plurality of times. And forming a multilayer wiring layer comprising a ceramic plate or a hard organic resin plate having a conductor layer therein. 5. A polyimide multilayer wiring layer is formed on the front and back of a ceramic plate or a hard organic resin plate having a conductor layer inside, and via a via hole is formed on the surface of each of the polyimide multilayer wiring layers formed on the front side thereof. Form a metal bump electrically connected to the internal wiring layer, and on the back side a polyimide with a metal part on the bottom that is electrically connected to the internal wiring layer via via holes on the surface of the polyimide multilayer wiring layer A via hole is formed, and a polyimide multilayer wiring layer is formed on a ceramic substrate or a hard organic resin substrate. Similarly, the surface of the polyimide multilayer wiring layer is electrically connected to an internal wiring layer via the via hole. Form the connected metal bumps and form with the polyimide surface of the polyimide multilayer wiring layer on the back of the ceramic plate or the hard organic resin plate with the conductor layer inside formed by After positioning and superposing the surface of the polyimide wiring layer on the ceramic substrate or the hard organic resin substrate with an anisotropic conductive film between them, the polyimide The polyimide surface of the multilayer wiring layer formed with the polyimide surface of the multilayer wiring layer is bonded by the adhesive force of the adhesive layer of the anisotropic conductive film, and at the same time, the metal and the metal bump on the bottom of the via hole are anisotropically conductive. By crushing the conductive particles in the film, the laminated structures are electrically connected to each other, and then the metal formed on the polyimide surface of the polyimide multilayer wiring layer on the surface of the ceramic plate having a conductive layer inside the laminated structure Bump and the polyimide surface of the polyimide multilayer wiring layer on the back of the ceramic plate or hard organic resin plate having a conductor layer inside another formed by the same method as Via holes are further laminated in the same manner as described above, and by repeating the above steps a plurality of times, a ceramic substrate or a hard organic resin plate having polyimide and a conductor layer inside inside on a ceramic substrate or a hard organic resin substrate A method for manufacturing a polyimide multilayer wiring board, comprising forming a multilayer wiring layer. 6. A polyimide multilayer wiring layer is formed on the front and back of a ceramic plate or a hard organic resin plate having a conductor layer inside, and via a via hole is formed on the surface of each of the polyimide multilayer wiring layers formed on the front side thereof. Form a polyimide via hole on the bottom with a metal part electrically connected to the internal wiring layer on the bottom, and electrically connect to the internal wiring layer via the via hole on the surface of the polyimide multilayer wiring layer on the back side Metal bumps are formed, and a polyimide multi-layer wiring layer is formed on a ceramic substrate or a hard organic resin substrate. Similarly, the surface of the polyimide multi-layer wiring layer is electrically connected to an internal wiring layer via via holes. Form a polyimide via hole with a connected metal part on the bottom and form a polyimide layer on the back of a ceramic plate or a hard organic resin plate with a conductor layer inside formed by After aligning the surface of the polyimide wiring layer on the ceramic substrate formed with the polyimide surface of the wire layer and the surface of the polyimide wiring layer with an anisotropic conductive film between them, The polyimide surface of the formed polyimide multilayer wiring layer is bonded to the polyimide surface of the formed polyimide multilayer wiring layer by the adhesive force of the adhesive layer of the anisotropic conductive film, and at the same time, the metal of the metal bump and the bottom surface of the via hole are bonded together. Crushes the conductive particles in the anisotropic conductive film, thereby electrically connecting between the laminated structures, and then the polyimide surface of the polyimide multilayer wiring layer on the surface of the ceramic plate having a conductor layer inside the laminated structure Via hole formed in the above, and a polyimide multi-layer wiring layer on the back surface of a ceramic plate or a hard organic resin plate having a conductor layer in another inside formed by the same method as By further laminating the metal bumps on the surface of the polyimide in the same manner as in the above, by repeating the above steps a plurality of times, a ceramic plate or a hard organic resin plate having polyimide and a conductor layer inside on a ceramic substrate or a hard organic resin substrate A method for manufacturing a polyimide multilayer wiring board, comprising: forming a multilayer wiring layer comprising: