JP3192925B2 - Serial data converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data converter for converting an input signal of serial data into a signal of a different protocol or the like.

[0002]

2. Description of the Related Art When transmitting serial data, the protocol may be different between the transmitting and receiving apparatuses. In such a case, a serial data converter for performing protocol conversion between the two devices is required.

FIG. 6 is a block diagram of a conventional general serial data converter. In FIG. 1, serial data input to an input interface unit 1 is converted by a data conversion unit 2 and output from an output interface unit 3.

According to this serial data conversion device, after inputting serial data (denoted by A) of a predetermined protocol (denoted by a) and performing conversion processing of a protocol such as a data format by the data conversion unit 2, The data is output as it is from the output interface unit 3 as serial data (denoted by B) of another protocol (denoted by b). Therefore, the output timing of the serial data B depends on the processing speed and the internal timing of the serial data converter.

FIG. 7 is a timing chart showing an example of an input / output operation in the serial data converter of FIG. As shown in the figure, of the serial data A input at a cycle ta, for example, input data _An is output as output data _Bn after a data conversion time _tw1 . Further, the input data A _{n + 1} becomes the output data B after the data conversion time t _w2.
Output as _{n + 1} .

[0006]

According to the conventional serial data conversion device, there are mainly two problems.

(1) The output becomes asynchronous Even if the serial input data A is input to the input interface unit 1 at a timing cycle (t _a ) synchronized with the correct time, the serial data B is not transferred from the correct time to the data reception time. and data conversion time (t _wn) is the resulting output through a normally output period t _bn will not match the t _a. Further, the period also fluctuates according to the ever-changing conversion time.

(2) A Conversion Delay Occurs The output data is delayed with respect to the input data because the data conversion time ( _twn ) is necessary. However, in practice, for example, when a rocket is tracked by controlling a radar based on output data, a real-time property is required for the serial data converter.

In view of these problems, an object of the present invention is to provide a serial data conversion device which adjusts the output timing of converted data to perform time synchronization and compensates for delay due to data conversion. .

[0010]

According to the present invention, there is provided a serial data conversion apparatus comprising: an input interface means for inputting serial data; a data conversion means for applying a predetermined conversion to the input serial data ; data
Output interface that outputs data as serial data
And the output cycle of the output interface means is constant.
So that the input serial data is
Key to adjust the internal hold time, which is the total time held
Adjusting means .

The present invention further comprises a setting means for setting the predetermined holding time when the value to be taken for the internal holding time is defined as a predetermined holding time.

The present invention further comprises means for measuring time, and in another aspect, means for externally inputting time.

According to the present invention, while the input serial data is held in the apparatus, the serial data to be subsequently input is predicted, and the input data is corrected according to the prediction result. Means.

[0014]

In the serial data converter of the present invention, serial data is input and firstly, a predetermined conversion is performed. Before or after that, the total time (internal holding time) during which the input serial data is held inside the device is manipulated, and the data output timing is adjusted. Thereafter, the data is output as serial data.

In the present invention, a predetermined holding time is set as a value to be taken for the internal holding time. The internal holding time of each input serial data is expanded so as to uniformly match the predetermined holding time.

In the present invention, the output timing is adjusted based on the measured time, and in another aspect, the output timing is adjusted based on the time inputted from outside.

Further, according to the present invention, while the input serial data is held in the apparatus, the serial data to be input next is predicted, and the data already in the apparatus is approximated to the prediction result. Is corrected.

At this time, the next data is predicted by a first-order extrapolation based on the change of two serial data input continuously.

In another aspect, the least squares method is applied to changes in three or more input serial data, and the next data is predicted.

[0020]

[Embodiment 1 ] Preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of the serial data converter according to the first embodiment. In the figure, the same reference numerals are given to the same components as those in the related art, and the description is omitted. The new configuration in the first embodiment is as follows.

(1) Input data is corrected by a method described later,
The delay time compensator 4 for compensating for the conversion delay (2) The elapsed time from the input time of the serial data to the output time, that is, the total time during which the data is held in the serial data converter in some form is referred to as “internal holding time” A predetermined holding time setting unit 5 that sets a desired time (hereinafter, referred to as “predetermined holding time”) as this time. (3) The actual internal holding time is set so that the internal holding time matches the predetermined holding time. An internal holding time adjusting unit 6 that adjusts and generates an output timing signal 20 (4) an output timing adjusting unit 7 that permits output of converted data by using the output timing signal 20 as a trigger. It is assumed that the predetermined holding time by the setting unit 5 is set to t. The predetermined holding time can be easily set, changed, and fine-tuned by a switch. That is, when this switch is realized by hardware, the time may be specified by a rotary switch or a dip switch, and when realized by software, the time can be specified by setting a value in a register.

First, the operation of the configuration excluding the delay time compensating unit 4 will be described. (It is assumed that the data passes through the delay time compensator 4.) The data converter 2 performs protocol conversion such as format on the serial input data A of the protocol a input from the input interface 1. At this time, the internal holding time adjusting section 6 extends the time so that the internal holding time of any of the input data coincides with the predetermined holding time t.
0 is output to the output timing adjustment unit 7. Therefore, the predetermined holding time t should be set so as to exceed the maximum value of the delay time inevitably generated such as the conversion delay.

On the other hand, the output timing adjusting section 7 outputs data to the output interface section 3 in response to the output timing signal 20. The output timing adjustment unit 7 may be, for example, a flip-flop circuit using the output timing signal 20 as a clock. Thereafter, the output interface unit 3 outputs the serial data B of the protocol b.

FIG. 2 is a timing chart showing an example of the input / output operation of the first embodiment. Of serial data A inputted at the period ta, for example, an input data A _n it is outputted as the output data B _n after protocol conversion by the delay time t _w. Further, the converted input Kadeta A _{n + 1} is similarly protocol is output after the delay time tw as output data B _{n + 1.} This tw is the predetermined holding time t, which is constant, so that the output cycle of the serial data B is the same as the input cycle of the serial data A, and the synchronous relationship is maintained.
Thus, the problem (1) can be solved by adjusting the internal holding time.

Next, the operation of the delay time compensator 4 will be described.

The delay time compensating unit 4 predicts a change to be generated in the input data (in other words, predicts the next input data).
Then, the data being processed in the apparatus is corrected, and the apparent internal holding time is set to zero. That is, since it is considered that the input data changes while the data is held internally, a change expected from the state of the change before that is added to the data after the protocol conversion, thereby eliminating the influence of the delay. The compensated data is supplied to the output timing adjustment unit 7.

FIG. 3 is a diagram showing a delay compensation operation in the first embodiment. Here, the change is predicted by the simplest linear extrapolation approximation. That is, if the input data A is continuous data that changes with time and the input data valid at the time T _n is A _n , the input data A is first converted to the data conversion unit 2.
In A _n 'is converted to, subsequently, Δ = A _n' 'the A _n' -A _n-1 addition, this is the predicted value B _{n + 1} in T _{n + 1.} In FIG. 3, B _{n + 1} is on the tangent connecting _An ′ and _An−1 ′. To this end, the delay time compensating unit 4 includes a memory for temporarily storing two serial data that are continuously input, a subtractor for calculating a difference Δ between these data,
And an adder for adding this difference to A _n '.

Since such an correction eliminates an apparent delay, compensation for the delay time (T _n -T _{n -1} ) is realized. Output completion timing of the output data B _n is to match the time T _n, the output timing is adjusted. As a result of the delay compensation, the above-mentioned problem (2) can be solved.

Although the first-order approximation is used in this embodiment,
It may be predicted to B _n by the least square method from 3 or more A _i. In this case, a memory having a large capacity may be provided as the memory, and an arithmetic unit for performing least square calculation may be provided instead of the subtractor.

Embodiment 2 FIG . In the first embodiment, the data output timing is adjusted so that the internal holding time is constant.
In the second embodiment, the timing is adjusted by an internal clock for measuring time. That is, in the second embodiment, the same effect as in the first embodiment is obtained by outputting the converted data in synchronization with the time of the internal clock. Embodiment 2 aims at compensation of delay time.

FIG. 4 is a configuration diagram of a serial data converter according to the second embodiment. The new configuration in the figure is an internal clock 8 whose time has been correctly adjusted, and an internal holding time calculator 9 that calculates an internal holding time actually applied from data input to data output. Others are the same as the first embodiment.

In FIG. 3, the output timing of the converted data is synchronized with a fixed time by the internal clock 8,
The output timing signal 20 is output to the output timing adjustment unit 7. The internal holding time calculator 9 calculates the actual internal holding time from the data input time and the output time indicated by the internal clock 8, and outputs it to the delay time compensator 4. Here, in order to cancel the internal holding time, the same compensation as in the first embodiment is performed on the converted data, and the compensated data is output to the output timing adjustment unit 7. The output timing adjusting unit 7 sends data to the output interface unit 3 triggered by the output timing signal 20 notified from the internal clock 8.

FIG. 5 is a timing chart showing an example of the input / output operation of the second embodiment. Of the serial data A,
For example, the input data A _n is output as the data B _n at time T ₀ is converted protocol. Also, input data A _{n + 1}
Is similarly converted and output as data B _{n + 1} at time T ₁ . At this time, the output timing of the serial data B is synchronized with the normal time Tn, and does not depend on the input timing of the serial data A.

In the present embodiment, the output timing is adjusted by the internal clock 8. However, an external time signal capable of notifying at regular intervals may be used instead. In this case, an external time interface unit (not shown) for inputting an external time signal may be provided instead of the internal clock 8 in FIG.
In particular, when the serial data converter already has an interrupt timer (PIT), a real-time clock (RTC), and the like, the realization of this configuration is easy and efficient.

[0036]

As described above, according to the present invention, the converted data is compensated for the conversion delay and output at the same timing as the input data.
No need to consider changes in interface timing, etc.
The converted data, which is the output data of the serial data converter, can be handled in the same way as the pre-conversion data.

According to the serial data converter of the present invention, the output timing of data is adjusted, so that the output can be synchronized. This is convenient when a device that requires time synchronization of converted data is connected to the subsequent stage.

Further, according to the present invention, since the predetermined holding time can be set, data conversion can be performed in accordance with the specifications of the device connected at the subsequent stage.

According to the present invention, the output can be synchronized by the timekeeping means of the apparatus, so that the synchronization accuracy is high.

In another aspect, the output timing is adjusted based on the time inputted from the outside, so that the present apparatus itself does not need to have time measuring means, which contributes to simplification of design.

Further, according to the present invention, since an apparent delay time can be eliminated by correcting data, the present invention is most suitable for a serial data converter requiring real-time performance.

At this time, a change in data can be predicted only by a change in two serial data input continuously, which facilitates design.

In another aspect, a change in data is predicted from a change in three or more input serial data, so that the prediction accuracy is high.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a serial data conversion device according to a first embodiment.

FIG. 2 is a timing chart illustrating an example of an input / output operation according to the first embodiment.

FIG. 3 is a diagram illustrating an example of a delay compensation operation according to the first embodiment.

FIG. 4 is a configuration diagram of a serial data conversion device according to a second embodiment.

FIG. 5 is a timing chart illustrating an input / output operation according to the second embodiment.

FIG. 6 is a configuration diagram of a conventional general serial data converter.

7 is a timing chart showing an example of an input / output operation in the serial data converter of FIG.

[Explanation of symbols]

1 input interface unit, 2 data conversion unit, 3 output interface unit, 4 delay time compensating unit, 5 predetermined holding time setting unit, 6 internal holding time adjusting unit, 7 output timing adjusting unit, 8 internal clock, 9 internal holding time calculation Department,
10 External time interface unit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 7/00 H03M 7/00

Claims (7)

(57) [Claims] An input interface means for inputting serial data, a data conversion means for applying a predetermined conversion to the input serial data, and a data after the data conversion.
Output interface that outputs data as serial data
Means and the output cycle of the output interface means are constant
So that the input serial data is
Adjust the internal hold time, which is the total time held in
A serial data conversion device comprising an adjustment unit . 2. The serial data conversion device according to claim 1, wherein when a desired value to be taken by said internal holding time is defined as a predetermined holding time, said device has a setting means for setting said predetermined holding time. A serial data conversion device, wherein the adjusting means extends the internal holding time of each input serial data so that the time uniformly matches the predetermined holding time. 3. The serial data converter according to claim 1, further comprising means for measuring a time, wherein said adjusting means stores an internal time based on the measured time.
A serial data converter for adjusting the holding time . 4. The serial data converter according to claim 1, further comprising means for externally inputting a time, wherein said adjusting means adjusts the internal holding time based on the input time . A serial data converter. 5. The serial data conversion device according to claim 1, wherein said serial data conversion device further comprises:
A serial data conversion apparatus comprising: a correcting unit that predicts serial data to be subsequently input and corrects already input data according to the prediction result. 6. The serial data conversion device according to claim 5, wherein said correction means performs prediction by linear extrapolation based on a change in two serial data input continuously. Characteristic serial data converter. 7. The serial data converter according to claim 5, wherein the correction means performs prediction by applying a least squares method to a change of three or more input serial data. Serial data converter.