JP2959505B2 - Data transmission circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission circuit, and more particularly to a data transmission circuit for transmitting data to a plurality of lines in synchronization with time.

[0002]

2. Description of the Related Art Conventionally, a data transmission circuit for transmitting data in synchronization with time has been used for compensating the phase between multiple stations in a pager phase compensator or using a digital communication circuit. This is used for performing time synchronization control in data transmission performed by JP-A-8-88612. In the data transmission circuit described in the latter publication, in a television automatic program control device,
In the middle of a program supplied in real time from another station, the timing of switching and transmitting the replacement video information of the own station and the timing of returning to the program supplied from another station after transmitting the replacement video information of the own station are generated. Set based on time information generated by the device.

[0003]

However, in the above-mentioned conventional data transmission circuit, the oscillator provided inside is also inexpensive (in order to reduce the cost of the device itself in which the data transmission circuit is incorporated). (About a normal crystal oscillator)
Is used, the stability of the oscillator output is low,
Since the configuration is such that a large number of counts are performed using the output clock, the synchronization accuracy of the output data is poor. As a result, when applied to a pager system, the phase between multiple stations cannot be compensated with high accuracy.

In the above-mentioned conventional data transmission circuit,
In order to adjust the output timing, a counter for counting the input reference signal for one cycle is required, and thus there is a problem that the circuit scale is large.

[0005] The present invention has been made in view of the above points,
By outputting the time information and the reference clock from the time information generator, and outputting the time information a little before the time when the data is actually output, the circuit scale can be reduced regardless of the variation in the stability of the internal oscillator. It is an object to provide a data transmission circuit that can be reduced.

Another object of the present invention is to provide a data transmission circuit capable of transmitting data input from a plurality of lines in a timely synchronized manner with a simple device configuration.

[0007]

In order to achieve the above object, the present invention provides an input unit for detecting a frame number from input data including a frame number, a memory for temporarily storing input data from the input unit, Time information output means for generating and outputting time information including a frame number, a timing pulse synchronized with a change in the value of the frame number, and a reference clock having a frequency higher than the frequency of the timing pulse in accordance with a clock using the global positioning system And generating a first address signal corresponding to the frame number of the input data input from the input unit, storing the input data from the input unit in the memory, and generating the first address signal based on the output signal of the time information output unit. Control means for reading the data stored in the memory in response to the address signal (2); It is obtained by the configuration and output means for delivering the output signal of the timing pulse and the reference clock and the control means in synchronism with the timing pulse and the reference clock from.

In the present invention, the time information, the timing pulse and the reference clock output from the time information output means are generated using the global positioning system (GPS), so that they have higher precision than a normal crystal oscillator. Using the time information, the timing pulse, and the reference clock, the input data can be output in synchronization with the timing pulse and the reference clock.

Further, according to the present invention, the time information output means is means for outputting a reference clock having the same frequency as the transmission speed of the data transmitted from the output means together with the time information and the timing pulse, and the control means is inputted from an input unit. Generating a first address signal corresponding to the frame number of the input data, storing the input data from the input unit in a memory, using a timing pulse from the time information output means as a trigger,
A central processing unit for reading time information and reading data stored in a memory by a second address signal generated corresponding to the frame number; and outputting a reference clock from a timing pulse input point in time from the time information output means. The circuit comprises a counter for outputting a timing control signal by counting a predetermined constant number, and an output unit for outputting data from the memory in accordance with the timing control signal from the counter.

According to the present invention, the time information can be output at a timing earlier than the timing at which the data is transmitted from the output unit, by a slight period until the reference clock is counted by a predetermined constant number after the input of the timing pulse.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data transmission circuit according to the present invention. This embodiment includes a time information output circuit 1 and an output data synchronization circuit 2. The time information output circuit 1 is a global positioning system (G
PS) and a highly stable oscillator mounted therein, and outputs a time information, a timing pulse, and a reference clock as a reference to an output data synchronization circuit 2.
Output to

The output data synchronizing circuit 2 comprises a central processing unit (CPU) 3, an input unit 4, a memory 5, an output unit 6, and a timing adjustment counter unit 7. The input data is input to the input unit 4, and the control of the CPU 3 is performed. After the input data is temporarily held by the memory 5, the data is output from the memory 5 via the output unit. The timing adjustment counter unit 7 counts the reference clock input from the time information output circuit 1 and adjusts the timing of the output unit 6 based on the count result.

FIG. 2 is a time chart showing signals at various parts in FIG. The time information output circuit 1 shown in FIG.
2B, the timing pulse shown in FIG. 2B, and the reference clock shown in FIG. 2C are generated and input to the output data synchronization circuit 2. FIG. 2D shows the input unit 4.
2 (E) shows the output data output from the output unit 6, and FIG. 2 (F) shows the output timing of the output unit 6 controlled by the timing adjustment counter unit 7. The output timing of the output unit 6 is, as shown in FIG. 2F, input from the time information output circuit 1 in FIG.
Is delayed by the time T1 as compared with the timing pulse of (1).

Next, the operation of the embodiment of FIG. 1 will be described with reference to the timing chart of FIG. The time information output circuit 1 generates the time information shown in FIG. 2A, the timing pulse shown in FIG. 2B synchronized with the time information, and the reference clock shown in FIG. It is input to the data synchronization circuit 2.

On the other hand, when the input data shown in FIG. 2D is input to the input unit 4, the input unit 4 detects the frame information and outputs it to the CPU 3. The CPU 3 inputs the write address signal generated in accordance with the input frame information to the memory 5 and stores the data extracted from the input unit 4 in the memory 5. Next, the CPU 3 reads the time information (FIG. 2A) input from the time information output circuit 1 using the timing pulse shown in FIG. 2B input from the time information output circuit 1 as a trigger. Then, the data in the memory 5 corresponding to the frame number is searched, a read address signal is generated and supplied to the memory 5, and the data is output from the memory 5 to the output unit 6.

The timing adjustment counter section 7 supplies a reference clock input from the time information output circuit 1 (FIG. 2C).
Is counted based on the timing pulse (FIG. 2B) and the output timing signal from the CPU 3, and based on this, a timing signal is output to the output unit 6 and the data is output as shown in FIG.
Output at the timing shown in (F). Here, data synchronized with the time information (FIG. 2A) from the time information output circuit 1 with a phase relationship delayed by the time T1 is output as shown in FIG. 2E.

Next, the relationship between the timing pulse shown in FIG. 2B, the reference clock shown in FIG. 2C, and the output timing shown in FIG. 2F will be described in more detail with reference to FIG. The CPU 3 starts the process at time T2 when the timing pulse shown in FIG. 3B output from the time information output circuit 1 is input, and ends the process at time T3. The time from the time T2 to T3 is the maximum processing time of the CPU 3. The CPU 3 reads the time information (FIG. 2A) by the timing pulse from the time information output circuit 1 within this maximum processing time, and searches for the data to be output from the data stored in the memory 5. , Output processing of data stored in the memory 5, and the like.

The output unit 6 operates from time T3 shown in FIG.
Transmission bit processing is performed for a period up to 4. Times T3 and T
The timing control of 4 and the timing control to the output unit 6 are performed by the timing adjustment counter unit 7. The timing adjustment counter unit 7 outputs a timing pulse (FIG. 2B, FIG.
(B)), the reference clock (FIGS. 2C and 3C), and the output control signal from the CPU 3, and controls the output unit 6 for the timing of transmission bit processing.

The above-mentioned transmission bit processing is performed by the timing adjustment counter unit 7 at a count value determined based on the reference clock (FIG. 2C, FIG. 3C). The timing adjustment counter unit 7 starts counting the reference clock from time T2 when the timing pulse is input at time T2, and counts the reference clock by a predetermined count required for the transmission bit processing time at time T4. Outputs the output timing signal. This makes it possible to always send data from the output unit 6 at time T4 as shown in FIG.

In this embodiment, the synchronization data output from the output data synchronization circuit 2 is based on the reference clock (FIG. 2C, FIG. 3C) input from the time information output circuit 1 after the maximum processing time of the CPU 3 has elapsed. Since (C)) is transmitted at the timing of counting a certain number, it is possible to realize high-precision synchronization accuracy in accordance with the stability of the reference clock output from the time information output circuit 1.

Also, the time (T
4-T2) Since the time information, the timing pulse, and the reference clock are input from the time information output circuit 1 to the output data synchronization circuit 2 earlier by the time (that is, the time T1 in FIG. 2), the circuit configuration becomes smaller. Data can be output with high accuracy. In particular, in the timing adjustment counter unit 7, since the time (T4−T2) may be obtained by counting with the reference clock, the circuit scale can be reduced.

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing a data transmission circuit according to a second embodiment of the present invention. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. FIG.
In the output data synchronization circuit 8 ₁ to 8 _N of N are respectively the same configuration, for example, the same structure as the output data synchronization circuit 2 of FIG. 1, the time information from said each time information output circuit 1, and the timing pulses A reference clock is commonly input.

On the other hand, the output data synchronization circuit 8 ₁ to 8 _N as input data, a channel (ch) 1~chN input data #. 1 to # N of the input separately. This gives c
Output data synchronization circuit 8 ₁ to 8 _N of h1~chN is input to the input data #. 1 to # N separately, temporarily stores the input data into the memory together with the read frame information included in the input data, time information Based on the time information, timing pulse and reference clock input from the output circuit 1,
The data of the frame number synchronized with the frame number of the time information is output.

Therefore, input data # 1 to input data #N
Time information but asynchronously, even if they are input to the output data synchronization circuit 8 ₁ to 8 _N provided corresponding, from the output data synchronization circuit 8 ₁ to 8 _N, which is input from the time information output circuit 1 And data synchronized with each other. When a large number of channels are configured as in this embodiment, the simple configuration of the timing adjustment counter unit 7 is more effective in the entire system.

[0026]

Next, embodiments of the present invention will be described with reference to the drawings. The time information output circuit 1 shown in FIG. 1 includes a highly stable oscillator therein, and generates time information, a timing pulse, and a reference clock synchronized with GPS. In the pager system, since the frame structure of the output data is defined at 1.875 seconds, the timing pulse output from the time information output circuit 1 is a pulse signal at 1.875 seconds. For time information,
The frame information is counted every 1.875 seconds, and is synchronized with the time. For example, 0 minutes 15 seconds every hour is 7 frames (1.875 seconds × 7 = 15 seconds). The reference clock is a transmission speed of data to be actually output.
6400 Hz which is the same as 400 Hz.

The output data synchronization circuit 2 shown in FIG. 1 reads input data (for example, a call signal from a central office in the case of a pager system) by the input section 4 and outputs a frame number included in the input data to the CPU 3 as described above. I do.
The CPU 3 generates a write address according to the input frame number, supplies the write address to the memory 5, and causes the memory 5 to write the input data. Here, the CPU 3 in the output data synchronizing circuit 2 starts processing using the timing pulse at an interval of 1.875 seconds input from the time information output circuit 1 as an interrupt signal. The CPU 3 detects the interrupt signal and reads the next input frame number from the time information.

Next, the CPU 3 searches whether data to be output at the time of the read frame number is stored in the memory 5, and reads out the data from the memory 3 when the data is stored in the memory 5. The processing of the CPU 3 so far must be the maximum time (T3-T2) shown in FIG. It is necessary to determine the maximum processing time in advance. By setting the maximum time of the CPU processing to be shorter, the number of counts counted by the timing adjustment counter unit 7 can be reduced, and a smaller circuit can be configured.

As a method of shortening the CPU processing time, one frame of data is not output to an output buffer or the like at a time, but data is output in units of 8 bits by exchanging flags with hardware. Is the way. In this case, the CPU processing time (T3−T2) from the input of the timing pulse can be shortened, whereby the number of counts in the period from time T2 to time T4 counted by the timing adjustment counter unit 7 can be reduced. ,
The configuration of the timing adjustment counter unit 7 can be made smaller.

In this embodiment, it is necessary to convert the 8-bit parallel data output from the memory 5 to serial data and output it. However, the count for converting the 8-bit parallel data to serial data is always Since it is constant, the timing for outputting data can be adjusted accurately.

The output section 6 starts counting the reference clock after the timing adjustment counter section 7 receives the timing pulse, and performs an initial process relating to data output from the CPU 3 while counting up to a predetermined count number. Thereafter, a process of converting 8-bit parallel data into serial data is performed, and data to be output is output according to a reference clock. These timing adjustments are performed by the timing adjustment counter unit 7. The timing adjustment counter unit 7 counts the clock based on the reference clock input from the time information output circuit 1, based on the timing pulse and the output control from the CPU 3, and outputs the parallel / serial conversion timing to the output unit 6. Perform control.

Therefore, in the timing adjustment counter section 7, since the reference clock needs to be counted a fixed number from the timing pulse to the output timing, the time information output circuit 1 outputs the timing pulse slightly before the output timing. As a result, the count number of the timing adjustment counter unit 7 can be reduced, so that data can be output in synchronization with the reference signal with a small circuit configuration.

The transmission speed of the output data is 640.
When the frequency is 0 Hz, and when the frequency of the reference clock is 6400 Hz, which is the same as the transmission speed, there is no need to perform a count process for dividing the reference clock to the transmission speed of the output data. Since the number can be minimized, a small-scale circuit configuration can be achieved. Further, since the 6400 Hz reference clock output from the time information output circuit 1 is a clock synchronized with GPS, it is a highly stable and highly accurate clock,
The timing adjustment counter unit 7 is based on the reference clock.
Operates and controls the output unit 6, so that synchronized data can be output with high accuracy.

[0034]

As described above, according to the present invention,
The use of GPS generates time information, timing pulses, and a reference clock with higher precision than a normal crystal oscillator, and outputs input data in synchronization with the timing pulse and the reference clock. , Data synchronized with the timing pulse and the reference clock can be transmitted.

Further, according to the present invention, the time information is output at a timing earlier than the timing at which the data is transmitted from the output unit, by a slight period until the reference clock is counted by a predetermined constant number after the input of the timing pulse. Since the number of counts of the counter means for adjusting the timing can be reduced, the circuit configuration of the output means can be realized on a small scale. Furthermore, by setting the reference clock output from the time information output means to the same frequency as the transmission speed of the output data, the number of counts of the count means can be minimized, thereby reducing the circuit configuration. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a timing chart of signals of respective units in FIG.

FIG. 3 is a timing chart illustrating an operation of a main part of FIG. 1;

FIG. 4 is a block diagram of a second embodiment of the present invention.

[Explanation of symbols]

1 time information output circuit 2, 8 ₁ to 8 _N output data synchronizing circuit 3 central processing unit (CPU) 4 input unit 5 memory 6 output section 7 timing adjustment counter

Claims (3)

(57) [Claims] An input unit for detecting the frame number from input data including a frame number; a memory for temporarily storing the input data from the input unit; time information including the frame number; A timing pulse synchronized with the change of the value, a time information output means for generating and outputting a reference clock having a higher frequency than the frequency of the timing pulse in accordance with a clock using the global positioning system; and A first address signal corresponding to a frame number of input data is generated, input data from the input unit is stored in the memory, and a second address signal generated based on an output signal of the time information output unit is used. Control means for reading data stored in the memory; and time information output means for reading data read from the memory. Data transmission circuit, characterized in that from a et of timing pulses and the reference clock and the output signal of the control means and an output means for delivering in synchronization with the timing pulse and the reference clock. 2. A plurality of output data synchronization circuits each comprising said input section, memory, control means and output means, are provided in parallel, and different input data are input to respective input sections in said plurality of output data synchronization circuits. 2. A data transmission circuit according to claim 1, wherein said time information, timing pulse and reference clock are commonly input to said plurality of output data synchronization circuits from said time information output means. 3. The time information output means is means for outputting the reference clock having the same frequency as the transmission rate of data transmitted from the output means together with the time information and the timing pulse. A first address signal corresponding to a frame number of the input data input from the unit is generated, the input data from the input unit is stored in the memory, and the timing pulse from the time information output unit is used as a trigger. A central processing unit that reads the time information and reads data stored in the memory by the second address signal generated in accordance with the frame number; and the output unit includes the timing pulse from the time information output unit. A counter that outputs a timing control signal by counting a predetermined constant number of the reference clock from an input time point Motor means and the data transmission circuit according to claim 1, wherein the more becomes possible output unit for outputting data from the memory by the timing control signal from said counter means.